brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

Merge branch 'sf' of git://git.denx.de/u-boot-blackfin

Browse Source 
* 'sf' of git://git.denx.de/u-boot-blackfin:
  sf: spansion: inline useless id defines
  sf: drop unused/duplicate command defines

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2012-07-20 08:58:06 +02:00
commit ad8439d464
8 changed files with 23 additions and 97 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/mtd/spi/eon.c
View File

@ -11,17 +11,8 @@
#include "spi_flash_internal.h"
/* EN25Q128-specific commands */
#define CMD_EN25Q128_WREN 0x06 /* Write Enable */
#define CMD_EN25Q128_WRDI 0x04 /* Write Disable */
#define CMD_EN25Q128_RDSR 0x05 /* Read Status Register */
#define CMD_EN25Q128_WRSR 0x01 /* Write Status Register */
#define CMD_EN25Q128_READ 0x03 /* Read Data Bytes */
#define CMD_EN25Q128_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
#define CMD_EN25Q128_PP 0x02 /* Page Program */
#define CMD_EN25Q128_SE 0x20 /* Sector Erase */
#define CMD_EN25Q128_BE 0xd8 /* Block Erase */
#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */
#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */
struct eon_spi_flash_params {
u8 idcode1;

11
drivers/mtd/spi/macronix.c
View File

@ -36,18 +36,9 @@
#include "spi_flash_internal.h"
/* MX25xx-specific commands */
#define CMD_MX25XX_WREN 0x06 /* Write Enable */
#define CMD_MX25XX_WRDI 0x04 /* Write Disable */
#define CMD_MX25XX_RDSR 0x05 /* Read Status Register */
#define CMD_MX25XX_WRSR 0x01 /* Write Status Register */
#define CMD_MX25XX_READ 0x03 /* Read Data Bytes */
#define CMD_MX25XX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
#define CMD_MX25XX_PP 0x02 /* Page Program */
#define CMD_MX25XX_SE 0x20 /* Sector Erase */
#define CMD_MX25XX_BE 0xD8 /* Block Erase */
#define CMD_MX25XX_CE 0xc7 /* Chip Erase */
#define CMD_MX25XX_DP 0xb9 /* Deep Power-down */
#define CMD_MX25XX_RES 0xab /* Release from DP, and Read Signature */
struct macronix_spi_flash_params {
u16 idcode;
@ -128,7 +119,7 @@ static int macronix_write_status(struct spi_flash *flash, u8 sr)
return ret;
}
cmd = CMD_MX25XX_WRSR;
cmd = CMD_WRITE_STATUS;
ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &sr, 1);
if (ret) {
debug("SF: fail to write status register\n");

23
drivers/mtd/spi/ramtron.c
View File

@ -54,19 +54,6 @@
#include <spi_flash.h>
#include "spi_flash_internal.h"
/* RAMTRON commands common to all devices */
#define CMD_RAMTRON_WREN 0x06 /* Write Enable */
#define CMD_RAMTRON_WRDI 0x04 /* Write Disable */
#define CMD_RAMTRON_RDSR 0x05 /* Read Status Register */
#define CMD_RAMTRON_WRSR 0x01 /* Write Status Register */
#define CMD_RAMTRON_READ 0x03 /* Read Data Bytes */
#define CMD_RAMTRON_WRITE 0x02 /* Write Data Bytes */
/* not all have those: */
#define CMD_RAMTRON_FSTRD 0x0b /* Fast Read (for compatibility - not used here) */
#define CMD_RAMTRON_SLEEP 0xb9 /* Enter Sleep Mode */
#define CMD_RAMTRON_RDID 0x9f /* Read ID */
#define CMD_RAMTRON_SNR 0xc3 /* Read Serial Number */
/*
* Properties of supported FRAMs
* Note: speed is currently not used because we have no method to deliver that
@ -196,7 +183,7 @@ static int ramtron_common(struct spi_flash *flash,
return ret;
}
if (command == CMD_RAMTRON_WRITE) {
if (command == CMD_PAGE_PROGRAM) {
/* send WREN */
ret = spi_flash_cmd_write_enable(flash);
if (ret < 0) {
@ -206,7 +193,7 @@ static int ramtron_common(struct spi_flash *flash,
}
/* do the transaction */
if (command == CMD_RAMTRON_WRITE)
if (command == CMD_PAGE_PROGRAM)
ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, buf, len);
else
ret = spi_flash_cmd_read(flash->spi, cmd, cmd_len, buf, len);
@ -223,14 +210,14 @@ static int ramtron_read(struct spi_flash *flash,
u32 offset, size_t len, void *buf)
{
return ramtron_common(flash, offset, len, buf,
CMD_RAMTRON_READ);
CMD_READ_ARRAY_SLOW);
}
static int ramtron_write(struct spi_flash *flash,
u32 offset, size_t len, const void *buf)
{
return ramtron_common(flash, offset, len, (void *)buf,
CMD_RAMTRON_WRITE);
CMD_PAGE_PROGRAM);
}
static int ramtron_erase(struct spi_flash *flash, u32 offset, size_t len)
@ -270,7 +257,7 @@ struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode)
* We COULD have a non JEDEC conformant FRAM here,
* read the status register to verify
*/
ret = spi_flash_cmd(spi, CMD_RAMTRON_RDSR, &sr, 1);
ret = spi_flash_cmd(spi, CMD_READ_STATUS, &sr, 1);
if (ret)
return NULL;

44
drivers/mtd/spi/spansion.c
View File

@ -32,28 +32,8 @@
#include "spi_flash_internal.h"
/* S25FLxx-specific commands */
#define CMD_S25FLXX_READ 0x03 /* Read Data Bytes */
#define CMD_S25FLXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
#define CMD_S25FLXX_READID 0x90 /* Read Manufacture ID and Device ID */
#define CMD_S25FLXX_WREN 0x06 /* Write Enable */
#define CMD_S25FLXX_WRDI 0x04 /* Write Disable */
#define CMD_S25FLXX_RDSR 0x05 /* Read Status Register */
#define CMD_S25FLXX_WRSR 0x01 /* Write Status Register */
#define CMD_S25FLXX_PP 0x02 /* Page Program */
#define CMD_S25FLXX_SE 0xd8 /* Sector Erase */
#define CMD_S25FLXX_BE 0xc7 /* Bulk Erase */
#define CMD_S25FLXX_DP 0xb9 /* Deep Power-down */
#define CMD_S25FLXX_RES 0xab /* Release from DP, and Read Signature */
#define SPSN_ID_S25FL008A 0x0213
#define SPSN_ID_S25FL016A 0x0214
#define SPSN_ID_S25FL032A 0x0215
#define SPSN_ID_S25FL064A 0x0216
#define SPSN_ID_S25FL128P 0x2018
#define SPSN_EXT_ID_S25FL128P_256KB 0x0300
#define SPSN_EXT_ID_S25FL128P_64KB 0x0301
#define SPSN_EXT_ID_S25FL032P 0x4d00
#define SPSN_EXT_ID_S25FL129P 0x4d01
struct spansion_spi_flash_params {
u16 idcode1;
@ -66,7 +46,7 @@ struct spansion_spi_flash_params {
static const struct spansion_spi_flash_params spansion_spi_flash_table[] = {
{
.idcode1 = SPSN_ID_S25FL008A,
.idcode1 = 0x0213,
.idcode2 = 0,
.page_size = 256,
.pages_per_sector = 256,
@ -74,7 +54,7 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = {
.name = "S25FL008A",
},
{
.idcode1 = SPSN_ID_S25FL016A,
.idcode1 = 0x0214,
.idcode2 = 0,
.page_size = 256,
.pages_per_sector = 256,
@ -82,7 +62,7 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = {
.name = "S25FL016A",
},
{
.idcode1 = SPSN_ID_S25FL032A,
.idcode1 = 0x0215,
.idcode2 = 0,
.page_size = 256,
.pages_per_sector = 256,
@ -90,7 +70,7 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = {
.name = "S25FL032A",
},
{
.idcode1 = SPSN_ID_S25FL064A,
.idcode1 = 0x0216,
.idcode2 = 0,
.page_size = 256,
.pages_per_sector = 256,
@ -98,32 +78,32 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = {
.name = "S25FL064A",
},
{
.idcode1 = SPSN_ID_S25FL128P,
.idcode2 = SPSN_EXT_ID_S25FL128P_64KB,
.idcode1 = 0x2018,
.idcode2 = 0x0301,
.page_size = 256,
.pages_per_sector = 256,
.nr_sectors = 256,
.name = "S25FL128P_64K",
},
{
.idcode1 = SPSN_ID_S25FL128P,
.idcode2 = SPSN_EXT_ID_S25FL128P_256KB,
.idcode1 = 0x2018,
.idcode2 = 0x0300,
.page_size = 256,
.pages_per_sector = 1024,
.nr_sectors = 64,
.name = "S25FL128P_256K",
},
{
.idcode1 = SPSN_ID_S25FL032A,
.idcode2 = SPSN_EXT_ID_S25FL032P,
.idcode1 = 0x0215,
.idcode2 = 0x4d00,
.page_size = 256,
.pages_per_sector = 256,
.nr_sectors = 64,
.name = "S25FL032P",
},
{
.idcode1 = SPSN_ID_S25FL128P,
.idcode2 = SPSN_EXT_ID_S25FL129P,
.idcode1 = 0x2018,
.idcode2 = 0x4d01,
.page_size = 256,
.pages_per_sector = 256,
.nr_sectors = 256,

2
drivers/mtd/spi/spi_flash_internal.h
View File

@ -17,8 +17,8 @@
#define CMD_READ_ARRAY_SLOW 0x03
#define CMD_READ_ARRAY_FAST 0x0b
#define CMD_READ_ARRAY_LEGACY 0xe8
#define CMD_WRITE_STATUS 0x01
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
#define CMD_READ_STATUS 0x05

14
drivers/mtd/spi/sst.c
View File

@ -18,12 +18,6 @@
#include "spi_flash_internal.h"
#define CMD_SST_WREN 0x06 /* Write Enable */
#define CMD_SST_WRDI 0x04 /* Write Disable */
#define CMD_SST_RDSR 0x05 /* Read Status Register */
#define CMD_SST_WRSR 0x01 /* Write Status Register */
#define CMD_SST_READ 0x03 /* Read Data Bytes */
#define CMD_SST_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
#define CMD_SST_BP 0x02 /* Byte Program */
#define CMD_SST_AAI_WP 0xAD /* Auto Address Increment Word Program */
#define CMD_SST_SE 0x20 /* Sector Erase */
@ -137,7 +131,7 @@ sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
};
debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
spi_w8r8(flash->spi, CMD_SST_RDSR), buf, cmd[0], offset);
spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
ret = sst_enable_writing(flash);
if (ret)
@ -184,7 +178,7 @@ sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf)
for (; actual < len - 1; actual += 2) {
debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
spi_w8r8(flash->spi, CMD_SST_RDSR), buf + actual, cmd[0],
spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual, cmd[0],
offset);
ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
@ -232,13 +226,13 @@ sst_unlock(struct spi_flash *flash)
if (ret)
return ret;
cmd = CMD_SST_WRSR;
cmd = CMD_WRITE_STATUS;
status = 0;
ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &status, 1);
if (ret)
debug("SF: Unable to set status byte\n");
debug("SF: sst: status = %x\n", spi_w8r8(flash->spi, CMD_SST_RDSR));
debug("SF: sst: status = %x\n", spi_w8r8(flash->spi, CMD_READ_STATUS));
return ret;
}

8
drivers/mtd/spi/stmicro.c
View File

@ -34,16 +34,8 @@
#include "spi_flash_internal.h"
/* M25Pxx-specific commands */
#define CMD_M25PXX_WREN 0x06 /* Write Enable */
#define CMD_M25PXX_WRDI 0x04 /* Write Disable */
#define CMD_M25PXX_RDSR 0x05 /* Read Status Register */
#define CMD_M25PXX_WRSR 0x01 /* Write Status Register */
#define CMD_M25PXX_READ 0x03 /* Read Data Bytes */
#define CMD_M25PXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
#define CMD_M25PXX_PP 0x02 /* Page Program */
#define CMD_M25PXX_SE 0xd8 /* Sector Erase */
#define CMD_M25PXX_BE 0xc7 /* Bulk Erase */
#define CMD_M25PXX_DP 0xb9 /* Deep Power-down */
#define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */
struct stmicro_spi_flash_params {

9
drivers/mtd/spi/winbond.c
View File

@ -11,18 +11,9 @@
#include "spi_flash_internal.h"
/* M25Pxx-specific commands */
#define CMD_W25_WREN 0x06 /* Write Enable */
#define CMD_W25_WRDI 0x04 /* Write Disable */
#define CMD_W25_RDSR 0x05 /* Read Status Register */
#define CMD_W25_WRSR 0x01 /* Write Status Register */
#define CMD_W25_READ 0x03 /* Read Data Bytes */
#define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
#define CMD_W25_PP 0x02 /* Page Program */
#define CMD_W25_SE 0x20 /* Sector (4K) Erase */
#define CMD_W25_BE 0xd8 /* Block (64K) Erase */
#define CMD_W25_CE 0xc7 /* Chip Erase */
#define CMD_W25_DP 0xb9 /* Deep Power-down */
#define CMD_W25_RES 0xab /* Release from DP, and Read Signature */
struct winbond_spi_flash_params {
uint16_t id;