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https://github.com/brain-hackers/u-boot-brain
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ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 1
Move code around to get rid of the forward declaration. No change to the actual code. Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut
parent
a386a50eb2
commit
ad64769ce0
@ -80,10 +80,6 @@ struct gbl_type *gbl;
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struct param_type *param;
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uint32_t curr_shadow_reg;
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static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
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uint32_t write_group, uint32_t use_dm,
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uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
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static void set_failing_group_stage(uint32_t group, uint32_t stage,
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uint32_t substage)
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{
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@ -1036,6 +1032,207 @@ static void rw_mgr_mem_handoff(void)
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*/
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}
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/*
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* issue write test command.
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* two variants are provided. one that just tests a write pattern and
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* another that tests datamask functionality.
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*/
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static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
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uint32_t test_dm)
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{
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uint32_t mcc_instruction;
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uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
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ENABLE_SUPER_QUICK_CALIBRATION);
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uint32_t rw_wl_nop_cycles;
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uint32_t addr;
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/*
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* Set counter and jump addresses for the right
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* number of NOP cycles.
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* The number of supported NOP cycles can range from -1 to infinity
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* Three different cases are handled:
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*
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* 1. For a number of NOP cycles greater than 0, the RW Mgr looping
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* mechanism will be used to insert the right number of NOPs
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*
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* 2. For a number of NOP cycles equals to 0, the micro-instruction
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* issuing the write command will jump straight to the
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* micro-instruction that turns on DQS (for DDRx), or outputs write
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* data (for RLD), skipping
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* the NOP micro-instruction all together
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*
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* 3. A number of NOP cycles equal to -1 indicates that DQS must be
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* turned on in the same micro-instruction that issues the write
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* command. Then we need
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* to directly jump to the micro-instruction that sends out the data
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*
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* NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
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* (2 and 3). One jump-counter (0) is used to perform multiple
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* write-read operations.
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* one counter left to issue this command in "multiple-group" mode
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*/
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rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
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if (rw_wl_nop_cycles == -1) {
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/*
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* CNTR 2 - We want to execute the special write operation that
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* turns on DQS right away and then skip directly to the
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* instruction that sends out the data. We set the counter to a
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* large number so that the jump is always taken.
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*/
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writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
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/* CNTR 3 - Not used */
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if (test_dm) {
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mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
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writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
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&sdr_rw_load_jump_mgr_regs->load_jump_add2);
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writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
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&sdr_rw_load_jump_mgr_regs->load_jump_add3);
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} else {
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mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
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writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
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&sdr_rw_load_jump_mgr_regs->load_jump_add2);
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writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
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&sdr_rw_load_jump_mgr_regs->load_jump_add3);
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}
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} else if (rw_wl_nop_cycles == 0) {
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/*
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* CNTR 2 - We want to skip the NOP operation and go straight
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* to the DQS enable instruction. We set the counter to a large
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* number so that the jump is always taken.
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*/
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writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
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/* CNTR 3 - Not used */
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if (test_dm) {
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mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
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writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
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&sdr_rw_load_jump_mgr_regs->load_jump_add2);
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} else {
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mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
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writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
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&sdr_rw_load_jump_mgr_regs->load_jump_add2);
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}
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} else {
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/*
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* CNTR 2 - In this case we want to execute the next instruction
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* and NOT take the jump. So we set the counter to 0. The jump
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* address doesn't count.
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*/
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writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
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writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
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/*
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* CNTR 3 - Set the nop counter to the number of cycles we
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* need to loop for, minus 1.
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*/
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writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
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if (test_dm) {
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mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
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writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
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&sdr_rw_load_jump_mgr_regs->load_jump_add3);
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} else {
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mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
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writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
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&sdr_rw_load_jump_mgr_regs->load_jump_add3);
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}
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}
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writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
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RW_MGR_RESET_READ_DATAPATH_OFFSET);
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if (quick_write_mode)
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writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
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else
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writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
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writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
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/*
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* CNTR 1 - This is used to ensure enough time elapses
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* for read data to come back.
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*/
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writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
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if (test_dm) {
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writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
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&sdr_rw_load_jump_mgr_regs->load_jump_add1);
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} else {
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writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
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&sdr_rw_load_jump_mgr_regs->load_jump_add1);
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}
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addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
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writel(mcc_instruction, addr + (group << 2));
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}
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/* Test writes, can check for a single bit pass or multiple bit pass */
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static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
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uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
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uint32_t *bit_chk, uint32_t all_ranks)
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{
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uint32_t r;
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uint32_t correct_mask_vg;
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uint32_t tmp_bit_chk;
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uint32_t vg;
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uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
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(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
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uint32_t addr_rw_mgr;
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uint32_t base_rw_mgr;
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*bit_chk = param->write_correct_mask;
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correct_mask_vg = param->write_correct_mask_vg;
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for (r = rank_bgn; r < rank_end; r++) {
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if (param->skip_ranks[r]) {
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/* request to skip the rank */
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continue;
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}
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/* set rank */
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set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
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tmp_bit_chk = 0;
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addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
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for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
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/* reset the fifos to get pointers to known state */
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writel(0, &phy_mgr_cmd->fifo_reset);
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tmp_bit_chk = tmp_bit_chk <<
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(RW_MGR_MEM_DQ_PER_WRITE_DQS /
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RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
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rw_mgr_mem_calibrate_write_test_issue(write_group *
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RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
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use_dm);
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base_rw_mgr = readl(addr_rw_mgr);
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tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
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if (vg == 0)
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break;
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}
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*bit_chk &= tmp_bit_chk;
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}
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if (all_correct) {
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set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
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debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
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%u => %lu", write_group, use_dm,
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*bit_chk, param->write_correct_mask,
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(long unsigned int)(*bit_chk ==
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param->write_correct_mask));
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return *bit_chk == param->write_correct_mask;
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} else {
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set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
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debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
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write_group, use_dm, *bit_chk);
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debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
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(long unsigned int)(*bit_chk != 0));
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return *bit_chk != 0x00;
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}
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}
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/**
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* rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
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* @rank_bgn: Rank number
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@ -2682,207 +2879,6 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void)
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}
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}
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/*
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* issue write test command.
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* two variants are provided. one that just tests a write pattern and
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* another that tests datamask functionality.
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*/
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static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
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uint32_t test_dm)
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{
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uint32_t mcc_instruction;
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uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
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ENABLE_SUPER_QUICK_CALIBRATION);
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uint32_t rw_wl_nop_cycles;
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uint32_t addr;
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/*
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* Set counter and jump addresses for the right
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* number of NOP cycles.
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* The number of supported NOP cycles can range from -1 to infinity
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* Three different cases are handled:
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*
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* 1. For a number of NOP cycles greater than 0, the RW Mgr looping
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* mechanism will be used to insert the right number of NOPs
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*
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* 2. For a number of NOP cycles equals to 0, the micro-instruction
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* issuing the write command will jump straight to the
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* micro-instruction that turns on DQS (for DDRx), or outputs write
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* data (for RLD), skipping
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* the NOP micro-instruction all together
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*
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* 3. A number of NOP cycles equal to -1 indicates that DQS must be
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* turned on in the same micro-instruction that issues the write
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* command. Then we need
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* to directly jump to the micro-instruction that sends out the data
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*
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* NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
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* (2 and 3). One jump-counter (0) is used to perform multiple
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* write-read operations.
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* one counter left to issue this command in "multiple-group" mode
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*/
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rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
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if (rw_wl_nop_cycles == -1) {
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/*
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* CNTR 2 - We want to execute the special write operation that
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* turns on DQS right away and then skip directly to the
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* instruction that sends out the data. We set the counter to a
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* large number so that the jump is always taken.
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*/
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writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
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/* CNTR 3 - Not used */
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if (test_dm) {
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mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
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writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
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&sdr_rw_load_jump_mgr_regs->load_jump_add2);
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writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
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&sdr_rw_load_jump_mgr_regs->load_jump_add3);
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} else {
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mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
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writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
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&sdr_rw_load_jump_mgr_regs->load_jump_add2);
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writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
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&sdr_rw_load_jump_mgr_regs->load_jump_add3);
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}
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} else if (rw_wl_nop_cycles == 0) {
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/*
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* CNTR 2 - We want to skip the NOP operation and go straight
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* to the DQS enable instruction. We set the counter to a large
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* number so that the jump is always taken.
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*/
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writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
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/* CNTR 3 - Not used */
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if (test_dm) {
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mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
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writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
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&sdr_rw_load_jump_mgr_regs->load_jump_add2);
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} else {
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mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
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writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
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&sdr_rw_load_jump_mgr_regs->load_jump_add2);
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}
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} else {
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/*
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* CNTR 2 - In this case we want to execute the next instruction
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* and NOT take the jump. So we set the counter to 0. The jump
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* address doesn't count.
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*/
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writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
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writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
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/*
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* CNTR 3 - Set the nop counter to the number of cycles we
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* need to loop for, minus 1.
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*/
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writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
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if (test_dm) {
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mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
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writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
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&sdr_rw_load_jump_mgr_regs->load_jump_add3);
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} else {
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mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
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writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
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&sdr_rw_load_jump_mgr_regs->load_jump_add3);
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}
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}
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writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
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RW_MGR_RESET_READ_DATAPATH_OFFSET);
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if (quick_write_mode)
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writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
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else
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writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
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writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
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/*
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* CNTR 1 - This is used to ensure enough time elapses
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* for read data to come back.
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*/
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writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
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if (test_dm) {
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writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
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&sdr_rw_load_jump_mgr_regs->load_jump_add1);
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} else {
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writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
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&sdr_rw_load_jump_mgr_regs->load_jump_add1);
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}
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addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
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writel(mcc_instruction, addr + (group << 2));
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}
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/* Test writes, can check for a single bit pass or multiple bit pass */
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static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
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uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
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uint32_t *bit_chk, uint32_t all_ranks)
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{
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uint32_t r;
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uint32_t correct_mask_vg;
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uint32_t tmp_bit_chk;
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uint32_t vg;
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uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
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(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
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uint32_t addr_rw_mgr;
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uint32_t base_rw_mgr;
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*bit_chk = param->write_correct_mask;
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correct_mask_vg = param->write_correct_mask_vg;
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for (r = rank_bgn; r < rank_end; r++) {
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if (param->skip_ranks[r]) {
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/* request to skip the rank */
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continue;
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}
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/* set rank */
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set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
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tmp_bit_chk = 0;
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addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
|
||||
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
|
||||
/* reset the fifos to get pointers to known state */
|
||||
writel(0, &phy_mgr_cmd->fifo_reset);
|
||||
|
||||
tmp_bit_chk = tmp_bit_chk <<
|
||||
(RW_MGR_MEM_DQ_PER_WRITE_DQS /
|
||||
RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
|
||||
rw_mgr_mem_calibrate_write_test_issue(write_group *
|
||||
RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
|
||||
use_dm);
|
||||
|
||||
base_rw_mgr = readl(addr_rw_mgr);
|
||||
tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
|
||||
if (vg == 0)
|
||||
break;
|
||||
}
|
||||
*bit_chk &= tmp_bit_chk;
|
||||
}
|
||||
|
||||
if (all_correct) {
|
||||
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
|
||||
debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
|
||||
%u => %lu", write_group, use_dm,
|
||||
*bit_chk, param->write_correct_mask,
|
||||
(long unsigned int)(*bit_chk ==
|
||||
param->write_correct_mask));
|
||||
return *bit_chk == param->write_correct_mask;
|
||||
} else {
|
||||
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
|
||||
debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
|
||||
write_group, use_dm, *bit_chk);
|
||||
debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
|
||||
(long unsigned int)(*bit_chk != 0));
|
||||
return *bit_chk != 0x00;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* search_window() - Search for the/part of the window with DM/DQS shift
|
||||
* @search_dm: If 1, search for the DM shift, if 0, search for DQS shift
|
||||
|
||||
Loading…
Reference in New Issue
Block a user