ARM: MediaTek: Add support for MediaTek MT7622 SoC
Add support for MediaTek MT7622 SoC. This include the file that will initialize the SoC after boot and its device tree. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
This commit is contained in:
Sam Shih
Tom Rini
parent
ce0069ed95
commit
ac57e2b013
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@ -0,0 +1,29 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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&topckgen {
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u-boot,dm-pre-reloc;
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};
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&pericfg {
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u-boot,dm-pre-reloc;
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};
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&apmixedsys {
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u-boot,dm-pre-reloc;
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};
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&timer0 {
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u-boot,dm-pre-reloc;
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};
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&uart0 {
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u-boot,dm-pre-reloc;
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};
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&snfi {
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u-boot,dm-pre-reloc;
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};
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@ -0,0 +1,185 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt7622-clk.h>
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/ {
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compatible = "mediatek,mt7622";
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interrupt-parent = <&sysirq>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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clock-frequency = <1300000000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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clock-frequency = <1300000000>;
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};
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};
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snfi: snfi@1100d000 {
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compatible = "mediatek,mtk-snfi-spi";
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reg = <0x1100d000 0x2000>;
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clocks = <&pericfg CLK_PERI_NFI_PD>,
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<&pericfg CLK_PERI_SNFI_PD>;
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clock-names = "nfi_clk", "pad_clk";
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assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
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<&topckgen CLK_TOP_NFI_INFRA_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
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<&topckgen CLK_TOP_UNIVPLL2_D8>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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arm,cpu-registers-not-fw-configured;
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};
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timer0: timer@10004000 {
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compatible = "mediatek,timer";
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reg = <0x10004000 0x80>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&system_clk>;
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clock-names = "system-clk";
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};
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system_clk: dummy13m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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};
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infracfg: infracfg@10000000 {
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compatible = "mediatek,mt7622-infracfg",
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"syscon";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pericfg: pericfg@10002000 {
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compatible = "mediatek,mt7622-pericfg", "syscon";
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reg = <0x10002000 0x1000>;
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#clock-cells = <1>;
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};
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scpsys: scpsys@10006000 {
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compatible = "mediatek,mt7622-scpsys",
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"syscon";
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#power-domain-cells = <1>;
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reg = <0x10006000 0x1000>;
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interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
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infracfg = <&infracfg>;
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clocks = <&topckgen CLK_TOP_HIF_SEL>;
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clock-names = "hif_sel";
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};
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sysirq: interrupt-controller@10200620 {
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compatible = "mediatek,sysirq";
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reg = <0x10200620 0x20>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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};
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apmixedsys: apmixedsys@10209000 {
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compatible = "mediatek,mt7622-apmixedsys";
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reg = <0x10209000 0x1000>;
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#clock-cells = <1>;
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};
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topckgen: topckgen@10210000 {
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compatible = "mediatek,mt7622-topckgen";
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reg = <0x10210000 0x1000>;
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#clock-cells = <1>;
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};
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pinctrl: pinctrl@10211000 {
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compatible = "mediatek,mt7622-pinctrl";
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reg = <0x10211000 0x1000>;
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gpio: gpio-controller {
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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watchdog: watchdog@10212000 {
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compatible = "mediatek,wdt";
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reg = <0x10212000 0x800>;
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};
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gic: interrupt-controller@10300000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0x10310000 0x1000>,
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<0x10320000 0x1000>,
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<0x10340000 0x2000>,
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<0x10360000 0x2000>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,hsuart";
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reg = <0x11002000 0x400>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART0_PD>;
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clock-names = "baud", "bus";
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status = "disabled";
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assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
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};
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt7622-mmc";
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reg = <0x11230000 0x1000>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
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<&topckgen CLK_TOP_MSDC50_0_SEL>;
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clock-names = "source", "hclk";
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status = "disabled";
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};
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mmc1: mmc@11240000 {
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compatible = "mediatek,mt7622-mmc";
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reg = <0x11240000 0x1000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
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<&topckgen CLK_TOP_AXI_SEL>;
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clock-names = "source", "hclk";
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status = "disabled";
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};
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};
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@ -13,6 +13,14 @@ config MT8512
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choice
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prompt "MediaTek board select"
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config TARGET_MT7622
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bool "MediaTek MT7622 SoC"
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select ARM64
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help
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The MediaTek MT7622 is a ARM64-based SoC with a dual-core Cortex-A53.
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including UART, SPI, USB3.0, SD and MMC cards, NAND, SNFI, PWM, PCIe,
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Gigabit Ethernet, I2C, built-in Wi-Fi, and PCIe.
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config TARGET_MT7623
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bool "MediaTek MT7623 SoC"
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select CPU_V7A
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@ -63,6 +71,7 @@ config TARGET_MT8518
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endchoice
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source "board/mediatek/mt7622/Kconfig"
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source "board/mediatek/mt7623/Kconfig"
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source "board/mediatek/mt7629/Kconfig"
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source "board/mediatek/mt8512/Kconfig"
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@ -4,6 +4,7 @@ obj-y += cpu.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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obj-$(CONFIG_MT8512) += mt8512/
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obj-$(CONFIG_TARGET_MT7622) += mt7622/
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obj-$(CONFIG_TARGET_MT7623) += mt7623/
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obj-$(CONFIG_TARGET_MT7629) += mt7629/
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obj-$(CONFIG_TARGET_MT8516) += mt8516/
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-y += init.o
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@ -0,0 +1,51 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <asm/armv8/mmu.h>
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int print_cpuinfo(void)
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{
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printf("CPU: MediaTek MT7622\n");
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return 0;
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}
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int dram_init(void)
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{
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int ret;
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ret = fdtdec_setup_memory_banksize();
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if (ret)
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return ret;
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return fdtdec_setup_mem_size_base();
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}
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void reset_cpu(ulong addr)
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{
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psci_system_reset();
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}
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static struct mm_region mt7622_mem_map[] = {
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{
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/* DDR */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
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}, {
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.virt = 0x00000000UL,
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.phys = 0x00000000UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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0,
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}
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};
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struct mm_region *mem_map = mt7622_mem_map;
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