mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-30 16:40:44 +09:00
* Add dual ethernet support on PM826
* Add support for LXT971 PHY on PM826 * Patch by Tord Andersson, 16 Jan 2003: Fix flash sector count for TQM8xxL * Fix I2C EEPROM problem on ICU862 board (would only write the first 16 bytes out of each 32 byte block)
This commit is contained in:
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16
CHANGELOG
16
CHANGELOG
@ -1,5 +1,19 @@
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======================================================================
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======================================================================
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Changes since U-Boot 0.2.0:
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Changes since U-Boot 0.2.1:
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======================================================================
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* Add dual ethernet support on PM826
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* Add support for LXT971 PHY on PM826
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* Patch by Tord Andersson, 16 Jan 2003:
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Fix flash sector count for TQM8xxL
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* Fix I2C EEPROM problem on ICU862 board (would only write the first
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16 bytes out of each 32 byte block)
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======================================================================
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Changes for U-Boot 0.2.1:
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======================================================================
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======================================================================
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* Add support for V37 board
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* Add support for V37 board
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@ -72,20 +72,27 @@ const iop_conf_t iop_conf_tab[4][32] = {
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/* Port B configuration */
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* PB31 */
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/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */
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/* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* PB30 */
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/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */
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/* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* PB29 */
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/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */
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#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
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#ifdef CONFIG_ETHER_ON_FCC2
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#error "SCC1 conflicts with FCC2"
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#endif
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/* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
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/* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
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/* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* PB27 */
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#else
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/* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* PB26 */
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/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */
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/* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* PB25 */
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#endif
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/* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* PB24 */
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/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */
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/* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* PB23 */
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/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */
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/* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* PB22 */
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/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */
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/* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* PB21 */
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/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */
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/* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* PB20 */
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/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */
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/* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* PB19 */
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/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */
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/* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* PB18 */
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/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */
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/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */
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/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */
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/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */
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/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
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/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
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/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
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/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
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/* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
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/* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
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@ -119,9 +126,9 @@ const iop_conf_t iop_conf_tab[4][32] = {
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/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */
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/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */
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/* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */
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/* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */
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/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */
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/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */
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/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* PC20 */
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/* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */
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/* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* PC19 */
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/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */
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/* PC18 */ { 0, 1, 0, 0, 0, 0 }, /* PC18 */
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/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */
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/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
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/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
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/* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
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/* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
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/* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
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/* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
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@ -288,7 +288,7 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn
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*/
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*/
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contr_reg[0] = 0;
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contr_reg[0] = 0;
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for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) {
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for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) {
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if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 1)
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if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0)
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break; /* got ack */
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break; /* got ack */
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#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
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#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
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udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
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udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
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@ -40,40 +40,61 @@
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*/
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*/
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#include <common.h>
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#include <common.h>
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#include <malloc.h>
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#include <asm/cpm_8260.h>
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#include <asm/cpm_8260.h>
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#include <mpc8260.h>
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#include <mpc8260.h>
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#include <net.h>
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#include <command.h>
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#include <command.h>
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#include <config.h>
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#include <config.h>
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#include <net.h>
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#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET)
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#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
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defined(CONFIG_NET_MULTI)
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/*---------------------------------------------------------------------*/
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static struct ether_fcc_info_s
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#if (CONFIG_ETHER_INDEX == 1)
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{
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int ether_index;
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#define PROFF_ENET PROFF_FCC1
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int proff_enet;
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#define CPM_CR_ENET_SBLOCK CPM_CR_FCC1_SBLOCK
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ulong cpm_cr_enet_sblock;
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#define CPM_CR_ENET_SBLOCK CPM_CR_FCC1_SBLOCK
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ulong cpm_cr_enet_page;
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#define CPM_CR_ENET_PAGE CPM_CR_FCC1_PAGE
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ulong cmxfcr_mask;
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ulong cmxfcr_value;
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/*---------------------------------------------------------------------*/
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}
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#elif (CONFIG_ETHER_INDEX == 2)
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ether_fcc_info[] =
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{
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#define PROFF_ENET PROFF_FCC2
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#ifdef CONFIG_ETHER_ON_FCC1
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#define CPM_CR_ENET_SBLOCK CPM_CR_FCC2_SBLOCK
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{
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#define CPM_CR_ENET_PAGE CPM_CR_FCC2_PAGE
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0,
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PROFF_FCC1,
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/*---------------------------------------------------------------------*/
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CPM_CR_FCC1_SBLOCK,
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#elif (CONFIG_ETHER_INDEX == 3)
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CPM_CR_FCC1_PAGE,
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CFG_CMXFCR_MASK1,
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#define PROFF_ENET PROFF_FCC3
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CFG_CMXFCR_VALUE1
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#define CPM_CR_ENET_SBLOCK CPM_CR_FCC3_SBLOCK
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},
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#define CPM_CR_ENET_PAGE CPM_CR_FCC3_PAGE
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/*---------------------------------------------------------------------*/
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#else
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#error "FCC Ethernet not correctly defined"
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#endif
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#endif
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#ifdef CONFIG_ETHER_ON_FCC2
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{
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1,
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PROFF_FCC2,
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CPM_CR_FCC2_SBLOCK,
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CPM_CR_FCC2_PAGE,
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CFG_CMXFCR_MASK2,
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CFG_CMXFCR_VALUE2
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},
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#endif
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#ifdef CONFIG_ETHER_ON_FCC3
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{
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2,
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PROFF_FCC3,
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CPM_CR_FCC3_SBLOCK,
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CPM_CR_FCC3_PAGE,
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CFG_CMXFCR_MASK3,
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CFG_CMXFCR_VALUE3
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},
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#endif
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};
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/*---------------------------------------------------------------------*/
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/*---------------------------------------------------------------------*/
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/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
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/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
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@ -116,7 +137,7 @@ static RTXBD rtx __attribute__ ((aligned(8)));
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#error "rtx must be 64-bit aligned"
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#error "rtx must be 64-bit aligned"
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#endif
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#endif
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int eth_send(volatile void *packet, int length)
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static int fec_send(struct eth_device* dev, volatile void *packet, int length)
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{
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{
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int i;
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int i;
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int result = 0;
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int result = 0;
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@ -156,7 +177,7 @@ out:
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return result;
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return result;
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}
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}
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int eth_rx(void)
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static int fec_recv(struct eth_device* dev)
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{
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{
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int length;
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int length;
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@ -194,8 +215,9 @@ int eth_rx(void)
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}
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}
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int eth_init(bd_t *bis)
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static int fec_init(struct eth_device* dev, bd_t *bis)
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{
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{
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struct ether_fcc_info_s * info = dev->priv;
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int i;
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int i;
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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volatile cpm8260_t *cp = &(immr->im_cpm);
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volatile cpm8260_t *cp = &(immr->im_cpm);
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@ -210,18 +232,18 @@ int eth_init(bd_t *bis)
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/* 28.9 - (3): connect FCC's tx and rx clocks */
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/* 28.9 - (3): connect FCC's tx and rx clocks */
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immr->im_cpmux.cmx_uar = 0;
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immr->im_cpmux.cmx_uar = 0;
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immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~CFG_CMXFCR_MASK) |
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immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~info->cmxfcr_mask) |
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CFG_CMXFCR_VALUE;
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info->cmxfcr_value;
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/* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
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/* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
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immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_gfmr =
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immr->im_fcc[info->ether_index].fcc_gfmr =
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FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
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FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
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/* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */
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/* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */
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immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
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immr->im_fcc[info->ether_index].fcc_fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
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/* 28.9 - (6): FDSR: Ethernet Syn */
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/* 28.9 - (6): FDSR: Ethernet Syn */
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immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_fdsr = 0xD555;
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immr->im_fcc[info->ether_index].fcc_fdsr = 0xD555;
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/* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
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/* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
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rxIdx = 0;
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rxIdx = 0;
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@ -246,7 +268,7 @@ int eth_init(bd_t *bis)
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rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
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rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
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/* 28.9 - (7): initialise parameter ram */
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/* 28.9 - (7): initialise parameter ram */
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pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[PROFF_ENET]);
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pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[info->proff_enet]);
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/* clear whole structure to make sure all reserved fields are zero */
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/* clear whole structure to make sure all reserved fields are zero */
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memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
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memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
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@ -259,7 +281,7 @@ int eth_init(bd_t *bis)
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* can do this. Later, we will add resource management for
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* can do this. Later, we will add resource management for
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* this area.
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* this area.
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*/
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*/
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mem_addr = CPM_FCC_SPECIAL_BASE + ((CONFIG_ETHER_INDEX-1) * 64);
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mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
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pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
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pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
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pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
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pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
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/*
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/*
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@ -288,7 +310,7 @@ int eth_init(bd_t *bis)
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* it unique by setting a few bits in the upper byte of the
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* it unique by setting a few bits in the upper byte of the
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* non-static part of the address.
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* non-static part of the address.
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*/
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*/
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#define ea bis->bi_enetaddr
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#define ea eth_get_dev()->enetaddr
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pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
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pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
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pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
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pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
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pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
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pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
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@ -308,10 +330,10 @@ int eth_init(bd_t *bis)
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#endif
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#endif
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/* 28.9 - (8): clear out events in FCCE */
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/* 28.9 - (8): clear out events in FCCE */
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immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_fcce = ~0x0;
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immr->im_fcc[info->ether_index].fcc_fcce = ~0x0;
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/* 28.9 - (9): FCCM: mask all events */
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/* 28.9 - (9): FCCM: mask all events */
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immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_fccm = 0;
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immr->im_fcc[info->ether_index].fcc_fccm = 0;
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/* 28.9 - (10-12): we don't use ethernet interrupts */
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/* 28.9 - (10-12): we don't use ethernet interrupts */
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@ -321,8 +343,8 @@ int eth_init(bd_t *bis)
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* than the manual describes because we have just now finished
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* than the manual describes because we have just now finished
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* the BD initialization.
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* the BD initialization.
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*/
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*/
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cp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE,
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cp->cp_cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
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CPM_CR_ENET_SBLOCK,
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info->cpm_cr_enet_sblock,
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0x0c,
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0x0c,
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CPM_CR_INIT_TRX) | CPM_CR_FLG;
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CPM_CR_INIT_TRX) | CPM_CR_FLG;
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do {
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do {
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@ -330,18 +352,43 @@ int eth_init(bd_t *bis)
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} while (cp->cp_cpcr & CPM_CR_FLG);
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} while (cp->cp_cpcr & CPM_CR_FLG);
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/* 28.9 - (14): enable tx/rx in gfmr */
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/* 28.9 - (14): enable tx/rx in gfmr */
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immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
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immr->im_fcc[info->ether_index].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
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return 1;
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return 1;
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}
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}
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void eth_halt(void)
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static void fec_halt(struct eth_device* dev)
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{
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{
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struct ether_fcc_info_s * info = dev->priv;
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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||||||
/* write GFMR: disable tx/rx */
|
/* write GFMR: disable tx/rx */
|
||||||
immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_gfmr &=
|
immr->im_fcc[info->ether_index].fcc_gfmr &=
|
||||||
~(FCC_GFMR_ENT | FCC_GFMR_ENR);
|
~(FCC_GFMR_ENT | FCC_GFMR_ENR);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET */
|
int fec_initialize(bd_t *bis)
|
||||||
|
{
|
||||||
|
struct eth_device* dev;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
|
||||||
|
{
|
||||||
|
dev = (struct eth_device*) malloc(sizeof *dev);
|
||||||
|
memset(dev, 0, sizeof *dev);
|
||||||
|
|
||||||
|
sprintf(dev->name, "FCC%d ETHERNET",
|
||||||
|
ether_fcc_info[i].ether_index + 1);
|
||||||
|
dev->priv = ðer_fcc_info[i];
|
||||||
|
dev->init = fec_init;
|
||||||
|
dev->halt = fec_halt;
|
||||||
|
dev->send = fec_send;
|
||||||
|
dev->recv = fec_recv;
|
||||||
|
|
||||||
|
eth_register(dev);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */
|
||||||
|
@ -38,6 +38,8 @@
|
|||||||
#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
|
#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
|
||||||
#define CONFIG_PM826 1 /* ...on a PM8260 module */
|
#define CONFIG_PM826 1 /* ...on a PM8260 module */
|
||||||
|
|
||||||
|
#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
|
||||||
|
|
||||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||||
@ -93,33 +95,50 @@
|
|||||||
/*
|
/*
|
||||||
* select ethernet configuration
|
* select ethernet configuration
|
||||||
*
|
*
|
||||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
|
* if CONFIG_ETHER_ON_SCC is selected, then
|
||||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
|
* - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
|
||||||
* for FCC)
|
* - CONFIG_NET_MULTI must not be defined
|
||||||
|
*
|
||||||
|
* if CONFIG_ETHER_ON_FCC is selected, then
|
||||||
|
* - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
|
||||||
|
* - CONFIG_NET_MULTI must be defined
|
||||||
*
|
*
|
||||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
|
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
|
||||||
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
|
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
|
||||||
* from CONFIG_COMMANDS to remove support for networking.
|
* from CONFIG_COMMANDS to remove support for networking.
|
||||||
*/
|
*/
|
||||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
|
#define CONFIG_NET_MULTI
|
||||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
|
|
||||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */
|
#undef CONFIG_ETHER_NONE /* define if ether on something else */
|
||||||
#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
|
|
||||||
|
|
||||||
#if (CONFIG_ETHER_INDEX == 1)
|
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
|
||||||
|
#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */
|
||||||
|
|
||||||
|
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
|
||||||
/*
|
/*
|
||||||
* - Rx-CLK is CLK11
|
* - Rx-CLK is CLK11
|
||||||
* - Tx-CLK is CLK10
|
* - Tx-CLK is CLK10
|
||||||
|
*/
|
||||||
|
#define CONFIG_ETHER_ON_FCC1
|
||||||
|
# define CFG_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
|
||||||
|
#ifndef CONFIG_DB_CR826_J30x_ON
|
||||||
|
# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
|
||||||
|
#else
|
||||||
|
# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
|
||||||
|
#endif
|
||||||
|
/*
|
||||||
|
* - Rx-CLK is CLK15
|
||||||
|
* - Tx-CLK is CLK14
|
||||||
|
*/
|
||||||
|
#define CONFIG_ETHER_ON_FCC2
|
||||||
|
# define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
|
||||||
|
# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
|
||||||
|
/*
|
||||||
* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
|
* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
|
||||||
* - Enable Full Duplex in FSMR
|
* - Enable Full Duplex in FSMR
|
||||||
*/
|
*/
|
||||||
# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
|
|
||||||
# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
|
|
||||||
# define CFG_CPMFCR_RAMTYPE 0
|
# define CFG_CPMFCR_RAMTYPE 0
|
||||||
# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
|
# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
|
||||||
|
|
||||||
#endif /* CONFIG_ETHER_INDEX */
|
|
||||||
|
|
||||||
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
|
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
|
||||||
#define CONFIG_8260_CLKIN 64000000 /* in Hz */
|
#define CONFIG_8260_CLKIN 64000000 /* in Hz */
|
||||||
|
|
||||||
|
@ -178,7 +178,7 @@
|
|||||||
* FLASH organization
|
* FLASH organization
|
||||||
*/
|
*/
|
||||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||||
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
|
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
|
||||||
|
|
||||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||||
|
@ -170,7 +170,7 @@
|
|||||||
* FLASH organization
|
* FLASH organization
|
||||||
*/
|
*/
|
||||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||||
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
|
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
|
||||||
|
|
||||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||||
|
@ -170,7 +170,7 @@
|
|||||||
* FLASH organization
|
* FLASH organization
|
||||||
*/
|
*/
|
||||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||||
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
|
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
|
||||||
|
|
||||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||||
|
@ -170,7 +170,7 @@
|
|||||||
* FLASH organization
|
* FLASH organization
|
||||||
*/
|
*/
|
||||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||||
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
|
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
|
||||||
|
|
||||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||||
|
@ -18,6 +18,30 @@
|
|||||||
#define CONFIG_NET_MULTI
|
#define CONFIG_NET_MULTI
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if !defined(CONFIG_NET_MULTI) && defined(CONFIG_8260)
|
||||||
|
#include <config.h>
|
||||||
|
#if defined(CONFIG_ETHER_ON_FCC)
|
||||||
|
#if defined(CONFIG_ETHER_ON_SCC)
|
||||||
|
#error "Ethernet not correctly defined"
|
||||||
|
#endif /* CONFIG_ETHER_ON_SCC */
|
||||||
|
#define CONFIG_NET_MULTI
|
||||||
|
#if (CONFIG_ETHER_INDEX == 1)
|
||||||
|
#define CONFIG_ETHER_ON_FCC1
|
||||||
|
# define CFG_CMXFCR_MASK1 CFG_CMXFCR_MASK
|
||||||
|
# define CFG_CMXFCR_VALUE1 CFG_CMXFCR_VALUE
|
||||||
|
#elif (CONFIG_ETHER_INDEX == 2)
|
||||||
|
#define CONFIG_ETHER_ON_FCC2
|
||||||
|
# define CFG_CMXFCR_MASK2 CFG_CMXFCR_MASK
|
||||||
|
# define CFG_CMXFCR_VALUE2 CFG_CMXFCR_VALUE
|
||||||
|
#elif (CONFIG_ETHER_INDEX == 3)
|
||||||
|
#define CONFIG_ETHER_ON_FCC3
|
||||||
|
# define CFG_CMXFCR_MASK3 CFG_CMXFCR_MASK
|
||||||
|
# define CFG_CMXFCR_VALUE3 CFG_CMXFCR_VALUE
|
||||||
|
#endif /* CONFIG_ETHER_INDEX */
|
||||||
|
#endif /* CONFIG_ETHER_ON_FCC */
|
||||||
|
#endif /* !CONFIG_NET_MULTI && CONFIG_8260 */
|
||||||
|
|
||||||
#include <asm/byteorder.h> /* for nton* / ntoh* stuff */
|
#include <asm/byteorder.h> /* for nton* / ntoh* stuff */
|
||||||
|
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user