diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile index d6037c1c4d..2613730409 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/mpc8641hpcn/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS := $(BOARD).o oftree.o +OBJS := $(BOARD).o pixis.o oftree.o SOBJS := init.o $(LIB): $(OBJS) $(SOBJS) diff --git a/board/mpc8641hpcn/config.mk b/board/mpc8641hpcn/config.mk index 4bdceec4dc..989a40b015 100644 --- a/board/mpc8641hpcn/config.mk +++ b/board/mpc8641hpcn/config.mk @@ -1,5 +1,5 @@ # Copyright 2004 Freescale Semiconductor. -# Modified by Jeff Brown (jeffrey@freescale.com) +# Modified by Jeff Brown # # See file CREDITS for list of people who contributed to this # project. diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S index 4d555a509f..69954a81ac 100644 --- a/board/mpc8641hpcn/init.S +++ b/board/mpc8641hpcn/init.S @@ -1,6 +1,6 @@ /* * Copyright 2004 Freescale Semiconductor. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -36,11 +36,10 @@ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xf800_0000 0xf80f_ffff CCSRBAR 1M + * 0xf810_0000 0xf81f_ffff PIXIS 1M * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M * * Notes: @@ -60,7 +59,6 @@ #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) #define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff) -/*#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) */ #define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))) /* @@ -73,14 +71,20 @@ #define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) #define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff) -/*#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) */ #define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))) - #define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) - #define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) +#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) +#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) +#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#else +#define LAWBAR8 0 +#define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) +#endif - .section .bootpg, "ax" + .section .bootpg, "ax" .globl law_entry law_entry: lis r7,CFG_CCSRBAR@h @@ -104,8 +108,8 @@ law_entry: stwu r6, 0x20(r4) lis r6,LAWAR2@h - ori r6,r6,LAWAR2@l - stwu r6, 0x20(r5) + ori r6,r6,LAWAR2@l + stwu r6, 0x20(r5) /* LAWBAR3, LAWAR3 */ lis r6,LAWBAR3@h @@ -121,7 +125,7 @@ law_entry: ori r6,r6,LAWBAR4@l stwu r6, 0x20(r4) - lis r6,LAWAR4@h + lis r6,LAWAR4@h ori r6,r6,LAWAR4@l stwu r6, 0x20(r5) /* LAWBAR5, LAWAR5 */ @@ -151,5 +155,14 @@ law_entry: ori r6,r6,LAWAR7@l stwu r6, 0x20(r5) + /* LAWBAR8, LAWAR8 */ + lis r6,LAWBAR8@h + ori r6,r6,LAWBAR8@l + stwu r6, 0x20(r4) + + lis r6,LAWAR8@h + ori r6,r6,LAWAR8@l + stwu r6, 0x20(r5) + blr diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index d02a7eff3c..c6b2a5b3bf 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -1,6 +1,6 @@ /* * Copyright 2004 Freescale Semiconductor. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * (C) Copyright 2002 Scott McNutt @@ -25,6 +25,7 @@ */ #include +#include #include #include #include @@ -35,20 +36,23 @@ extern void ft_cpu_setup(void *blob, bd_t *bd); #endif +#include "pixis.h" + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif -extern long int spd_sdram(void); +#if defined(CONFIG_SPD_EEPROM) +#include "spd_sdram.h" +#endif -void local_bus_init(void); void sdram_init(void); long int fixed_sdram(void); int board_early_init_f (void) { - return 0; + return 0; } int checkboard (void) @@ -57,41 +61,34 @@ int checkboard (void) #ifdef CONFIG_PCI - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_pex_t *pex1 = &immap->im_pex1; + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_pex_t *pex1 = &immap->im_pex1; - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); - - if ((io_sel==2 || io_sel==3 || io_sel==5 \ - || io_sel==6 || io_sel==7 || io_sel==0xF) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ - debug ("PCI-EXPRESS 1: %s \n", - pex1_agent ? "Agent" : "Host"); - debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); - if (pex1->pme_msg_det) { - pex1->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x", - pex1->pme_msg_det); - } - debug ("\n"); - } else { - printf ("PCI-EXPRESS 1: Disabled\n"); - } + if ((io_sel == 2 || io_sel == 3 || io_sel == 5 + || io_sel == 6 || io_sel == 7 || io_sel == 0xF) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); + debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det); + if (pex1->pme_msg_det) { + pex1->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pex1->pme_msg_det); + } + debug ("\n"); + } else { + puts("PCI-EXPRESS 1: Disabled\n"); + } #else - printf("PCI-EXPRESS1: Disabled\n"); + puts("PCI-EXPRESS1: Disabled\n"); #endif - /* - * Initialize local bus. - */ - local_bus_init(); - return 0; } @@ -100,7 +97,6 @@ long int initdram(int board_type) { long dram_size = 0; - extern long spd_sdram (void); #if defined(CONFIG_SPD_EEPROM) dram_size = spd_sdram (); @@ -112,7 +108,7 @@ initdram(int board_type) puts(" DDR: "); return dram_size; #endif - + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. @@ -125,34 +121,6 @@ initdram(int board_type) } -/* - * Initialize Local Bus - */ - -void -local_bus_init(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; -} - #if defined(CFG_DRAM_TEST) int testdram(void) { @@ -160,7 +128,7 @@ int testdram(void) uint *pend = (uint *) CFG_MEMTEST_END; uint *p; - printf("SDRAM test phase 1:\n"); + puts("SDRAM test phase 1:\n"); for (p = pstart; p < pend; p++) *p = 0xaaaaaaaa; @@ -171,7 +139,7 @@ int testdram(void) } } - printf("SDRAM test phase 2:\n"); + puts("SDRAM test phase 2:\n"); for (p = pstart; p < pend; p++) *p = 0x55555555; @@ -182,7 +150,7 @@ int testdram(void) } } - printf("SDRAM test passed.\n"); + puts("SDRAM test passed.\n"); return 0; } #endif @@ -207,9 +175,9 @@ long int fixed_sdram(void) ddr->sdram_mode_1 = CFG_DDR_MODE_1; ddr->sdram_mode_2 = CFG_DDR_MODE_2; ddr->sdram_interval = CFG_DDR_INTERVAL; - ddr->sdram_data_init = CFG_DDR_DATA_INIT; + ddr->sdram_data_init = CFG_DDR_DATA_INIT; ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; - ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; + ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS; #if defined (CONFIG_DDR_ECC) @@ -217,7 +185,7 @@ long int fixed_sdram(void) ddr->err_sbe = 0x00ff0000; #endif asm("sync;isync"); - + udelay(500); #if defined (CONFIG_DDR_ECC) @@ -228,7 +196,7 @@ long int fixed_sdram(void) ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; #endif asm("sync; isync"); - + udelay(500); #endif return CFG_SDRAM_SIZE * 1024 * 1024; @@ -281,15 +249,113 @@ ft_board_setup(void *blob, bd_t *bd) int len; ft_cpu_setup(blob, bd); - + p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } - } #endif +void +mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char cmd; + ulong val; + ulong corepll; + /* + * No args is a simple reset request. + */ + if (argv <= 0) { + out8(PIXIS_BASE + PIXIS_RST, 0); + /* not reached */ + } + + cmd = argv[1][1]; + switch (cmd) { + case 'f': /* reset with frequency changed */ + if (argc < 5) + goto my_usage; + read_from_px_regs(0); + + val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10)); + + corepll = strfractoint(argv[3]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10)); + if (val == 3) { + puts("Setting registers VCFGEN0 and VCTL\n"); + read_from_px_regs(1); + puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); + set_px_go(); + } else + goto my_usage; + + while (1); /* Not reached */ + + case 'l': + if (argv[2][1] == 'f') { + read_from_px_regs(0); + read_from_px_regs_altbank(0); + /* reset with frequency changed */ + val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10)); + + corepll = strfractoint(argv[4]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10)); + if (val == 3) { + puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs(1); + read_from_px_regs_altbank(1); + puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); + set_px_go_with_watchdog(); + } else + goto my_usage; + + while(1); /* Not reached */ + + } else if(argv[2][1] == 'd'){ + /* + * Reset from alternate bank without changing + * frequencies but with watchdog timer enabled. + */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + puts("Setting registers VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); + set_px_go_with_watchdog(); + while(1); /* Not reached */ + + } else { + /* + * Reset from next bank without changing + * frequency and without watchdog timer enabled. + */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + if(argc > 2) + goto my_usage; + puts("Setting registers VCFGNE1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + puts("Resetting board to boot from the other bank....\n"); + set_px_go(); + } + + default: + goto my_usage; + } + +my_usage: + puts("\nUsage: reset cf \n"); + puts(" reset altbank [cf ]\n"); + puts(" reset altbank [wd]\n"); + puts("For example: reset cf 40 2.5 10\n"); + puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); +} diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index ef28fc31eb..a11c321714 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -18,7 +18,7 @@ linux,phandle = <100>; cpus { - #cpus = <1>; + #cpus = <2>; #address-cells = <1>; #size-cells = <0>; linux,phandle = <200>; @@ -30,19 +30,32 @@ i-cache-line-size = <20>; // 32 bytes d-cache-size = <8000>; // L1, 32K i-cache-size = <8000>; // L1, 32K - timebase-frequency = <0>; // 33 MHz, from uboot - bus-frequency = <0>; // 166 MHz - clock-frequency = <0>; // 825 MHz, from uboot + timebase-frequency = <0>; // 33 MHz, from uboot + bus-frequency = <0>; // From uboot + clock-frequency = <0>; // From uboot 32-bit; linux,phandle = <201>; linux,boot-cpu; }; + PowerPC,8641@1 { + device_type = "cpu"; + reg = <1>; + d-cache-line-size = <20>; // 32 bytes + i-cache-line-size = <20>; // 32 bytes + d-cache-size = <8000>; // L1, 32K + i-cache-size = <8000>; // L1, 32K + timebase-frequency = <0>; // 33 MHz, from uboot + bus-frequency = <0>; // From uboot + clock-frequency = <0>; // From uboot + 32-bit; + linux,phandle = <202>; + }; }; memory { device_type = "memory"; linux,phandle = <300>; - reg = <00000000 10000000>; // 256M at 0x0 + reg = <00000000 40000000>; // 1G at 0x0 }; soc8641@f8000000 { @@ -63,6 +76,15 @@ dfsrr; }; + i2c@3100 { + device_type = "i2c"; + compatible = "fsl-i2c"; + reg = <3100 100>; + interrupts = <2b 0>; + interrupt-parent = <40000>; + dfsrr; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -73,28 +95,28 @@ ethernet-phy@0 { linux,phandle = <2452000>; interrupt-parent = <40000>; - interrupts = ; + interrupts = <3a 0>; reg = <0>; device_type = "ethernet-phy"; }; ethernet-phy@1 { linux,phandle = <2452001>; interrupt-parent = <40000>; - interrupts = ; + interrupts = <3a 0>; reg = <1>; device_type = "ethernet-phy"; }; ethernet-phy@2 { linux,phandle = <2452002>; interrupt-parent = <40000>; - interrupts = ; + interrupts = <3a 0>; reg = <2>; device_type = "ethernet-phy"; }; ethernet-phy@3 { linux,phandle = <2452003>; interrupt-parent = <40000>; - interrupts = ; + interrupts = <3a 0>; reg = <3>; device_type = "ethernet-phy"; }; @@ -154,8 +176,8 @@ serial@4500 { device_type = "serial"; compatible = "ns16550"; - reg = <4500 100>; // reg base, size - clock-frequency = <0>; // should we fill in in uboot? + reg = <4500 100>; + clock-frequency = <0>; interrupts = <2a 3>; interrupt-parent = <40000>; }; @@ -163,12 +185,120 @@ serial@4600 { device_type = "serial"; compatible = "ns16550"; - reg = <4600 100>; // reg base, size - clock-frequency = <0>; // should we fill in in uboot? - interrupts = <2a 3>; + reg = <4600 100>; + clock-frequency = <0>; + interrupts = <1c 3>; interrupt-parent = <40000>; }; + pci@8000 { + compatible = "86xx"; + device_type = "pci"; + linux,phandle = <8000>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <8000 1000>; + bus-range = <0 fe>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e2000000 0 00100000>; + clock-frequency = <1fca055>; + interrupt-parent = <40000>; + interrupts = <8 0>; + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x11 */ + 8800 0 0 1 40000 3 0 + 8800 0 0 2 40000 4 0 + 8800 0 0 3 40000 5 0 + 8800 0 0 4 40000 6 0 + + /* IDSEL 0x12 */ + 9000 0 0 1 40000 4 0 + 9000 0 0 2 40000 5 0 + 9000 0 0 3 40000 6 0 + 9000 0 0 4 40000 3 0 + + /* IDSEL 0x13 */ + 9800 0 0 1 40000 5 0 + 9800 0 0 2 40000 6 0 + 9800 0 0 3 40000 3 0 + 9800 0 0 4 40000 4 0 + + /* IDSEL 0x14 */ + a000 0 0 1 40000 6 0 + a000 0 0 2 40000 3 0 + a000 0 0 3 40000 4 0 + a000 0 0 4 40000 5 0 + + /* IDSEL 0x15 */ + a800 0 0 1 40000 0 0 + a800 0 0 2 40000 0 0 + a800 0 0 3 40000 0 0 + a800 0 0 4 40000 0 0 + + /* IDSEL 0x16 */ + b000 0 0 1 40000 0 0 + b000 0 0 2 40000 0 0 + b000 0 0 3 40000 0 0 + b000 0 0 4 40000 0 0 + + /* IDSEL 0x17 */ + b800 0 0 1 40000 0 0 + b800 0 0 2 40000 0 0 + b800 0 0 3 40000 0 0 + b800 0 0 4 40000 0 0 + + /* IDSEL 0x18 */ + c000 0 0 1 40000 0 0 + c000 0 0 2 40000 0 0 + c000 0 0 3 40000 0 0 + c000 0 0 4 40000 0 0 + + /* IDSEL 0x19 */ + c800 0 0 1 40000 0 0 + c800 0 0 2 40000 0 0 + c800 0 0 3 40000 0 0 + c800 0 0 4 40000 0 0 + + /* IDSEL 0x1a */ + d000 0 0 1 40000 0 0 + d000 0 0 2 40000 0 0 + d000 0 0 3 40000 0 0 + d000 0 0 4 40000 0 0 + + + /* IDSEL 0x1b */ + d800 0 0 1 40000 0 0 + d800 0 0 2 40000 0 0 + d800 0 0 3 40000 0 0 + d800 0 0 4 40000 0 0 + + /* IDSEL 0x1c */ + e000 0 0 1 40000 0 0 + e000 0 0 2 40000 0 0 + e000 0 0 3 40000 0 0 + e000 0 0 4 40000 0 0 + + /* IDSEL 0x1d */ + e800 0 0 1 40000 0 0 + e800 0 0 2 40000 0 0 + e800 0 0 3 40000 0 0 + e800 0 0 4 40000 0 0 + + /* IDSEL 0x1e */ + f000 0 0 1 40000 0 0 + f000 0 0 2 40000 0 0 + f000 0 0 3 40000 0 0 + f000 0 0 4 40000 0 0 + + /* IDSEL 0x1f */ + f800 0 0 1 40000 6 0 + f800 0 0 2 40000 6 0 + f800 0 0 3 40000 6 0 + f800 0 0 4 40000 6 0 + >; + }; pic@40000 { linux,phandle = <40000>; clock-frequency = <0>; diff --git a/board/mpc8641hpcn/pixis.c b/board/mpc8641hpcn/pixis.c new file mode 100644 index 0000000000..f226b3e8dd --- /dev/null +++ b/board/mpc8641hpcn/pixis.c @@ -0,0 +1,324 @@ +/* + * Copyright 2006 Freescale Semiconductor + * Jeff Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include "pixis.h" + + +/* + * Per table 27, page 58 of MPC8641HPCN spec. + */ +int set_px_sysclk(ulong sysclk) +{ + u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux; + + switch (sysclk) { + case 33: + sysclk_s = 0x04; + sysclk_r = 0x04; + sysclk_v = 0x07; + sysclk_aux = 0x00; + break; + case 40: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x20; + sysclk_aux = 0x01; + break; + case 50: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x2A; + sysclk_aux = 0x02; + break; + case 66: + sysclk_s = 0x01; + sysclk_r = 0x04; + sysclk_v = 0x04; + sysclk_aux = 0x03; + break; + case 83: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x4B; + sysclk_aux = 0x04; + break; + case 100: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x5C; + sysclk_aux = 0x05; + break; + case 134: + sysclk_s = 0x06; + sysclk_r = 0x1F; + sysclk_v = 0x3B; + sysclk_aux = 0x06; + break; + case 166: + sysclk_s = 0x06; + sysclk_r = 0x1F; + sysclk_v = 0x4B; + sysclk_aux = 0x07; + break; + default: + printf("Unsupported SYSCLK frequency.\n"); + return 0; + } + + vclkh = (sysclk_s << 5) | sysclk_r ; + vclkl = sysclk_v; + + out8(PIXIS_BASE + PIXIS_VCLKH, vclkh); + out8(PIXIS_BASE + PIXIS_VCLKL, vclkl); + + out8(PIXIS_BASE + PIXIS_AUX,sysclk_aux); + + return 1; +} + + +int set_px_mpxpll(ulong mpxpll) +{ + u8 tmp; + u8 val; + + switch (mpxpll) { + case 2: + case 4: + case 6: + case 8: + case 10: + case 12: + case 14: + case 16: + val = (u8)mpxpll; + break; + default: + printf("Unsupported MPXPLL ratio.\n"); + return 0; + } + + tmp = in8(PIXIS_BASE + PIXIS_VSPEED1); + tmp = (tmp & 0xF0) | (val & 0x0F); + out8(PIXIS_BASE + PIXIS_VSPEED1, tmp); + + return 1; +} + + +int set_px_corepll(ulong corepll) +{ + u8 tmp; + u8 val; + + switch ((int)corepll) { + case 20: + val = 0x08; + break; + case 25: + val = 0x0C; + break; + case 30: + val = 0x10; + break; + case 35: + val = 0x1C; + break; + case 40: + val = 0x14; + break; + case 45: + val = 0x0E; + break; + default: + printf("Unsupported COREPLL ratio.\n"); + return 0; + } + + tmp = in8(PIXIS_BASE + PIXIS_VSPEED0); + tmp = (tmp & 0xE0) | (val & 0x1F); + out8(PIXIS_BASE + PIXIS_VSPEED0, tmp); + + return 1; +} + + +void read_from_px_regs(int set) +{ + u8 mask = 0x1C; + u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0); + + if (set) + tmp = tmp | mask; + else + tmp = tmp & ~mask; + out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp); +} + + +void read_from_px_regs_altbank(int set) +{ + u8 mask = 0x04; + u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1); + + if (set) + tmp = tmp | mask; + else + tmp = tmp & ~mask; + out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp); +} + + +void set_altbank(void) +{ + u8 tmp; + + tmp = in8(PIXIS_BASE + PIXIS_VBOOT); + tmp ^= 0x40; + + out8(PIXIS_BASE + PIXIS_VBOOT, tmp); +} + + +void set_px_go(void) +{ + u8 tmp; + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp & 0x1E; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp | 0x01; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); +} + + +void set_px_go_with_watchdog(void) +{ + u8 tmp; + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp & 0x1E; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp | 0x09; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); +} + + +int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u8 tmp; + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp & 0x1E; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + + /* setting VCTL[WDEN] to 0 to disable watch dog */ + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp &= ~ 0x08; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + + return 0; +} + + +U_BOOT_CMD( + diswd, 1, 0, disable_watchdog, + "diswd - Disable watchdog timer \n", + NULL +); + + +/* + * This function takes the non-integral cpu:mpx pll ratio + * and converts it to an integer that can be used to assign + * FPGA register values. + * input: strptr i.e. argv[2] + */ + +ulong strfractoint(uchar *strptr) +{ + int i, j, retval; + int mulconst; + int intarr_len = 0, decarr_len = 0, no_dec = 0; + ulong intval = 0, decval = 0; + uchar intarr[3], decarr[3]; + + /* Assign the integer part to intarr[] + * If there is no decimal point i.e. + * if the ratio is an integral value + * simply create the intarr. + */ + i = 0; + while (strptr[i] != 46) { + if (strptr[i] == 0) { + no_dec = 1; + break; + } + intarr[i] = strptr[i]; + i++; + } + + /* Assign length of integer part to intarr_len. */ + intarr_len = i; + intarr[i] = '\0'; + + if (no_dec) { + /* Currently needed only for single digit corepll ratios */ + mulconst=10; + decval = 0; + } else { + j = 0; + i++; /* Skipping the decimal point */ + while ((strptr[i] > 47) && (strptr[i] < 58)) { + decarr[j] = strptr[i]; + i++; + j++; + } + + decarr_len = j; + decarr[j] = '\0'; + + mulconst = 1; + for (i = 0; i < decarr_len; i++) + mulconst *= 10; + decval = simple_strtoul(decarr, NULL, 10); + } + + intval = simple_strtoul(intarr, NULL, 10); + intval = intval * mulconst; + + retval = intval + decval; + + return retval; +} diff --git a/board/mpc8641hpcn/pixis.h b/board/mpc8641hpcn/pixis.h new file mode 100644 index 0000000000..cd9a45db87 --- /dev/null +++ b/board/mpc8641hpcn/pixis.h @@ -0,0 +1,33 @@ +/* + * Copyright 2006 Freescale Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +extern int set_px_sysclk(ulong sysclk); +extern int set_px_mpxpll(ulong mpxpll); +extern int set_px_corepll(ulong corepll); +extern void read_from_px_regs(int set); +extern void read_from_px_regs_altbank(int set); +extern void set_altbank(void); +extern void set_px_go(void); +extern void set_px_go_with_watchdog(void); +extern int disable_watchdog(cmd_tbl_t *cmdtp, + int flag, int argc, char *argv[]); +extern ulong strfractoint(uchar *strptr); diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds index c5c40e7eb4..b34de8e0ac 100644 --- a/board/mpc8641hpcn/u-boot.lds +++ b/board/mpc8641hpcn/u-boot.lds @@ -1,7 +1,7 @@ /* * (C) Copyright 2004, Freescale, Inc. * (C) Copyright 2002,2003, Motorola,Inc. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * * See file CREDITS for list of people who contributed to this * project. diff --git a/common/cmd_boot.c b/common/cmd_boot.c index e68f16f9da..182e2ab980 100644 --- a/common/cmd_boot.c +++ b/common/cmd_boot.c @@ -83,7 +83,7 @@ U_BOOT_CMD( extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); U_BOOT_CMD( - reset, 1, 0, do_reset, + reset, CFG_MAXARGS, 1, do_reset, "reset - Perform RESET of the CPU\n", NULL ); diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile index 0dd099df6a..ab6255a7df 100644 --- a/cpu/mpc86xx/Makefile +++ b/cpu/mpc86xx/Makefile @@ -3,7 +3,7 @@ # Xianghua Xiao,X.Xiao@motorola.com # # (C) Copyright 2004 Freescale Semiconductor. (MC86xx Port) -# Jeff Brown (Jeffrey@freescale.com) +# Jeff Brown # See file CREDITS for list of people who contributed to this # project. # @@ -30,7 +30,7 @@ LIB = lib$(CPU).a START = start.o #resetvec.o ASOBJS = cache.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o i2c.o spd_sdram.o + pci.o i2c.o spd_sdram.o OBJS = $(COBJS) all: .depend $(START) $(ASOBJS) $(LIB) diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S index 75186b1e4b..f316b3ec13 100644 --- a/cpu/mpc86xx/cache.S +++ b/cpu/mpc86xx/cache.S @@ -28,7 +28,7 @@ * Most of this code is taken from 74xx_7xx/cache.S * and then cleaned up a bit */ - + /* * Invalidate L1 instruction cache. */ @@ -316,24 +316,30 @@ _GLOBAL(dcache_status) blr /* - * Invalidate L2 cache using L2I and polling L2IP + * Invalidate L2 cache using L2I, assume L2 is enabled */ _GLOBAL(l2cache_invalidate) - sync - oris r3, r3, L2CR_L2I@h + mfspr r3, l2cr + rlwinm. r3, r3, 0, 0, 0 + beq 1f + + mfspr r3, l2cr + rlwinm r3, r3, 0, 1, 31 + +#ifdef CONFIG_ALTIVEC + dssall +#endif sync mtspr l2cr, r3 sync +1: mfspr r3, l2cr + oris r3, r3, L2CR_L2I@h + mtspr l2cr, r3 + invl2: mfspr r3, l2cr - andi. r3, r3, L2CR_L2IP + andi. r3, r3, L2CR_L2I@h bne invl2 - /* turn off the global invalidate bit */ - mfspr r3, l2cr - rlwinm r3, r3, 0, 11, 9 - sync - mtspr l2cr, r3 - sync blr /* diff --git a/cpu/mpc86xx/config.mk b/cpu/mpc86xx/config.mk index 4ef7ace2f4..3c54f4ad39 100644 --- a/cpu/mpc86xx/config.mk +++ b/cpu/mpc86xx/config.mk @@ -1,6 +1,6 @@ # # (C) Copyright 2004 Freescale Semiconductor. -# Jeff Brown +# Jeff Brown # # See file CREDITS for list of people who contributed to this # project. @@ -23,4 +23,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -ffixed-r29 -mstring \ No newline at end of file +PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -ffixed-r29 -mstring diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 36da7774ea..fc77d9949f 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -1,6 +1,6 @@ /* - * Copyright 2004 Freescale Semiconductor - * Jeff Brown (jeffrey@freescale.com) + * Copyright 2006 Freescale Semiconductor + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -32,29 +32,10 @@ #include #endif -extern unsigned long get_board_sys_clk(ulong dummy); - - -static __inline__ unsigned long get_dbat3u (void) -{ - unsigned long dbat3u; - asm volatile("mfspr %0, 542" : "=r" (dbat3u) :); - return dbat3u; -} - -static __inline__ unsigned long get_dbat3l (void) -{ - unsigned long dbat3l; - asm volatile("mfspr %0, 543" : "=r" (dbat3l) :); - return dbat3l; -} - -static __inline__ unsigned long get_msr (void) -{ - unsigned long msr; - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; -} +#ifdef CONFIG_MPC8641HPCN +extern void mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, + int argc, char *argv[]); +#endif int checkcpu (void) @@ -74,8 +55,7 @@ int checkcpu (void) minor = PVR_MIN(pvr); puts("CPU:\n"); - - printf(" Core: "); + puts(" Core: "); switch (ver) { case PVR_VER(PVR_86xx): @@ -131,22 +111,19 @@ int checkcpu (void) printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr); } - printf(" L2: "); - if (get_l2cr() & 0x80000000) - printf("Enabled\n"); - else - printf("Disabled\n"); + puts(" L2: "); + if (get_l2cr() & 0x80000000) + puts("Enabled\n"); + else + puts("Disabled\n"); return 0; } -/* -------------------------------------------------------------------- */ - static inline void soft_restart(unsigned long addr) { - #ifndef CONFIG_MPC8641HPCN /* SRR0 has system reset vector, SRR1 has default MSR value */ @@ -158,283 +135,25 @@ soft_restart(unsigned long addr) __asm__ __volatile__ ("rfi"); #else /* CONFIG_MPC8641HPCN */ - out8(PIXIS_BASE+PIXIS_RST,0); + + out8(PIXIS_BASE + PIXIS_RST, 0); + #endif /* !CONFIG_MPC8641HPCN */ + while(1); /* not reached */ } - -#ifdef CONFIG_MPC8641HPCN - -int set_px_sysclk(ulong sysclk) -{ - u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux,tmp; - - /* Per table 27, page 58 of MPC8641HPCN spec*/ - switch(sysclk) - { - case 33: - sysclk_s = 0x04; - sysclk_r = 0x04; - sysclk_v = 0x07; - sysclk_aux = 0x00; - break; - case 40: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x20; - sysclk_aux = 0x01; - break; - case 50: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x2A; - sysclk_aux = 0x02; - break; - case 66: - sysclk_s = 0x01; - sysclk_r = 0x04; - sysclk_v = 0x04; - sysclk_aux = 0x03; - break; - case 83: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x4B; - sysclk_aux = 0x04; - break; - case 100: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x5C; - sysclk_aux = 0x05; - break; - case 134: - sysclk_s = 0x06; - sysclk_r = 0x1F; - sysclk_v = 0x3B; - sysclk_aux = 0x06; - break; - case 166: - sysclk_s = 0x06; - sysclk_r = 0x1F; - sysclk_v = 0x4B; - sysclk_aux = 0x07; - break; - default: - printf("Unsupported SYSCLK frequency.\n"); - return 0; - } - - vclkh = (sysclk_s << 5) | sysclk_r ; - vclkl = sysclk_v; - out8(PIXIS_BASE+PIXIS_VCLKH,vclkh); - out8(PIXIS_BASE+PIXIS_VCLKL,vclkl); - - out8(PIXIS_BASE+PIXIS_AUX,sysclk_aux); - - return 1; -} - -int set_px_mpxpll(ulong mpxpll) -{ - u8 tmp; - u8 val; - switch(mpxpll) - { - case 2: - case 4: - case 6: - case 8: - case 10: - case 12: - case 14: - case 16: - val = (u8)mpxpll; - break; - default: - printf("Unsupported MPXPLL ratio.\n"); - return 0; - } - - tmp = in8(PIXIS_BASE+PIXIS_VSPEED1); - tmp = (tmp & 0xF0) | (val & 0x0F); - out8(PIXIS_BASE+PIXIS_VSPEED1,tmp); - - return 1; -} - -int set_px_corepll(ulong corepll) -{ - u8 tmp; - u8 val; - - switch ((int)corepll) { - case 20: - val = 0x08; - break; - case 25: - val = 0x0C; - break; - case 30: - val = 0x10; - break; - case 35: - val = 0x1C; - break; - case 40: - val = 0x14; - break; - case 45: - val = 0x0E; - break; - default: - printf("Unsupported COREPLL ratio.\n"); - return 0; - } - - tmp = in8(PIXIS_BASE+PIXIS_VSPEED0); - tmp = (tmp & 0xE0) | (val & 0x1F); - out8(PIXIS_BASE+PIXIS_VSPEED0,tmp); - - return 1; -} - -void read_from_px_regs(int set) -{ - u8 tmp, mask = 0x1C; - tmp = in8(PIXIS_BASE+PIXIS_VCFGEN0); - if (set) - tmp = tmp | mask; - else - tmp = tmp & ~mask; - out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp); -} - -void read_from_px_regs_altbank(int set) -{ - u8 tmp, mask = 0x04; - tmp = in8(PIXIS_BASE+PIXIS_VCFGEN1); - if (set) - tmp = tmp | mask; - else - tmp = tmp & ~mask; - out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp); -} - -void set_altbank(void) -{ - u8 tmp; - tmp = in8(PIXIS_BASE+PIXIS_VBOOT); - tmp ^= 0x40; - out8(PIXIS_BASE+PIXIS_VBOOT,tmp); - } - - -void set_px_go(void) -{ - u8 tmp; - tmp = in8(PIXIS_BASE+PIXIS_VCTL); - tmp = tmp & 0x1E; - out8(PIXIS_BASE+PIXIS_VCTL,tmp); - tmp = in8(PIXIS_BASE+PIXIS_VCTL); - tmp = tmp | 0x01; - out8(PIXIS_BASE+PIXIS_VCTL,tmp); -} - -void set_px_go_with_watchdog(void) -{ - u8 tmp; - tmp = in8(PIXIS_BASE+PIXIS_VCTL); - tmp = tmp & 0x1E; - out8(PIXIS_BASE+PIXIS_VCTL,tmp); - tmp = in8(PIXIS_BASE+PIXIS_VCTL); - tmp = tmp | 0x09; - out8(PIXIS_BASE+PIXIS_VCTL,tmp); -} - -/* This function takes the non-integral cpu:mpx pll ratio - * and converts it to an integer that can be used to assign - * FPGA register values. - * input: strptr i.e. argv[2] -*/ - -ulong strfractoint(uchar *strptr) -{ - int i,j,retval,intarr_len=0, decarr_len=0, mulconst, no_dec=0; - ulong intval =0, decval=0; - uchar intarr[3], decarr[3]; - - /* Assign the integer part to intarr[] - * If there is no decimal point i.e. - * if the ratio is an integral value - * simply create the intarr. - */ - i=0; - while(strptr[i] != 46) - { - if(strptr[i] == 0) - { - no_dec = 1; - break; /* Break from loop once the end of string is reached */ - } - - intarr[i] = strptr[i]; - i++; - } - - intarr_len = i; /* Assign length of integer part to intarr_len*/ - intarr[i] = '\0'; /* */ - - if(no_dec) - { - mulconst=10; /* Currently needed only for single digit corepll ratios */ - decval = 0; - } - else - { - j=0; - i++; /* Skipping the decimal point */ - while ((strptr[i] > 47) && (strptr[i] < 58)) - { - decarr[j] = strptr[i]; - i++; - j++; - } - - decarr_len = j; - decarr[j] = '\0'; - - mulconst=1; - for(i=0; i 1) { - cmd = argv[1][1]; - switch(cmd) { - case 'f': /* reset with frequency changed */ - if (argc < 5) - goto my_usage; - read_from_px_regs(0); - - val = set_px_sysclk(simple_strtoul(argv[2],NULL,10)); - - corepll = strfractoint(argv[3]); - val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[4], - NULL, 10)); - if (val == 3) { - printf("Setting registers VCFGEN0 and VCTL\n"); - read_from_px_regs(1); - printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); - set_px_go(); - } else - goto my_usage; - - while (1); /* Not reached */ - - case 'l': - if (argv[2][1] == 'f') { - read_from_px_regs(0); - read_from_px_regs_altbank(0); - /* reset with frequency changed */ - val = set_px_sysclk(simple_strtoul(argv[3],NULL,10)); - - corepll = strfractoint(argv[4]); - val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10)); - if (val == 3) { - printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs(1); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); - set_px_go_with_watchdog(); - } else - goto my_usage; - - while(1); /* Not reached */ - } else { - /* Reset from next bank without changing frequencies */ - read_from_px_regs(0); - read_from_px_regs_altbank(0); - if(argc > 2) - goto my_usage; - printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); - set_px_go_with_watchdog(); - while(1); /* Not reached */ - } - - default: - goto my_usage; - } - -my_usage: - printf("\nUsage: reset cf \n"); - printf(" reset altbank [cf ]\n"); - printf("For example: reset cf 40 2.5 10\n"); - printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); - return; - } else - out8(PIXIS_BASE+PIXIS_RST,0); + mpc8641_reset_board(cmdtp, flag, argc, argv); #endif /* !CONFIG_MPC8641HPCN */ @@ -571,7 +218,6 @@ void dma_init(void) dma->satr0 = 0x00040000; dma->datr0 = 0x00040000; asm("sync; isync"); - return; } uint dma_check(void) diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index c816c18974..93b73381f2 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -1,6 +1,6 @@ /* * Copyright 2004 Freescale Semiconductor. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -106,15 +106,6 @@ void cpu_init_f(void) /* enable SYNCBE | ABE bits in HID1 */ set_hid1(get_hid1() | 0x00000C00); - - /* Since the bats have been set up at this point and - * the local bus registers have been initialized, we - * turn on the WDEN bit in PIXIS_VCTL - */ -/* val = in8(PIXIS_BASE+PIXIS_VCTL); */ - /* Set the WDEN */ -/* val |= 0x08; */ -/* out8(PIXIS_BASE+PIXIS_VCTL,val); */ } /* diff --git a/cpu/mpc86xx/i2c.c b/cpu/mpc86xx/i2c.c index f2b4b0f6da..b3ac848a46 100644 --- a/cpu/mpc86xx/i2c.c +++ b/cpu/mpc86xx/i2c.c @@ -7,7 +7,7 @@ * Gleb Natapov * Some bits are taken from linux driver writen by adrian@humboldt.co.uk * - * Modified for MPC86xx by Jeff Brown (jeffrey@freescale.com) + * Modified for MPC86xx by Jeff Brown * * Hardware I2C driver for MPC107 PCI bridge. * @@ -207,7 +207,7 @@ i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) i = __i2c_read(data, length); - exit: +exit: writeb(MPC86xx_I2CCR_MEN, I2CCCR); return !(i == length); @@ -230,7 +230,7 @@ i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) i = __i2c_write(data, length); - exit: +exit: writeb(MPC86xx_I2CCR_MEN, I2CCCR); return !(i == length); diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index b5cd439e53..a8bcb98b81 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -9,7 +9,7 @@ * Xianghua Xiao (X.Xiao@motorola.com) * * (C) Copyright 2004 Freescale Semiconductor. (MPC86xx Port) - * Jeff Brown (Jeffrey@freescale.com) + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -37,11 +37,10 @@ #include #include -unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */ - - +unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */ unsigned long timestamp; + static __inline__ unsigned long get_msr (void) { unsigned long msr; @@ -75,7 +74,7 @@ static __inline__ void set_dec (unsigned long val) /* interrupt is not supported yet */ int interrupt_init_cpu (unsigned *decrementer_count) { - return 0; + return 0; } @@ -89,14 +88,14 @@ int interrupt_init (void) if (ret) return ret; - decrementer_count = get_tbclk()/CFG_HZ; - debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", (get_tbclk()/1000000), decrementer_count); + decrementer_count = get_tbclk()/CFG_HZ; + debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", (get_tbclk()/1000000), decrementer_count); - set_dec (decrementer_count); + set_dec (decrementer_count); set_msr (get_msr () | MSR_EE); - debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", get_msr(), get_dec()); + debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", get_msr(), get_dec()); return 0; } @@ -119,7 +118,7 @@ int disable_interrupts (void) void increment_timestamp(void) { - timestamp++; + timestamp++; } /* @@ -136,15 +135,15 @@ timer_interrupt_cpu (struct pt_regs *regs) void timer_interrupt (struct pt_regs *regs) { - /* call cpu specific function from $(CPU)/interrupts.c */ - timer_interrupt_cpu (regs); + /* call cpu specific function from $(CPU)/interrupts.c */ + timer_interrupt_cpu (regs); - timestamp++; + timestamp++; - ppcDcbf(×tamp); + ppcDcbf(×tamp); - /* Restore Decrementer Count */ - set_dec (decrementer_count); + /* Restore Decrementer Count */ + set_dec (decrementer_count); #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0) @@ -164,17 +163,17 @@ void timer_interrupt (struct pt_regs *regs) void reset_timer (void) { - timestamp = 0; + timestamp = 0; } ulong get_timer (ulong base) { - return timestamp - base; + return timestamp - base; } void set_timer (ulong t) { - timestamp = t; + timestamp = t; } /* @@ -192,11 +191,8 @@ irq_free_handler(int vec) } - -/******************************************************************************* - * +/* * irqinfo - print information about PCI devices,not implemented. - * */ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 9ce31d7c6f..f30bbbd7e2 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -41,6 +41,15 @@ extern int dma_xfer(void *dest, uint count, void *src); #define CFG_READ_SPD i2c_read #endif +/* + * Only one of the following three should be 1; others should be 0 + * By default the cache line interleaving is selected if + * the CONFIG_DDR_INTERLEAVE flag is defined in MPC8641HPCN.h + */ +#define CFG_PAGE_INTERLEAVING 0 +#define CFG_BANK_INTERLEAVING 0 +#define CFG_SUPER_BANK_INTERLEAVING 0 + /* * Convert picoseconds into clock cycles (rounding up if needed). */ @@ -144,10 +153,11 @@ convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) long int -spd_sdram(void) +spd_init(unsigned char i2c_address, unsigned int ddr_num, + unsigned int dimm_num, unsigned int start_addr) { volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; + volatile ccsr_ddr_t *ddr; volatile ccsr_gur_t *gur = &immap->im_gur; spd_eeprom_t spd; unsigned int n_ranks; @@ -175,28 +185,41 @@ spd_sdram(void) unsigned int mode_caslat; unsigned char sdram_type; unsigned char d_init; + unsigned int law_size; + volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; - - unsigned int law_size; - volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + if (ddr_num == 1) + ddr = &immap->im_ddr1; + else + ddr = &immap->im_ddr2; /* * Read SPD information. */ - CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) &spd, sizeof(spd)); + debug("Performing SPD read at I2C address 0x%02lx\n",i2c_address); + memset((void *)&spd, 0, sizeof(spd)); + CFG_READ_SPD(i2c_address, 0, 1, (uchar *) &spd, sizeof(spd)); /* * Check for supported memory module types. */ if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) { - printf("Unable to locate DDR I or DDR II module.\n" - " Fundamental memory type is 0x%0x\n", - spd.mem_type); + debug("Warning: Unable to locate DDR I or DDR II module for DIMM %d of DDR controller %d.\n" + " Fundamental memory type is 0x%0x\n", + dimm_num, + ddr_num, + spd.mem_type); return 0; } + debug("\nFound memory of type 0x%02lx ", spd.mem_type); + if (spd.mem_type == SPD_MEMTYPE_DDR) + debug("DDR I\n"); + else + debug("DDR II\n"); + /* * These test gloss over DDR I and II differences in interpretation * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks @@ -253,11 +276,7 @@ spd_sdram(void) */ rank_density = compute_banksize(spd.mem_type, spd.row_dens); - - /* - * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg - */ - ddr1->cs0_bnds = (rank_density >> 24) - 1; + debug("Start address for this controller is 0x%08lx\n", start_addr); /* * ODT configuration recommendation from DDR Controller Chapter. @@ -268,30 +287,133 @@ spd_sdram(void) odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */ } - ddr1->cs0_config = ( 1 << 31 - | (odt_rd_cfg << 20) - | (odt_wr_cfg << 16) - | (spd.nrow_addr - 12) << 8 - | (spd.ncol_addr - 8) ); - debug("\n"); - debug("DDR: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds); - debug("DDR: cs0_config = 0x%08x\n", ddr1->cs0_config); - - if (n_ranks == 2) { +#ifdef CONFIG_DDR_INTERLEAVE +#ifdef CONFIG_MPC8641HPCN + if (dimm_num != 1) { + printf("For interleaving memory on HPCN, need to use DIMM 1 for DDR Controller %d !\n", ddr_num); + return 0; + } else { /* - * Eg: Bounds: 0x0f00_0000 to 0x1e0000_0000, second 256 Meg + * Since interleaved memory only uses CS0, the + * memory sticks have to be identical in size and quantity + * of ranks. That essentially gives double the size on + * one rank, i.e on CS0 for both controllers put together. + * Confirm this??? */ - ddr1->cs1_bnds = ( (rank_density >> 8) - | ((rank_density >> (24 - 1)) - 1) ); - ddr1->cs1_config = ( 1<<31 + rank_density *= 2; + + /* + * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg + */ + start_addr = 0; + ddr->cs0_bnds = (start_addr >> 8) + | (((start_addr + rank_density - 1) >> 24)); + /* + * Default interleaving mode to cache-line interleaving. + */ + ddr->cs0_config = ( 1 << 31 +#if (CFG_PAGE_INTERLEAVING == 1) + | (PAGE_INTERLEAVING) +#elif (CFG_BANK_INTERLEAVING == 1) + | (BANK_INTERLEAVING) +#elif (CFG_SUPER_BANK_INTERLEAVING == 1) + | (SUPER_BANK_INTERLEAVING) +#else + | (CACHE_LINE_INTERLEAVING) +#endif | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); - debug("DDR: cs1_bnds = 0x%08x\n", ddr1->cs1_bnds); - debug("DDR: cs1_config = 0x%08x\n", ddr1->cs1_config); - } + debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds); + debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config); + + /* + * Adjustment for dual rank memory to get correct memory + * size (return value of this function). + */ + if (n_ranks == 2) { + n_ranks = 1; + rank_density /= 2; + } else { + rank_density /= 2; + } + } +#endif /* CONFIG_MPC8641HPCN */ + +#else /* CONFIG_DDR_INTERLEAVE */ + + if (dimm_num == 1) { + /* + * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg + */ + ddr->cs0_bnds = (start_addr >> 8) + | (((start_addr + rank_density - 1) >> 24)); + + ddr->cs0_config = ( 1 << 31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + + debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds); + debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config); + + if (n_ranks == 2) { + /* + * Eg: Bounds: 0x1000_0000 to 0x1f00_0000, + * second 256 Meg + */ + ddr->cs1_bnds = (((start_addr + rank_density) >> 8) + | (( start_addr + 2*rank_density - 1) + >> 24)); + ddr->cs1_config = ( 1<<31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds); + debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config); + } + + } else { + /* + * This is the 2nd DIMM slot for this controller + */ + /* + * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg + */ + ddr->cs2_bnds = (start_addr >> 8) + | (((start_addr + rank_density - 1) >> 24)); + + ddr->cs2_config = ( 1 << 31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + + debug("DDR: cs2_bnds = 0x%08x\n", ddr->cs2_bnds); + debug("DDR: cs2_config = 0x%08x\n", ddr->cs2_config); + + if (n_ranks == 2) { + /* + * Eg: Bounds: 0x1000_0000 to 0x1f00_0000, + * second 256 Meg + */ + ddr->cs3_bnds = (((start_addr + rank_density) >> 8) + | (( start_addr + 2*rank_density - 1) + >> 24)); + ddr->cs3_config = ( 1<<31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + debug("DDR: cs3_bnds = 0x%08x\n", ddr->cs3_bnds); + debug("DDR: cs3_config = 0x%08x\n", ddr->cs3_config); + } + } +#endif /* CONFIG_DDR_INTERLEAVE */ /* * Find the largest CAS by locating the highest 1 bit @@ -447,15 +569,14 @@ spd_sdram(void) unsigned char act_pd_exit = 2; /* Empirical? */ unsigned char pre_pd_exit = 6; /* Empirical? */ - ddr1->timing_cfg_0 = (0 + ddr->timing_cfg_0 = (0 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */ | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */ | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */ | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */ ); - debug("DDR: timing_cfg_0 = 0x%08x\n", ddr1->timing_cfg_0); + debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); - } else { } @@ -520,10 +641,10 @@ spd_sdram(void) /* * Sneak in some Extended Refresh Recovery. */ - ddr1->ext_refrec = (trfc_high << 16); - debug("DDR: ext_refrec = 0x%08x\n", ddr1->ext_refrec); + ddr->ext_refrec = (trfc_high << 16); + debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec); - ddr1->timing_cfg_1 = + ddr->timing_cfg_1 = (0 | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */ | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */ @@ -535,7 +656,7 @@ spd_sdram(void) | ((twtr_clk & 0x07) << 0) /* WRTORD */ ); - debug("DDR: timing_cfg_1 = 0x%08x\n", ddr1->timing_cfg_1); + debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); /* @@ -612,7 +733,7 @@ spd_sdram(void) } } - ddr1->timing_cfg_2 = (0 + ddr->timing_cfg_2 = (0 | ((add_lat & 0x7) << 28) /* ADD_LAT */ | ((cpo & 0x1f) << 23) /* CPO */ | ((wr_lat & 0x7) << 19) /* WR_LAT */ @@ -622,7 +743,7 @@ spd_sdram(void) | ((four_act & 0x1f) << 0) /* FOUR_ACT */ ); - debug("DDR: timing_cfg_2 = 0x%08x\n", ddr1->timing_cfg_2); + debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); /* @@ -673,7 +794,7 @@ spd_sdram(void) } /* - * Encoded Burst Lenght of 4. + * Encoded Burst Length of 4. */ burst_len = 2; /* Fiat. */ @@ -706,7 +827,7 @@ spd_sdram(void) mode_odt_enable = 0x40; /* 150 Ohm */ } - ddr1->sdram_mode_1 = + ddr->sdram_mode_1 = (0 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ @@ -715,14 +836,14 @@ spd_sdram(void) | (burst_len << 0) /* Burst length */ ); - debug("DDR: sdram_mode = 0x%08x\n", ddr1->sdram_mode_1); + debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode_1); /* * Clear EMRS2 and EMRS3. */ - ddr1->sdram_mode_2 = 0; - debug("DDR: sdram_mode_2 = 0x%08x\n", ddr1->sdram_mode_2); + ddr->sdram_mode_2 = 0; + debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2); /* @@ -749,12 +870,12 @@ spd_sdram(void) * Set BSTOPRE to 0x100 for page mode * If auto-charge is used, set BSTOPRE = 0 */ - ddr1->sdram_interval = + ddr->sdram_interval = (0 | (refresh_clk & 0x3fff) << 16 | 0x100 ); - debug("DDR: sdram_interval = 0x%08x\n", ddr1->sdram_interval); + debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval); } /* @@ -763,11 +884,11 @@ spd_sdram(void) */ #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) if (spd.config == 0x02) { - ddr1->err_disable = 0x0000000d; - ddr1->err_sbe = 0x00ff0000; + ddr->err_disable = 0x0000000d; + ddr->err_sbe = 0x00ff0000; } - debug("DDR: err_disable = 0x%08x\n", ddr1->err_disable); - debug("DDR: err_sbe = 0x%08x\n", ddr1->err_sbe); + debug("DDR: err_disable = 0x%08x\n", ddr->err_disable); + debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe); #endif asm("sync;isync"); @@ -800,8 +921,8 @@ spd_sdram(void) * Use the DDR controller to auto initialize memory. */ d_init = 1; - ddr1->sdram_data_init = CONFIG_MEM_INIT_VALUE; - debug("DDR: ddr_data_init = 0x%08x\n", ddr1->sdram_data_init); + ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE; + debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init); #else /* * Memory will be initialized via DMA, or not at all. @@ -809,13 +930,13 @@ spd_sdram(void) d_init = 0; #endif - ddr1->sdram_cfg_2 = (0 + ddr->sdram_cfg_2 = (0 | (dqs_cfg << 26) /* Differential DQS */ | (odt_cfg << 21) /* ODT */ | (d_init << 4) /* D_INIT auto init DDR */ ); - debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr1->sdram_cfg_2); + debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2); #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL @@ -835,121 +956,373 @@ spd_sdram(void) clk_adjust = 0x7; } - ddr1->sdram_clk_cntl = (0 + ddr->sdram_clk_cntl = (0 | 0x80000000 | (clk_adjust << 23) ); - debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr1->sdram_clk_cntl); + debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl); } #endif - /* - * Figure out the settings for the sdram_cfg register. - * Build up the entire register in 'sdram_cfg' before writing - * since the write into the register will actually enable the - * memory controller; all settings must be done before enabling. - * - * sdram_cfg[0] = 1 (ddr sdram logic enable) - * sdram_cfg[1] = 1 (self-refresh-enable) - * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM) - * 010 DDR 1 SDRAM - * 011 DDR 2 SDRAM - */ - sdram_type = (spd.mem_type == SPD_MEMTYPE_DDR) ? 2 : 3; - sdram_cfg_1 = (0 - | (1 << 31) /* Enable */ - | (1 << 30) /* Self refresh */ - | (sdram_type << 24) /* SDRAM type */ - ); - - /* - * sdram_cfg[3] = RD_EN - registered DIMM enable - * A value of 0x26 indicates micron registered DIMMS (micron.com) - */ - if (spd.mem_type == SPD_MEMTYPE_DDR && spd.mod_attr == 0x26) { - sdram_cfg_1 |= 0x10000000; /* RD_EN */ - } - -#if defined(CONFIG_DDR_ECC) - /* - * If the user wanted ECC (enabled via sdram_cfg[2]) - */ - if (spd.config == 0x02) { - sdram_cfg_1 |= 0x20000000; /* ECC_EN */ - } -#endif - - /* - * REV1 uses 1T timing. - * REV2 may use 1T or 2T as configured by the user. - */ - { - uint pvr = get_pvr(); - - if (pvr != PVR_85xx_REV1) { -#if defined(CONFIG_DDR_2T_TIMING) - /* - * Enable 2T timing by setting sdram_cfg[16]. - */ - sdram_cfg_1 |= 0x8000; /* 2T_EN */ -#endif - } - } - - /* - * 200 painful micro-seconds must elapse between - * the DDR clock setup and the DDR config enable. - */ - udelay(200); - - /* - * Go! - */ - ddr1->sdram_cfg_1 = sdram_cfg_1; - - asm("sync;isync"); - udelay(500); - - debug("DDR: sdram_cfg = 0x%08x\n", ddr1->sdram_cfg_1); - - -#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - debug("DDR: memory initializing\n"); - /* - * Poll until memory is initialized. - * 512 Meg at 400 might hit this 200 times or so. - */ - while ((ddr1->sdram_cfg_2 & (d_init << 4)) != 0) { - udelay(1000); - } - debug("DDR: memory initialized\n"); -#endif - /* * Figure out memory size in Megabytes. */ + debug("# ranks = %d, rank_density = 0x%08lx\n", n_ranks, rank_density); memsize = n_ranks * rank_density / 0x100000; + return memsize; +} - /* - * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord. - */ - law_size = 19 + __ilog2(memsize); +unsigned int enable_ddr(unsigned int ddr_num) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + spd_eeprom_t spd1,spd2; + volatile ccsr_ddr_t *ddr; + unsigned sdram_cfg_1; + unsigned char sdram_type, mem_type, config, mod_attr; + unsigned char d_init; + unsigned int no_dimm1=0, no_dimm2=0; + + /* Set up pointer to enable the current ddr controller */ + if (ddr_num == 1) + ddr = &immap->im_ddr1; + else + ddr = &immap->im_ddr2; /* - * Set up LAWBAR for all of DDR. + * Read both dimm slots and decide whether + * or not to enable this controller. */ - mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); - mcm->lawar1 = (LAWAR_EN - | LAWAR_TRGT_IF_DDR - | (LAWAR_SIZE & law_size)); - debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); - debug("DDR: LARAR1=0x%08x\n", mcm->lawar1); + memset((void *)&spd1,0,sizeof(spd1)); + memset((void *)&spd2,0,sizeof(spd2)); - return memsize * 1024 * 1024; + if (ddr_num == 1) { + CFG_READ_SPD(SPD_EEPROM_ADDRESS1, + 0, 1, (uchar *) &spd1, sizeof(spd1)); + CFG_READ_SPD(SPD_EEPROM_ADDRESS2, + 0, 1, (uchar *) &spd2, sizeof(spd2)); + } else { + CFG_READ_SPD(SPD_EEPROM_ADDRESS3, + 0, 1, (uchar *) &spd1, sizeof(spd1)); + CFG_READ_SPD(SPD_EEPROM_ADDRESS4, + 0, 1, (uchar *) &spd2, sizeof(spd2)); + } + + /* + * Check for supported memory module types. + */ + if (spd1.mem_type != SPD_MEMTYPE_DDR + && spd1.mem_type != SPD_MEMTYPE_DDR2) { + no_dimm1 = 1; + } else { + debug("\nFound memory of type 0x%02lx ",spd1.mem_type ); + if (spd1.mem_type == SPD_MEMTYPE_DDR) + debug("DDR I\n"); + else + debug("DDR II\n"); + } + + if (spd2.mem_type != SPD_MEMTYPE_DDR && + spd2.mem_type != SPD_MEMTYPE_DDR2) { + no_dimm2 = 1; + } else { + debug("\nFound memory of type 0x%02lx ",spd2.mem_type ); + if (spd2.mem_type == SPD_MEMTYPE_DDR) + debug("DDR I\n"); + else + debug("DDR II\n"); + } + +#ifdef CONFIG_DDR_INTERLEAVE + if (no_dimm1) { + printf("For interleaved operation memory modules need to be present in CS0 DIMM slots of both DDR controllers!\n"); + return 0; + } +#endif + + /* + * Memory is not present in DIMM1 and DIMM2 - so do not enable DDRn + */ + if (no_dimm1 && no_dimm2) { + printf("No memory modules found for DDR controller %d!!\n", ddr_num); + return 0; + } else { + mem_type = no_dimm2 ? spd1.mem_type : spd2.mem_type; + + /* + * Figure out the settings for the sdram_cfg register. + * Build up the entire register in 'sdram_cfg' before + * writing since the write into the register will + * actually enable the memory controller; all settings + * must be done before enabling. + * + * sdram_cfg[0] = 1 (ddr sdram logic enable) + * sdram_cfg[1] = 1 (self-refresh-enable) + * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM) + * 010 DDR 1 SDRAM + * 011 DDR 2 SDRAM + */ + sdram_type = (mem_type == SPD_MEMTYPE_DDR) ? 2 : 3; + sdram_cfg_1 = (0 + | (1 << 31) /* Enable */ + | (1 << 30) /* Self refresh */ + | (sdram_type << 24) /* SDRAM type */ + ); + + /* + * sdram_cfg[3] = RD_EN - registered DIMM enable + * A value of 0x26 indicates micron registered + * DIMMS (micron.com) + */ + mod_attr = no_dimm2 ? spd1.mod_attr : spd2.mod_attr; + if (mem_type == SPD_MEMTYPE_DDR && mod_attr == 0x26) { + sdram_cfg_1 |= 0x10000000; /* RD_EN */ + } + +#if defined(CONFIG_DDR_ECC) + + config = no_dimm2 ? spd1.config : spd2.config; + + /* + * If the user wanted ECC (enabled via sdram_cfg[2]) + */ + if (config == 0x02) { + ddr->err_disable = 0x00000000; + asm("sync;isync;"); + ddr->err_sbe = 0x00ff0000; + ddr->err_int_en = 0x0000000d; + sdram_cfg_1 |= 0x20000000; /* ECC_EN */ + } +#endif + + /* + * Set 1T or 2T timing based on 1 or 2 modules + */ + { + if (!(no_dimm1 || no_dimm2)) { + /* + * 2T timing,because both DIMMS are present. + * Enable 2T timing by setting sdram_cfg[16]. + */ + sdram_cfg_1 |= 0x8000; /* 2T_EN */ + } + } + + /* + * 200 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + */ + udelay(200); + + /* + * Go! + */ + ddr->sdram_cfg_1 = sdram_cfg_1; + + asm volatile("sync;isync"); + udelay(500); + + debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg_1); + + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + d_init = 1; + debug("DDR: memory initializing\n"); + + /* + * Poll until memory is initialized. + * 512 Meg at 400 might hit this 200 times or so. + */ + while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { + udelay(1000); + } + debug("DDR: memory initialized\n\n"); +#endif + + debug("Enabled DDR Controller %d\n", ddr_num); + return 1; + } } + +long int +spd_sdram(void) +{ + int memsize_ddr1_dimm1 = 0; + int memsize_ddr1_dimm2 = 0; + int memsize_ddr2_dimm1 = 0; + int memsize_ddr2_dimm2 = 0; + int memsize_total = 0; + int memsize_ddr1 = 0; + int memsize_ddr2 = 0; + unsigned int ddr1_enabled = 0; + unsigned int ddr2_enabled = 0; + unsigned int law_size_ddr1; + unsigned int law_size_ddr2; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; + volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2; + volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + +#ifdef CONFIG_DDR_INTERLEAVE + unsigned int law_size_interleaved; + + memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1, + 1, 1, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr1_dimm1; + + memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3, + 2, 1, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr2_dimm1; + + if (memsize_ddr1_dimm1 != memsize_ddr2_dimm1) { + if (memsize_ddr1_dimm1 < memsize_ddr2_dimm1) + memsize_total -= memsize_ddr1_dimm1; + else + memsize_total -= memsize_ddr2_dimm1; + debug("Total memory available for interleaving 0x%08lx\n", + memsize_total * 1024 * 1024); + debug("Adjusting CS0_BNDS to account for unequal DIMM sizes in interleaved memory\n"); + ddr1->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24; + ddr2->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24; + debug("DDR1: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds); + debug("DDR2: cs0_bnds = 0x%08x\n", ddr2->cs0_bnds); + } + + ddr1_enabled = enable_ddr(1); + ddr2_enabled = enable_ddr(2); + + /* + * Both controllers need to be enabled for interleaving. + */ + if (ddr1_enabled && ddr2_enabled) { + law_size_interleaved = 19 + __ilog2(memsize_total); + + /* + * Set up LAWBAR for DDR 1 space. + */ + mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); + mcm->lawar1 = (LAWAR_EN + | LAWAR_TRGT_IF_DDR_INTERLEAVED + | (LAWAR_SIZE & law_size_interleaved)); + debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); + debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1); + debug("Interleaved memory size is 0x%08lx\n", memsize_total); + +#ifdef CONFIG_DDR_INTERLEAVE +#if (CFG_PAGE_INTERLEAVING == 1) + printf("Page "); +#elif (CFG_BANK_INTERLEAVING == 1) + printf("Bank "); +#elif (CFG_SUPER_BANK_INTERLEAVING == 1) + printf("Super-bank "); +#else + printf("Cache-line "); +#endif +#endif + printf("Interleaved"); + return memsize_total * 1024 * 1024; + } else { + printf("Interleaved memory not enabled - check CS0 DIMM slots for both controllers.\n"); + return 0; + } + +#else + /* + * Call spd_sdram() routine to init ddr1 - pass I2c address, + * controller number, dimm number, and starting address. + */ + memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1, + 1, 1, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr1_dimm1; + + memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2, + 1, 2, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr1_dimm2; + + /* + * Enable the DDR controller - pass ddr controller number. + */ + ddr1_enabled = enable_ddr(1); + + /* Keep track of memory to be addressed by DDR1 */ + memsize_ddr1 = memsize_ddr1_dimm1 + memsize_ddr1_dimm2; + + /* + * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord. + */ + if (ddr1_enabled) { + law_size_ddr1 = 19 + __ilog2(memsize_ddr1); + + /* + * Set up LAWBAR for DDR 1 space. + */ + mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); + mcm->lawar1 = (LAWAR_EN + | LAWAR_TRGT_IF_DDR1 + | (LAWAR_SIZE & law_size_ddr1)); + debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); + debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1); + } + +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3, + 2, 1, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr2_dimm1; + + memsize_ddr2_dimm2 = spd_init(SPD_EEPROM_ADDRESS4, + 2, 2, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr2_dimm2; + + ddr2_enabled = enable_ddr(2); + + /* Keep track of memory to be addressed by DDR2 */ + memsize_ddr2 = memsize_ddr2_dimm1 + memsize_ddr2_dimm2; + + if (ddr2_enabled) { + law_size_ddr2 = 19 + __ilog2(memsize_ddr2); + + /* + * Set up LAWBAR for DDR 2 space. + */ + if (ddr1_enabled) + mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12) + & 0xfffff); + else + mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); + + mcm->lawar8 = (LAWAR_EN + | LAWAR_TRGT_IF_DDR2 + | (LAWAR_SIZE & law_size_ddr2)); + debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8); + debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8); + } +#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */ + + debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n", + memsize_ddr1, memsize_ddr2); + + /* + * If neither DDR controller is enabled return 0. + */ + if (!ddr1_enabled && !ddr2_enabled) + return 0; + else { + printf("Non-interleaved"); + return memsize_total * 1024 * 1024; + } + +#endif /* CONFIG_DDR_INTERLEAVE */ +} + + #endif /* CONFIG_SPD_EEPROM */ diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index a08ae5f94b..5e05ab81f1 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -1,6 +1,6 @@ /* * Copyright 2004 Freescale Semiconductor. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * (C) Copyright 2000-2002 @@ -29,9 +29,6 @@ #include #include -unsigned long get_board_sys_clk(ulong dummy); -unsigned long get_sysclk_from_px_regs(void); - void get_sys_info (sys_info_t *sysInfo) { @@ -39,11 +36,11 @@ void get_sys_info (sys_info_t *sysInfo) volatile ccsr_gur_t *gur = &immap->im_gur; uint plat_ratio, e600_ratio; - plat_ratio = (gur->porpllsr) & 0x0000003e; + plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; switch(plat_ratio) { - case 0x0: + case 0x0: sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ; break; case 0x02: @@ -55,19 +52,14 @@ void get_sys_info (sys_info_t *sysInfo) case 0x09: case 0x0a: case 0x0c: - case 0x10: - sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; - break; + case 0x10: + sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; + break; default: sysInfo->freqSystemBus = 0; break; } -#if 0 - printf("assigned system bus freq = %d for plat ratio 0x%08lx\n", - sysInfo->freqSystemBus, plat_ratio); -#endif - e600_ratio = (gur->porpllsr) & 0x003f0000; e600_ratio >>= 16; @@ -75,13 +67,13 @@ void get_sys_info (sys_info_t *sysInfo) case 0x10: sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus; break; - case 0x19: + case 0x19: sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus/2; break; case 0x20: sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; break; - case 0x39: + case 0x39: sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus/2; break; case 0x28: @@ -90,16 +82,10 @@ void get_sys_info (sys_info_t *sysInfo) case 0x1d: sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus/2; break; - default: - /* JB - Emulator workaround until real cop is plugged in */ - /* sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; */ + default: sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus; break; } -#if 0 - printf("assigned processor freq = %d for e600 ratio 0x%08lx\n", - sysInfo->freqProcessor, e600_ratio); -#endif } @@ -128,6 +114,7 @@ int get_clocks(void) * get_bus_freq * Return system bus freq in Hz */ + ulong get_bus_freq(ulong dummy) { ulong val; @@ -139,42 +126,6 @@ ulong get_bus_freq(ulong dummy) return val; } -unsigned long get_sysclk_from_px_regs() -{ - ulong val; - u8 vclkh, vclkl; - - vclkh = in8(PIXIS_BASE + PIXIS_VCLKH); - vclkl = in8(PIXIS_BASE + PIXIS_VCLKL); - - if ((vclkh == 0x84) && (vclkl == 0x07)) { - val = 33000000; - } - if ((vclkh == 0x3F) && (vclkl == 0x20)) { - val = 40000000; - } - if ((vclkh == 0x3F) && (vclkl == 0x2A)) { - val = 50000000; - } - if ((vclkh == 0x24) && (vclkl == 0x04)) { - val = 66000000; - } - if ((vclkh == 0x3F) && (vclkl == 0x4B)) { - val = 83000000; - } - if ((vclkh == 0x3F) && (vclkl == 0x5C)) { - val = 100000000; - } - if ((vclkh == 0xDF) && (vclkl == 0x3B)) { - val = 134000000; - } - if ((vclkh == 0xDF) && (vclkl == 0x4B)) { - val = 166000000; - } - - return val; -} - /* * get_board_sys_clk diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index b96363151d..07e75572b9 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -207,11 +207,7 @@ boot_warm: /* init the L2 cache */ addis r3, r0, L2_INIT@h ori r3, r3, L2_INIT@l - sync mtspr l2cr, r3 -#ifdef CONFIG_ALTIVEC - dssall -#endif /* invalidate the L2 cache */ bl l2cache_invalidate sync @@ -245,6 +241,13 @@ in_flash: bl setup_ccsrbar #endif + /* Fix for SMP linux - Changing arbitration to round-robin */ + lis r3, CFG_CCSRBAR@h + ori r3, r3, 0x1000 + xor r4, r4, r4 + li r4, 0x1000 + stw r4, 0(r3) + /* setup the law entries */ bl law_entry sync @@ -280,9 +283,9 @@ in_flash: /* make sure timer enabled in guts register too */ lis r3, CFG_CCSRBAR@h oris r3,r3, 0xE - ori r3,r3,0x0070 /*Jason from 3*/ + ori r3,r3,0x0070 lwz r4, 0(r3) - lis r5,0xFFFC /*Jason from 0xffff*/ + lis r5,0xFFFC ori r5,r5,0x5FFF and r4,r4,r5 stw r4,0(r3) diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn new file mode 100644 index 0000000000..907a911ed1 --- /dev/null +++ b/doc/README.mpc8641hpcn @@ -0,0 +1,123 @@ +Freescale MPC8641HPCN board +=========================== + +Created 05/24/2006 Haiying Wang +------------------------------- + +1. Building U-Boot +------------------ +The 86xx HPCN code base is known to compile using: + Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 + + $ make MPC8641HPCN_config + Configuring for MPC8641HPCN board... + + $ make + + +2. Switch and Jumper Setting +---------------------------- +Jumpers: + J14 Pins 1-2 (near plcc32 socket) + +Switches: + SW1(1-5) = 01100 CFG_COREPLL = 01000 :: CORE = 2:1 + 01100 :: CORE = 2.5:1 + 10000 :: CORE = 3:1 + 11100 :: CORE = 3.5:1 + 10100 :: CORE = 4:1 + 01110 :: CORE = 4.5:1 + SW1(6-8) = 001 CFG_SYSCLK = 000 :: SYSCLK = 33MHz + 001 :: SYSCLK = 40MHz + + SW2(1-4) = 1100 CFG_CCBPLL = 0010 :: 2X + 0100 :: 4X + 0110 :: 6X + 1000 :: 8X + 1010 :: 10X + 1100 :: 12X + 1110 :: 14X + 0000 :: 16X + SW2(5-8) = 1110 CFG_BOOTLOC = 1110 :: boot 16-bit localbus + + SW3(1-7) = 0011000 CFG_VID = 0011000 :: VCORE = 1.2V + 0100000 :: VCORE = 1.11V + SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V + 1 :: VCC_PLAT = 1.0V + + SW4(1-2) = 11 CFG_HOSTMODE = 11 :: both prots host/root + SW4(3-4) = 11 CFG_BOOTSEQ = 11 :: no boot seq + SW4(5-8) = 0011 CFG_IOPORT = 0011 :: both PEX + + SW5(1) = 1 CFG_FLASHMAP = 1 :: boot from flash + 0 :: boot from PromJet + SW5(2) = 1 CFG_FLASHBANK = 1 :: swap upper/lower + halves (virtual banks) + 0 :: normal + SW5(3) = 0 CFG_FLASHWP = 0 :: not protected + SW5(4) = 0 CFG_PORTDIV = 1 :: 2:1 for PD4 + 1:1 for PD6 + SW5(5-6) = 11 CFG_PIXISOPT = 11 :: s/w determined + SW5(7-8) = 11 CFG_LADOPT = 11 :: s/w determined + + SW6(1) = 1 CFG_CPUBOOT = 1 :: no boot holdoff + SW6(2) = 1 CFG_BOOTADDR = 1 :: no traslation + SW6(3-5) = 000 CFG_REFCLKSEL = 000 :: 100MHZ + SW6(6) = 1 CFG_SERROM_ADDR= 1 :: + SW6(7) = 1 CFG_MEMDEBUG = 1 :: + SW6(8) = 1 CFG_DDRDEBUG = 1 :: + + SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49 + SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled + SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode + SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz + SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode + SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled + SW8(7) = 1 ACPWR = 1 :: non-battery + SW8(8) = 0 CFG_IDWP = 0 :: write enable + + +3. Flash U-Boot +--------------- +The flash range 0xFF800000 to 0xFFFFFFFF can be divided into 2 halves. +It is possible to use either half to boot using u-boot. Switch 5 bit 2 +is used for this purpose. + +0xFF800000 to 0xFFBFFFFF - 4MB +0xFFC00000 to 0xFFFFFFFF - 4MB +When this bit is 0, U-Boot is at 0xFFF00000. +When this bit is 1, U-Boot is at 0xFFB00000. + +Use the above mentioned flash commands to program the other half, and +use switch 5, bit 2 to alternate between the halves. Note: The booting +version of U-Boot will always be at 0xFFF00000. + +To Flash U-Boot into the booting bank (0xFFC00000 - 0xFFFFFFFF): + + tftp 1000000 u-boot.bin + protect off all + erase fff00000 ffffffff + cp.b 1000000 fff00100 80000 + +To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF): + + tftp 1000000 u-boot.bin + erase ffb00000 ffbfffff + cp.b 1000000 ffb00100 80000 + + +4. Memory Map +------------- + + Memory Range Device Size + ------------ ------ ---- + 0x0000_0000 0x7fff_ffff DDR 2G + 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M + 0xa000_0000 0xafff_ffff PCI2/PEX2 MEM 512M + 0xf800_0000 0xf80f_ffff CCSR 1M + 0xf810_0000 0xf81f_ffff PIXIS 1M + 0xf840_0000 0xf840_3fff Stack space 32K + 0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 512M + 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 512M + 0xfe00_0000 0xfeff_ffff Flash(alternate)16M + 0xff00_0000 0xffff_ffff Flash(boot bank)16M diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 6bbe072b2d..9e81b47071 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -52,7 +52,7 @@ typedef struct ccsr_local_mcm { uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ char res19[4]; uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ - char res20[16]; + char res20[20]; uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ char res21[4]; uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ @@ -60,7 +60,7 @@ typedef struct ccsr_local_mcm { uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ char res23[4]; uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ - char res24[720]; + char res24[716]; uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */ char res25[4]; uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index d4a28edf9b..2a197be294 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -57,6 +57,13 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_NUM_DDR_CONTROLLERS 2 +/* #define CONFIG_DDR_INTERLEAVE 1 */ +#define CACHE_LINE_INTERLEAVING 0x20000000 +#define PAGE_INTERLEAVING 0x21000000 +#define BANK_INTERLEAVING 0x22000000 +#define SUPER_BANK_INTERLEAVING 0x23000000 + #define CONFIG_ALTIVEC 1 @@ -99,7 +106,10 @@ /* * Determine DDR configuration from I2C interface. */ - #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ #else /* @@ -136,15 +146,16 @@ /* - * In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 - * We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff + * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. + * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. * However, when u-boot comes up, the flash_init needs hard start addresses - * to build its info table. For user convenience, we have the flash addresses - * as fe800000 and ff800000. That way, when we do flash operations, u-boot - * knows where the flash is and the user can download u-boot code from promjet to - * fef00000 <- more intuitive than fe700000. Note that, on switching the boot - * location, fef00000 becomes fff00000. + * to build its info table. For user convenience, the flash addresses is + * fe800000 and ff800000. That way, u-boot knows where the flash is + * and the user can download u-boot code from promjet to fef00000, a + * more intuitive location than fe700000. + * + * Note that, on switching the boot location, fef00000 becomes fff00000. */ #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ #define CFG_FLASH_BASE2 0xff800000 @@ -257,14 +268,18 @@ #define CFG_64BIT_VSPRINTF 1 #define CFG_64BIT_STRTOUL 1 -/* I2C */ +/* + * I2C + */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -/* RapidIO MMU */ +/* + * RapidIO MMU + */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ @@ -347,19 +362,21 @@ #endif /* CONFIG_TSEC_ENET */ -/* BAT0 2G Cacheable, non-guarded +/* + * BAT0 2G Cacheable, non-guarded * 0x0000_0000 2G DDR */ #define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE ) -#define CFG_DBAT0U ( BATU_BL_512M | BATU_VS | BATU_VP ) +#define CFG_DBAT0U ( BATU_BL_2G | BATU_VS | BATU_VP ) #define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) #define CFG_IBAT0U CFG_DBAT0U -/* BAT1 1G Cache-inhibited, guarded +/* + * BAT1 1G Cache-inhibited, guarded * 0x8000_0000 512M PCI-Express 1 Memory * 0xa000_0000 512M PCI-Express 2 Memory - ** SS - Changed it for operating from 0xd0000000 + * Changed it for operating from 0xd0000000 */ #define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) @@ -367,7 +384,8 @@ #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT1U CFG_DBAT1U -/* BAT2 512M Cache-inhibited, guarded +/* + * BAT2 512M Cache-inhibited, guarded * 0xc000_0000 512M RapidIO Memory */ #define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ @@ -376,7 +394,8 @@ #define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT2U CFG_DBAT2U -/* BAT3 4M Cache-inhibited, guarded +/* + * BAT3 4M Cache-inhibited, guarded * 0xf800_0000 4M CCSR */ #define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ @@ -385,10 +404,11 @@ #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT3U CFG_DBAT3U -/* BAT4 32M Cache-inhibited, guarded +/* + * BAT4 32M Cache-inhibited, guarded * 0xe200_0000 16M PCI-Express 1 I/O * 0xe300_0000 16M PCI-Express 2 I/0 - ** SS - Note that this is at 0xe0000000 + * Note that this is at 0xe0000000 */ #define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) @@ -396,7 +416,8 @@ #define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT4U CFG_DBAT4U -/* BAT5 128K Cacheable, non-guarded +/* + * BAT5 128K Cacheable, non-guarded * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) */ #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) @@ -404,7 +425,8 @@ #define CFG_IBAT5L CFG_DBAT5L #define CFG_IBAT5U CFG_DBAT5U -/* BAT6 32M Cache-inhibited, guarded +/* + * BAT6 32M Cache-inhibited, guarded * 0xfe00_0000 32M FLASH */ #define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \ @@ -427,7 +449,7 @@ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH 1 /* Flash is not usable now */