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rockchip: Add an MMC driver
Add an MMC driver which supports RK3288, but may also support other SoCs. It uses the Designware MMC device. Signed-off-by: Simon Glass <sjg@chromium.org>
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@ -10,6 +10,15 @@ config DM_MMC
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appear as block devices in U-Boot and can support filesystems such
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appear as block devices in U-Boot and can support filesystems such
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as EXT4 and FAT.
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as EXT4 and FAT.
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config ROCKCHIP_DWMMC
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bool "Rockchip SD/MMC controller support"
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depends on DM_MMC && OF_CONTROL
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help
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This enables support for the Rockchip SD/MMM controller, which is
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based on Designware IP. The device is compatible with at least
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SD 3.0, SDIO 3.0 and MMC 4.5 and supports common eMMC chips as well
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as removeable SD and micro-SD cards.
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config SH_SDHI
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config SH_SDHI
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bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
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bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
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depends on RMOBILE
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depends on RMOBILE
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@ -29,6 +29,7 @@ obj-$(CONFIG_MXS_MMC) += mxsmmc.o
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obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
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obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
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obj-$(CONFIG_X86) += pci_mmc.o
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obj-$(CONFIG_X86) += pci_mmc.o
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obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
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obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
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obj-$(CONFIG_ROCKCHIP_DWMMC) += rockchip_dw_mmc.o
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obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
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obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
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obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
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obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
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obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
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obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
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98
drivers/mmc/rockchip_dw_mmc.c
Normal file
98
drivers/mmc/rockchip_dw_mmc.c
Normal file
@ -0,0 +1,98 @@
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/*
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* Copyright (c) 2013 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dwmmc.h>
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#include <errno.h>
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#include <syscon.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/periph.h>
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#include <linux/err.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct rockchip_dwmmc_priv {
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struct udevice *clk;
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struct rk3288_grf *grf;
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struct dwmci_host host;
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};
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static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
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{
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struct udevice *dev = host->priv;
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struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
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int ret;
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ret = clk_set_periph_rate(priv->clk, PERIPH_ID_SDMMC0 + host->dev_index,
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freq);
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if (ret < 0) {
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debug("%s: err=%d\n", __func__, ret);
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return ret;
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}
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return freq;
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}
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static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
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{
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struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
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struct dwmci_host *host = &priv->host;
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host->name = dev->name;
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host->ioaddr = (void *)dev_get_addr(dev);
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host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
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"bus-width", 4);
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host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
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host->priv = dev;
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/* TODO(sjg@chromium.org): Remove the need for this hack */
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host->dev_index = (ulong)host->ioaddr == 0xff0f0000 ? 0 : 1;
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return 0;
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}
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static int rockchip_dwmmc_probe(struct udevice *dev)
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{
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
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struct dwmci_host *host = &priv->host;
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u32 minmax[2];
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int ret;
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priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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if (IS_ERR(priv->grf))
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return PTR_ERR(priv->grf);
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ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &priv->clk);
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if (ret)
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return ret;
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ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
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"clock-freq-min-max", minmax, 2);
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if (!ret)
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ret = add_dwmci(host, minmax[1], minmax[0]);
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if (ret)
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return ret;
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upriv->mmc = host->mmc;
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return 0;
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}
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static const struct udevice_id rockchip_dwmmc_ids[] = {
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{ .compatible = "rockchip,rk3288-dw-mshc" },
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{ }
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};
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U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
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.name = "rockchip_dwmmc",
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.id = UCLASS_MMC,
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.of_match = rockchip_dwmmc_ids,
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.ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
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.probe = rockchip_dwmmc_probe,
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.priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
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};
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