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mips: mt76xx: lowlevel_init.S: Add missing memory controller reset in DDR init

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This fixes an issue which has been noticed on the Gardena board, with
the watchdog enabled, where the watdchdog reset (after a system hang)
did result in reporting of 2.9 GiB and a hang after this. With this
patch applied the memory controller is correctly reset and initialized
again even after a watchdog reset.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Stefan Roese 2018-10-09 08:59:04 +02:00 committed by Daniel Schwierzeck
parent 4751e5595e
commit a8b0bf6313
1 changed files with 6 additions and 0 deletions
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6
arch/mips/mach-mt7620/lowlevel_init.S
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@ -108,6 +108,12 @@ CPLL_READY:
sw t3, 0(t0)
CPLL_DONE:
/* Reset MC */
lw t2, 0x34(s0)
ori t2, BIT(10)
sw t2, 0x34(s0)
nop
/*
* SDR and DDR initialization: delay 200us
*/