board/km: add support for expu1 design based on nxp
The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> [Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Aleksandar Gerasimovski
Priyanka Jain
parent
0b036d4c1b
commit
a7fd6fa1c2
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@ -1491,6 +1491,24 @@ config TARGET_PG_WCOM_SELI8
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SELI8 is a QorIQ LS1021a based service unit card used
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in XMC20 and FOX615 product families.
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config TARGET_PG_WCOM_EXPU1
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bool "Support Hitachi-Powergrids EXPU1 service unit card"
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select ARCH_LS1021A
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select ARCH_SUPPORT_PSCI
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select BOARD_EARLY_INIT_F
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select BOARD_LATE_INIT
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select CPU_V7A
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select SYS_FSL_DDR
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select FSL_DDR_INTERACTIVE
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select VENDOR_KM
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imply SCSI
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help
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Support for Hitachi-Powergrids EXPU1 service unit card.
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EXPU1 is a QorIQ LS1021a based service unit card used
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in XMC20 and FOX615 product families.
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config TARGET_LS1021ATSN
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bool "Support ls1021atsn"
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select ARCH_LS1021A
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@ -411,6 +411,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
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ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
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ls1021a-iot-duart.dtb ls1021a-tsn.dtb
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dtb-$(CONFIG_TARGET_PG_WCOM_SELI8) += ls1021a-pg-wcom-seli8.dtb
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dtb-$(CONFIG_TARGET_PG_WCOM_EXPU1) += ls1021a-pg-wcom-expu1.dtb
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dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
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fsl-ls2080a-qds-42-x.dtb \
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@ -0,0 +1,130 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Hitachi ABB Power Grids EXPU1 board device tree source
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*
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* Copyright 2020 Hitachi ABB Power Grids
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*
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* Copyright 2013-2015 Freescale Semiconductor, Inc.
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*/
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/dts-v1/;
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#include "ls1021a.dtsi"
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/ {
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model = "EXPU1 Service Unit for XMC and FOX";
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aliases {
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enet2-rgmii-debug-phy = &debug_phy;
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};
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chosen {
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stdout-path = &uart0;
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};
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};
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&enet0 {
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status = "okay";
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tbi-handle = <&tbi0>;
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phy-connection-type = "sgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&enet1 {
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status = "okay";
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tbi-handle = <&tbi1>;
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phy-connection-type = "sgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&enet2 {
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phy-handle = <&debug_phy>;
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phy-connection-type = "rgmii-id";
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max-speed = <100>;
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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&dspi1 {
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bus-num = <0>;
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status = "okay";
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zl30343@0 {
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compatible = "gen,spidev", "zarlink,zl30343";
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reg = <0>;
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spi-max-frequency = <8000000>;
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};
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};
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&ifc {
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#address-cells = <2>;
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#size-cells = <1>;
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/* NOR Flash on board */
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ranges = <0x0 0x0 0x60000000 0x04000000>;
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status = "okay";
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x4000000>;
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bank-width = <2>;
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device-width = <1>;
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partition@0 {
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label = "rcw";
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reg = <0x0 0x20000>;
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read-only;
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};
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partition@20000 {
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label = "qe";
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reg = <0x20000 0x20000>;
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};
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/* ZL30343 init data to be added here */
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partition@40000 {
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label = "envred";
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reg = <0x40000 0x20000>;
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};
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partition@60000 {
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label = "env";
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reg = <0x60000 0x20000>;
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};
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partition@100000 {
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label = "u-boot";
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reg = <0x100000 0x100000>;
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};
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partition@200000 {
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label = "ubi0";
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reg = <0x200000 0x3E00000>;
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};
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};
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};
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&mdio0 {
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debug_phy: ethernet-phy@11 {
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reg = <0x11>;
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};
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tbi0: tbi-phy@0xb {
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reg = <0xb>;
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device_type = "tbi-phy";
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};
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};
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&mdio1 {
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tbi1: tbi-phy@0xd {
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reg = <0xd>;
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device_type = "tbi-phy";
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};
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};
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&uart0 {
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status = "okay";
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};
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@ -64,6 +64,13 @@ config SYS_PAX_BASE
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help
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IFC Base Address for PAXx FPGA.
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config SYS_CLIPS_BASE
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hex "CLIPS IFC Base Address"
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default 0x78000000
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depends on ARCH_LS1021A
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help
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IFC Base Address for CLIPS FPGA.
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config KM_CONSOLE_TTY
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string "KM Console"
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default "ttyS0"
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@ -17,3 +17,23 @@ config BOARD_SPECIFIC_OPTIONS
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imply FS_CRAMFS
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endif
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if TARGET_PG_WCOM_EXPU1
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config SYS_BOARD
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default "pg-wcom-ls102xa"
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config SYS_VENDOR
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default "keymile"
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config SYS_SOC
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default "ls102xa"
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config SYS_CONFIG_NAME
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default "pg-wcom-expu1"
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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imply FS_CRAMFS
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endif
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@ -6,5 +6,8 @@ S: Maintained
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F: board/keymile/pg-wcom-ls102xa/
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F: include/configs/km/pg-wcom-ls102xa.h
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F: include/configs/pg-wcom-seli8.h
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F: include/configs/pg-wcom-expu1.h
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F: configs/pg_wcom_seli8_defconfig
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F: configs/pg_wcom_expu1_defconfig
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F: arch/arm/dts/ls1021a-pg-wcom-seli8.dts
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F: arch/arm/dts/ls1021a-pg-wcom-expu1.dts
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@ -70,16 +70,29 @@ int board_early_init_f(void)
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/* QRIO Configuration */
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qrio_uprstreq(UPREQ_CORE_RST);
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if (IS_ENABLED(CONFIG_TARGET_PG_WCOM_SELI8)) {
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qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_wdmask(KM_LIU_RST, true);
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#if CONFIG_IS_ENABLED(TARGET_PG_WCOM_SELI8)
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qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_wdmask(KM_LIU_RST, true);
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qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_wdmask(KM_PAXK_RST, true);
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qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_wdmask(KM_PAXK_RST, true);
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#endif
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qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
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qrio_prst(KM_DBG_ETH_RST, false, false);
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}
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#if CONFIG_IS_ENABLED(TARGET_PG_WCOM_EXPU1)
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qrio_prstcfg(WCOM_TMG_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_wdmask(WCOM_TMG_RST, true);
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qrio_prstcfg(WCOM_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_prst(WCOM_PHY_RST, false, false);
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qrio_prstcfg(WCOM_QSFP_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_wdmask(WCOM_QSFP_RST, true);
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qrio_prstcfg(WCOM_CLIPS_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_prst(WCOM_CLIPS_RST, false, false);
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#endif
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qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
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qrio_prst(KM_DBG_ETH_RST, false, false);
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i2c_deblock_gpio_cfg();
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@ -0,0 +1,70 @@
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CONFIG_ARM=y
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CONFIG_TARGET_PG_WCOM_EXPU1=y
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CONFIG_SYS_TEXT_BASE=0x60100000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_KM_DEF_NETDEV="eth2"
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CONFIG_KM_COMMON_ETH_INIT=y
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CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
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CONFIG_SYS_MEMTEST_START=0x80000000
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CONFIG_SYS_MEMTEST_END=0x9fffffff
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CONFIG_ENV_SIZE=0x4000
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CONFIG_ENV_SECT_SIZE=0x20000
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CONFIG_BOOTCOUNT_BOOTLIMIT=3
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CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
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CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-expu1"
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CONFIG_AHCI=y
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_BOOTDELAY=3
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
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CONFIG_SILENT_CONSOLE=y
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CONFIG_MISC_INIT_R=y
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CONFIG_LAST_STAGE_INIT=y
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_GREPENV=y
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CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_MEMTEST=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_NAND=y
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CONFIG_CMD_NAND_TRIMFFS=y
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CONFIG_CMD_CRAMFS=y
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CONFIG_CMD_MTDPARTS=y
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CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash"
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CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),-(ubi0);68000000.flash:-(ubi1)"
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CONFIG_CMD_UBI=y
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CONFIG_OF_CONTROL=y
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CONFIG_ENV_IS_IN_FLASH=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_ADDR=0x60060000
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CONFIG_ENV_ADDR_REDUND=0x60040000
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CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
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CONFIG_DM=y
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CONFIG_BOOTCOUNT_LIMIT=y
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CONFIG_SYS_FSL_DDR3=y
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# CONFIG_MMC is not set
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CONFIG_SYS_I2C_MXC=y
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CONFIG_SYS_I2C_MXC_I2C1=y
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CONFIG_SYS_I2C_MXC_I2C2=y
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CONFIG_SYS_I2C_MXC_I2C3=y
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CONFIG_MTD=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_FLASH_CFI_MTD=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_PHY_MARVELL=y
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CONFIG_PHY_FIXED=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_PHY_GIGE=y
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CONFIG_MII=y
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CONFIG_TSEC_ENET=y
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CONFIG_SPECIFY_CONSOLE_INDEX=y
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CONFIG_DM_SERIAL=y
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CONFIG_SYS_NS16550=y
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@ -0,0 +1,53 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2020 Hitachi ABB Power Grids
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*/
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#ifndef __CONFIG_PG_WCOM_EXPU1_H
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#define __CONFIG_PG_WCOM_EXPU1_H
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#define WCOM_EXPU1
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#define CONFIG_HOSTNAME "EXPU1"
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#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
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#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
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/* CLIPS FPGA Definitions */
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#define CONFIG_SYS_CSPR3_EXT (0x00)
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#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \
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CSPR_PORT_SIZE_8 | \
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CSPR_MSEL_GPCM | \
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CSPR_V)
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#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
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#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
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CSOR_GPCM_TRHZ_40)
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#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
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FTIM0_GPCM_TEADC(0x7) | \
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FTIM0_GPCM_TEAHC(0x2))
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#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
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FTIM1_GPCM_TRAD(0x12))
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#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
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FTIM2_GPCM_TCH(0x1) | \
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FTIM2_GPCM_TWP(0x12))
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#define CONFIG_SYS_CS3_FTIM3 0x04000000
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/* PRST */
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#define WCOM_CLIPS_RST 0
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#define WCOM_QSFP_RST 1
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#define WCOM_PHY_RST 2
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#define WCOM_TMG_RST 3
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#define KM_DBG_ETH_RST 15
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/* QRIO GPIOs used for deblocking */
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#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
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#define KM_I2C_DEBLOCK_SCL 20
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#define KM_I2C_DEBLOCK_SDA 21
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/* ZL30343 on SPI */
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#define WCOM_ZL30343_CFG_ADDR 0xe8070000
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#define WCOM_ZL30343_SPI_BUS 0
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#define WCOM_ZL30343_CS 0
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#include "km/pg-wcom-ls102xa.h"
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#endif /* __CONFIG_PG_WCOM_EXPU1_H */
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