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https://github.com/brain-hackers/u-boot-brain
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Blackfin: bfin_mac: respect CONFIG_PHY_{ADDR,CLOCK_FREQ}
Rather than having the on-chip MAC hardcoded to phy address 1 and a speed of 2.5mhz, use these as defaults if the board doesn't specify otherwise. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Ben Warren <biggerbadderben@gmail.com>
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@ -22,6 +22,13 @@
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#include "bfin_mac.h"
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#ifndef CONFIG_PHY_ADDR
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# define CONFIG_PHY_ADDR 1
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#endif
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#ifndef CONFIG_PHY_CLOCK_FREQ
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# define CONFIG_PHY_CLOCK_FREQ 2500000
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#endif
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#ifdef CONFIG_POST
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#include <post.h>
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#endif
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@ -265,14 +272,14 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
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/* Odd word alignment for Receive Frame DMA word */
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/* Configure checksum support and rcve frame word alignment */
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bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(2500000)));
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bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ)));
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/* turn on auto-negotiation and wait for link to come up */
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bfin_miiphy_write(dev->name, PHYADDR, MII_BMCR, BMCR_ANENABLE);
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bfin_miiphy_write(dev->name, CONFIG_PHY_ADDR, MII_BMCR, BMCR_ANENABLE);
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count = 0;
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while (1) {
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++count;
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if (bfin_miiphy_read(dev->name, PHYADDR, MII_BMSR, &phydat))
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if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_BMSR, &phydat))
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return -1;
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if (phydat & BMSR_LSTATUS)
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break;
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@ -284,7 +291,7 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
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}
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/* see what kind of link we have */
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if (bfin_miiphy_read(dev->name, PHYADDR, MII_LPA, &phydat))
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if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_LPA, &phydat))
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return -1;
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if (phydat & LPA_DUPLEX)
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*opmode = FDMODE;
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@ -9,7 +9,6 @@
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#ifndef __BFIN_MAC_H__
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#define __BFIN_MAC_H__
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#define PHYADDR 0x01
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#define RECV_BUFSIZE (0x614)
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typedef struct ADI_DMA_CONFIG_REG {
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