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OMAP3+: Introduce generic logic for OMAP voltage controller
OMAP Voltage controller is used to generically talk to PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code in multiple SoC code, introduce a common voltage controller logic which can be re-used from elsewhere. With this change, we replace setup_sri2c with omap_vc_init which has the same functionality, and replace the voltage scale replication in do_scale_vcore and do_scale_tps62361 with omap_vc_bypass_send_value. omap_vc_bypass_send_value can also now be used with any configuration of PMIC. NOTE: Voltage controller controlling I2C_SR is a write-only data path, so no register read operation can be implemented. Reported-by: Isabelle Gros <i-gros@ti.com> Reported-by: Jerome Angeloni <j-angeloni@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
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commit
a78274b205
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@ -37,6 +37,7 @@ ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
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COBJS += hwinit-common.o
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COBJS += hwinit-common.o
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COBJS += clocks-common.o
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COBJS += clocks-common.o
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COBJS += emif-common.o
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COBJS += emif-common.o
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COBJS += vc.o
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endif
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endif
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ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
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ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
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@ -362,27 +362,19 @@ static void setup_non_essential_dplls(void)
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void do_scale_tps62361(u32 reg, u32 volt_mv)
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void do_scale_tps62361(u32 reg, u32 volt_mv)
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{
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{
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u32 temp, step;
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u32 step;
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step = volt_mv - TPS62361_BASE_VOLT_MV;
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step = volt_mv - TPS62361_BASE_VOLT_MV;
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step /= 10;
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step /= 10;
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temp = TPS62361_I2C_SLAVE_ADDR |
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(reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
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(step << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
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PRM_VC_VAL_BYPASS_VALID_BIT;
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debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
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debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
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if (omap_vc_bypass_send_value(TPS62361_I2C_SLAVE_ADDR, reg, step))
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writel(temp, &prcm->prm_vc_val_bypass);
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if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
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&prcm->prm_vc_val_bypass, LDELAY)) {
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puts("Scaling voltage failed for vdd_mpu from TPS\n");
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puts("Scaling voltage failed for vdd_mpu from TPS\n");
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}
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}
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}
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void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
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void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
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{
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{
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u32 temp, offset_code;
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u32 offset_code;
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u32 step = 12660; /* 12.66 mV represented in uV */
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u32 step = 12660; /* 12.66 mV represented in uV */
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u32 offset = volt_mv;
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u32 offset = volt_mv;
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@ -400,16 +392,9 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
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debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
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debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
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offset_code);
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offset_code);
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if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
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temp = SMPS_I2C_SLAVE_ADDR |
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vcore_reg, offset_code))
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(vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
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(offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
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PRM_VC_VAL_BYPASS_VALID_BIT;
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writel(temp, &prcm->prm_vc_val_bypass);
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if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
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&prcm->prm_vc_val_bypass, LDELAY)) {
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printf("Scaling voltage failed for 0x%x\n", vcore_reg);
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printf("Scaling voltage failed for 0x%x\n", vcore_reg);
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}
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}
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}
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static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
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static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
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@ -529,29 +514,6 @@ void setup_clocks_for_console(void)
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CD_CLKCTRL_CLKTRCTRL_SHIFT);
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CD_CLKCTRL_CLKTRCTRL_SHIFT);
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}
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}
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void setup_sri2c(void)
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{
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u32 sys_clk_khz, cycles_hi, cycles_low, temp;
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sys_clk_khz = get_sys_clk_freq() / 1000;
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/*
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* Setup the dedicated I2C controller for Voltage Control
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* I2C clk - high period 40% low period 60%
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*/
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cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
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cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
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/* values to be set in register - less by 5 & 7 respectively */
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cycles_hi -= 5;
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cycles_low -= 7;
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temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
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(cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
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writel(temp, &prcm->prm_vc_cfg_i2c_clk);
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/* Disable high speed mode and all advanced features */
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writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
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}
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void do_enable_clocks(u32 *const *clk_domains,
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void do_enable_clocks(u32 *const *clk_domains,
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u32 *const *clk_modules_hw_auto,
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u32 *const *clk_modules_hw_auto,
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u32 *const *clk_modules_explicit_en,
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u32 *const *clk_modules_explicit_en,
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138
arch/arm/cpu/armv7/omap-common/vc.c
Normal file
138
arch/arm/cpu/armv7/omap-common/vc.c
Normal file
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@ -0,0 +1,138 @@
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/*
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* Voltage Controller implementation for OMAP
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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* Nishanth Menon
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/omap_common.h>
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#include <asm/arch/sys_proto.h>
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/*
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* Define Master code if there are multiple masters on the I2C_SR bus.
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* Normally not required
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*/
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#ifndef CONFIG_OMAP_VC_I2C_HS_MCODE
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#define CONFIG_OMAP_VC_I2C_HS_MCODE 0x0
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#endif
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/* Register defines and masks for VC IP Block */
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/* PRM_VC_CFG_I2C_MODE */
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#define PRM_VC_CFG_I2C_MODE_DFILTEREN_BIT (0x1 << 6)
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#define PRM_VC_CFG_I2C_MODE_SRMODEEN_BIT (0x1 << 4)
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#define PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT (0x1 << 3)
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#define PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT 0x0
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#define PRM_VC_CFG_I2C_MODE_HSMCODE_MASK 0x3
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/* PRM_VC_CFG_I2C_CLK */
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#define PRM_VC_CFG_I2C_CLK_HSCLL_SHIFT 24
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#define PRM_VC_CFG_I2C_CLK_HSCLL_MASK 0xFF
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#define PRM_VC_CFG_I2C_CLK_HSCLH_SHIFT 16
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#define PRM_VC_CFG_I2C_CLK_HSCLH_MASK 0xFF
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#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0
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#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF
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#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8
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#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8)
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/* PRM_VC_VAL_BYPASS */
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#define PRM_VC_VAL_BYPASS_VALID_BIT (0x1 << 24)
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#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0
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#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F
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#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8
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#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF
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#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16
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#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF
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/**
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* omap_vc_init() - Initialization for Voltage controller
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* @speed_khz: I2C buspeed in KHz
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*/
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void omap_vc_init(u16 speed_khz)
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{
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u32 val;
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u32 sys_clk_khz, cycles_hi, cycles_low;
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sys_clk_khz = get_sys_clk_freq() / 1000;
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if (speed_khz > 400) {
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puts("higher speed requested - throttle to 400Khz\n");
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speed_khz = 400;
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}
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/*
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* Setup the dedicated I2C controller for Voltage Control
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* I2C clk - high period 40% low period 60%
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*/
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speed_khz /= 10;
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cycles_hi = sys_clk_khz * 4 / speed_khz;
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cycles_low = sys_clk_khz * 6 / speed_khz;
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/* values to be set in register - less by 5 & 7 respectively */
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cycles_hi -= 5;
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cycles_low -= 7;
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val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
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(cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
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writel(val, &prcm->prm_vc_cfg_i2c_clk);
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val = CONFIG_OMAP_VC_I2C_HS_MCODE <<
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PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT;
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/* No HS mode for now */
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val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT;
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writel(val, &prcm->prm_vc_cfg_i2c_mode);
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}
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/**
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* omap_vc_bypass_send_value() - Send a data using VC Bypass command
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* @sa: 7 bit I2C slave address of the PMIC
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* @reg_addr: I2C register address(8 bit) address in PMIC
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* @reg_data: what 8 bit data to write
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*/
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int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data)
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{
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/*
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* Unfortunately we need to loop here instead of a defined time
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* use arbitary large value
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*/
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u32 timeout = 0xFFFF;
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u32 reg_val;
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sa &= PRM_VC_VAL_BYPASS_SLAVEADDR_MASK;
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reg_addr &= PRM_VC_VAL_BYPASS_REGADDR_MASK;
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reg_data &= PRM_VC_VAL_BYPASS_DATA_MASK;
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/* program VC to send data */
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reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT |
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reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT |
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reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT;
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writel(reg_val, &prcm->prm_vc_val_bypass);
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/* Signal VC to send data */
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writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, &prcm->prm_vc_val_bypass);
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/* Wait on VC to complete transmission */
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do {
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reg_val = readl(&prcm->prm_vc_val_bypass) &
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PRM_VC_VAL_BYPASS_VALID_BIT;
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if (!reg_val)
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break;
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sdelay(100);
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} while (--timeout);
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/* Optional: cleanup PRM_IRQSTATUS_Ax */
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/* In case we can do something about it in future.. */
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if (!timeout)
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return -1;
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/* All good.. */
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return 0;
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}
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@ -275,7 +275,7 @@ void scale_vcores(void)
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{
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{
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u32 volt, omap_rev;
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u32 volt, omap_rev;
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setup_sri2c();
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omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
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omap_rev = omap_revision();
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omap_rev = omap_revision();
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/* TPS - supplies vdd_mpu on 4460 */
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/* TPS - supplies vdd_mpu on 4460 */
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@ -243,7 +243,7 @@ void scale_vcores(void)
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{
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{
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u32 volt;
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u32 volt;
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setup_sri2c();
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omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
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/* Enable 1.22V from TPS for vdd_mpu */
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/* Enable 1.22V from TPS for vdd_mpu */
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volt = 1220;
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volt = 1220;
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#define OMAP_SYS_CLK_IND_38_4_MHZ 6
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#define OMAP_SYS_CLK_IND_38_4_MHZ 6
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#define OMAP_32K_CLK_FREQ 32768
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#define OMAP_32K_CLK_FREQ 32768
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/* PRM_VC_CFG_I2C_CLK */
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#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0
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#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF
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#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8
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#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8)
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/* PRM_VC_VAL_BYPASS */
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/* PRM_VC_VAL_BYPASS */
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#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
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#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
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#define PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000
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#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0
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#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F
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#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8
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#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF
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#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16
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#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF
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/* SMPS */
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/* SMPS */
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#define SMPS_I2C_SLAVE_ADDR 0x12
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#define SMPS_I2C_SLAVE_ADDR 0x12
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#define SMPS_REG_ADDR_VCORE1 0x55
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#define SMPS_REG_ADDR_VCORE1 0x55
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@ -757,7 +743,6 @@ void scale_vcores(void);
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void do_scale_tps62361(u32 reg, u32 volt_mv);
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void do_scale_tps62361(u32 reg, u32 volt_mv);
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u32 omap_ddr_clk(void);
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u32 omap_ddr_clk(void);
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void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
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void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
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void setup_sri2c(void);
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void setup_post_dividers(u32 *const base, const struct dpll_params *params);
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void setup_post_dividers(u32 *const base, const struct dpll_params *params);
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u32 get_sys_clk_index(void);
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u32 get_sys_clk_index(void);
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void enable_basic_clocks(void);
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void enable_basic_clocks(void);
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@ -55,6 +55,8 @@ u32 omap_sdram_size(void);
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u32 cortex_rev(void);
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u32 cortex_rev(void);
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void init_omap_revision(void);
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void init_omap_revision(void);
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void do_io_settings(void);
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void do_io_settings(void);
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void omap_vc_init(u16 speed_khz);
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int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
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/*
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/*
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* This is used to verify if the configuration header
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* This is used to verify if the configuration header
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* was executed by Romcode prior to control of transfer
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* was executed by Romcode prior to control of transfer
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@ -615,23 +615,9 @@ struct omap5_prcm_regs {
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#define OMAP_SYS_CLK_IND_38_4_MHZ 6
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#define OMAP_SYS_CLK_IND_38_4_MHZ 6
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#define OMAP_32K_CLK_FREQ 32768
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#define OMAP_32K_CLK_FREQ 32768
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|
||||||
/* PRM_VC_CFG_I2C_CLK */
|
|
||||||
#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0
|
|
||||||
#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF
|
|
||||||
#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8
|
|
||||||
#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8)
|
|
||||||
|
|
||||||
/* PRM_VC_VAL_BYPASS */
|
/* PRM_VC_VAL_BYPASS */
|
||||||
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
|
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
|
||||||
|
|
||||||
#define PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000
|
|
||||||
#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0
|
|
||||||
#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F
|
|
||||||
#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8
|
|
||||||
#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF
|
|
||||||
#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16
|
|
||||||
#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF
|
|
||||||
|
|
||||||
/* SMPS */
|
/* SMPS */
|
||||||
#define SMPS_I2C_SLAVE_ADDR 0x12
|
#define SMPS_I2C_SLAVE_ADDR 0x12
|
||||||
#define SMPS_REG_ADDR_VCORE1 0x55
|
#define SMPS_REG_ADDR_VCORE1 0x55
|
||||||
|
@ -703,7 +689,6 @@ void scale_vcores(void);
|
||||||
void do_scale_tps62361(u32 reg, u32 volt_mv);
|
void do_scale_tps62361(u32 reg, u32 volt_mv);
|
||||||
u32 omap_ddr_clk(void);
|
u32 omap_ddr_clk(void);
|
||||||
void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
|
void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
|
||||||
void setup_sri2c(void);
|
|
||||||
void setup_post_dividers(u32 *const base, const struct dpll_params *params);
|
void setup_post_dividers(u32 *const base, const struct dpll_params *params);
|
||||||
u32 get_sys_clk_index(void);
|
u32 get_sys_clk_index(void);
|
||||||
void enable_basic_clocks(void);
|
void enable_basic_clocks(void);
|
||||||
|
|
|
@ -55,6 +55,8 @@ u32 omap_sdram_size(void);
|
||||||
u32 cortex_rev(void);
|
u32 cortex_rev(void);
|
||||||
void init_omap_revision(void);
|
void init_omap_revision(void);
|
||||||
void do_io_settings(void);
|
void do_io_settings(void);
|
||||||
|
void omap_vc_init(u16 speed_khz);
|
||||||
|
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* This is used to verify if the configuration header
|
* This is used to verify if the configuration header
|
||||||
|
|
Loading…
Reference in New Issue
Block a user