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riscv: cpu: fu740: Add support for cpu fu740
Add SiFive fu740 cpu to support RISC-V arch Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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@ -61,6 +61,7 @@ source "board/sipeed/maix/Kconfig"
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# platform-specific options below
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# platform-specific options below
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source "arch/riscv/cpu/ax25/Kconfig"
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source "arch/riscv/cpu/ax25/Kconfig"
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source "arch/riscv/cpu/fu540/Kconfig"
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source "arch/riscv/cpu/fu540/Kconfig"
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source "arch/riscv/cpu/fu740/Kconfig"
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source "arch/riscv/cpu/generic/Kconfig"
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source "arch/riscv/cpu/generic/Kconfig"
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# architecture-specific options below
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# architecture-specific options below
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37
arch/riscv/cpu/fu740/Kconfig
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37
arch/riscv/cpu/fu740/Kconfig
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@ -0,0 +1,37 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2020-2021 SiFive, Inc
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# Pragnesh Patel <pragnesh.patel@sifive.com>
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config SIFIVE_FU740
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bool
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select ARCH_EARLY_INIT_R
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select RAM
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select SPL_RAM if SPL
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imply CPU
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imply CPU_RISCV
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imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
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imply SPL_SIFIVE_CLINT
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imply CMD_CPU
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imply SPL_CPU
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imply SPL_OPENSBI
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imply SPL_LOAD_FIT
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imply SMP
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imply CLK_SIFIVE
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imply CLK_SIFIVE_PRCI
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imply SIFIVE_SERIAL
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imply MACB
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imply MII
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imply SPI
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imply SPI_SIFIVE
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imply MMC
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imply MMC_SPI
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imply MMC_BROKEN_CD
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imply CMD_MMC
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imply DM_GPIO
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imply SIFIVE_GPIO
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imply CMD_GPIO
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imply MISC
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imply SIFIVE_OTP
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imply DM_PWM
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imply PWM_SIFIVE
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12
arch/riscv/cpu/fu740/Makefile
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12
arch/riscv/cpu/fu740/Makefile
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@ -0,0 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2020-2021 SiFive, Inc
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# Pragnesh Patel <pragnesh.patel@sifive.com>
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ifeq ($(CONFIG_SPL_BUILD),y)
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obj-y += spl.o
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else
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obj-y += dram.o
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obj-y += cpu.o
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obj-y += cache.o
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endif
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55
arch/riscv/cpu/fu740/cache.c
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55
arch/riscv/cpu/fu740/cache.c
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@ -0,0 +1,55 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020-2021 SiFive, Inc
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*
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* Authors:
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* Pragnesh Patel <pragnesh.patel@sifive.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <asm/global_data.h>
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/* Register offsets */
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#define L2_CACHE_CONFIG 0x000
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#define L2_CACHE_ENABLE 0x008
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#define MASK_NUM_WAYS GENMASK(15, 8)
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#define NUM_WAYS_SHIFT 8
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DECLARE_GLOBAL_DATA_PTR;
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int cache_enable_ways(void)
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{
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const void *blob = gd->fdt_blob;
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int node;
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fdt_addr_t base;
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u32 config;
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u32 ways;
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volatile u32 *enable;
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node = fdt_node_offset_by_compatible(blob, -1,
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"sifive,fu740-c000-ccache");
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if (node < 0)
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return node;
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base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
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NULL, false);
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if (base == FDT_ADDR_T_NONE)
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return FDT_ADDR_T_NONE;
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config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
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ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
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enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
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/* memory barrier */
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mb();
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(*enable) = ways - 1;
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/* memory barrier */
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mb();
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return 0;
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}
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22
arch/riscv/cpu/fu740/cpu.c
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22
arch/riscv/cpu/fu740/cpu.c
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <irq_func.h>
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#include <asm/cache.h>
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/*
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* cleanup_before_linux() is called just before we call linux
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* it prepares the processor for linux
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*
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* we disable interrupt and caches.
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*/
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int cleanup_before_linux(void)
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{
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disable_interrupts();
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cache_flush();
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return 0;
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}
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38
arch/riscv/cpu/fu740/dram.c
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38
arch/riscv/cpu/fu740/dram.c
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <init.h>
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#include <linux/sizes.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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return fdtdec_setup_mem_size_base();
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}
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int dram_init_banksize(void)
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{
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return fdtdec_setup_memory_banksize();
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}
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ulong board_get_usable_ram_top(ulong total_size)
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{
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#ifdef CONFIG_64BIT
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/*
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* Ensure that we run from first 4GB so that all
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* addresses used by U-Boot are 32bit addresses.
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*
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* This in-turn ensures that 32bit DMA capable
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* devices work fine because DMA mapping APIs will
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* provide 32bit DMA addresses only.
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*/
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if (gd->ram_top > SZ_4G)
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return SZ_4G;
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#endif
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return gd->ram_top;
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}
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23
arch/riscv/cpu/fu740/spl.c
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23
arch/riscv/cpu/fu740/spl.c
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020-201 SiFive, Inc
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* Pragnesh Patel <pragnesh.patel@sifive.com>
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*/
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#include <dm.h>
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#include <log.h>
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int spl_soc_init(void)
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{
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int ret;
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struct udevice *dev;
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/* DDR init */
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM init failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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14
arch/riscv/include/asm/arch-fu740/cache.h
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14
arch/riscv/include/asm/arch-fu740/cache.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020-2021 SiFive, Inc.
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*
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* Authors:
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* Pragnesh Patel <pragnesh.patel@sifve.com>
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*/
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#ifndef _CACHE_SIFIVE_H
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#define _CACHE_SIFIVE_H
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int cache_enable_ways(void);
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#endif /* _CACHE_SIFIVE_H */
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14
arch/riscv/include/asm/arch-fu740/clk.h
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14
arch/riscv/include/asm/arch-fu740/clk.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2020-2021 SiFive Inc
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*
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* Authors:
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* Pragnesh Patel <pragnesh.patel@sifive.com>
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*/
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#ifndef __CLK_SIFIVE_H
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#define __CLK_SIFIVE_H
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/* Note: This is a placeholder header for driver compilation. */
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#endif
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38
arch/riscv/include/asm/arch-fu740/gpio.h
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38
arch/riscv/include/asm/arch-fu740/gpio.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020-2021 SiFive, Inc.
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*/
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#ifndef _GPIO_SIFIVE_H
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#define _GPIO_SIFIVE_H
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#define GPIO_INPUT_VAL 0x00
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#define GPIO_INPUT_EN 0x04
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#define GPIO_OUTPUT_EN 0x08
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#define GPIO_OUTPUT_VAL 0x0C
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#define GPIO_RISE_IE 0x18
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#define GPIO_RISE_IP 0x1C
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#define GPIO_FALL_IE 0x20
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#define GPIO_FALL_IP 0x24
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#define GPIO_HIGH_IE 0x28
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#define GPIO_HIGH_IP 0x2C
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#define GPIO_LOW_IE 0x30
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#define GPIO_LOW_IP 0x34
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#define GPIO_OUTPUT_XOR 0x40
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#define NR_GPIOS 16
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enum gpio_state {
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LOW,
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HIGH
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};
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/* Details about a GPIO bank */
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struct sifive_gpio_plat {
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void *base; /* address of registers in physical memory */
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};
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#define SIFIVE_GENERIC_GPIO_NR(port, index) \
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(((port) * NR_GPIOS) + ((index) & (NR_GPIOS - 1)))
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#endif /* _GPIO_SIFIVE_H */
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13
arch/riscv/include/asm/arch-fu740/reset.h
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13
arch/riscv/include/asm/arch-fu740/reset.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2020-2021 SiFive, Inc.
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*
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* Author: Sagar Kadam <sagar.kadam@sifive.com>
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*/
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#ifndef __RESET_SIFIVE_H
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#define __RESET_SIFIVE_H
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int sifive_reset_bind(struct udevice *dev, ulong count);
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#endif
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14
arch/riscv/include/asm/arch-fu740/spl.h
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14
arch/riscv/include/asm/arch-fu740/spl.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020-2021 SiFive, Inc.
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*
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* Authors:
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* Pragnesh Patel <pragnesh.patel@sifve.com>
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*/
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#ifndef _SPL_SIFIVE_H
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#define _SPL_SIFIVE_H
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int spl_soc_init(void);
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#endif /* _SPL_SIFIVE_H */
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