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https://github.com/brain-hackers/u-boot-brain
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arm: at91: Add gardena-gateway-at91sam support
The GARDENA smart Gateway boards are equipped with an Atmel / Microchip AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage. This patch adds support for this board including SPL support. Therefore the AT91Boostrap is not needed on this platform any more. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Stefan Roese
Eugen Hristev
parent
d4c8873f93
commit
a71e2f933b
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@ -609,6 +609,9 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
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dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
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dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \
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at91sam9g25-gardena-smart-gateway.dtb
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dtb-$(CONFIG_TARGET_ETHERNUT5) += ethernut5.dtb
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dtb-$(CONFIG_TARGET_USB_A9263) += usb_a9263.dtb
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@ -0,0 +1,5 @@
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// SPDX-License-Identifier: GPL-2.0+
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&dbgu {
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u-boot,dm-pre-reloc;
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};
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120
arch/arm/dts/at91sam9g25-gardena-smart-gateway.dts
Normal file
120
arch/arm/dts/at91sam9g25-gardena-smart-gateway.dts
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@ -0,0 +1,120 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Device Tree file for the GARDENA smart Gateway (AT91SAM)
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*
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* Copyright (C) 2012 Atmel,
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* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
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*/
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/dts-v1/;
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#include "at91sam9g25.dtsi"
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/ {
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model = "GARDENA smart Gateway (AT91SAM)";
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compatible = "gardena,smart-gateway-at91sam", "atmel,at91sam9";
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aliases {
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serial0 = &dbgu;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory {
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reg = <0x20000000 0x8000000>;
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};
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clocks {
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slow_xtal {
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clock-frequency = <32768>;
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};
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main_xtal {
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clock-frequency = <12000000>;
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};
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};
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leds {
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compatible = "gpio-leds";
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power_blue {
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label = "smartgw:power:blue";
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gpios = <&pioC 21 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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power_green {
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label = "smartgw:power:green";
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gpios = <&pioC 20 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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power_red {
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label = "smartgw:power:red";
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gpios = <&pioC 19 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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radio_blue {
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label = "smartgw:radio:blue";
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gpios = <&pioC 18 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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radio_green {
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label = "smartgw:radio:green";
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gpios = <&pioC 17 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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radio_red {
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label = "smartgw:radio:red";
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gpios = <&pioC 16 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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internet_blue {
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label = "smartgw:internet:blue";
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gpios = <&pioC 15 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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internet_green {
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label = "smartgw:internet:green";
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gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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internet_red {
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label = "smartgw:internet:red";
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gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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};
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};
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&dbgu {
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status = "okay";
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};
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&macb0 {
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phy-mode = "rmii";
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status = "okay";
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};
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&nand0 {
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nand-bus-width = <8>;
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nand-ecc-mode = "hw";
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atmel,has-pmecc; /* Enable PMECC */
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atmel,pmecc-cap = <2>;
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atmel,pmecc-sector-size = <512>;
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nand-on-flash-bbt;
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status = "okay";
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};
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&watchdog {
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status = "okay";
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timeout-sec = <16>;
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};
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@ -147,6 +147,13 @@ config TARGET_AT91SAM9X5EK
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select BOARD_LATE_INIT
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select SUPPORT_SPL
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config TARGET_GARDENA_SMART_GATEWAY_AT91SAM
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bool "GARDENA smart Gateway (AT91SAM)"
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select AT91SAM9X5
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select BOARD_EARLY_INIT_F
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select BOARD_LATE_INIT
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select SUPPORT_SPL
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config TARGET_SAMA5D2_PTC_EK
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bool "SAMA5D2 PTC EK board"
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select BOARD_EARLY_INIT_F
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@ -283,6 +290,7 @@ source "board/bluewater/snapper9260/Kconfig"
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source "board/calao/usb_a9263/Kconfig"
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source "board/egnite/ethernut5/Kconfig"
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source "board/esd/meesc/Kconfig"
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source "board/gardena/smart-gateway-at91sam/Kconfig"
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source "board/l+g/vinco/Kconfig"
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source "board/mini-box/picosam9g45/Kconfig"
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source "board/ronetix/pm9261/Kconfig"
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12
board/gardena/smart-gateway-at91sam/Kconfig
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12
board/gardena/smart-gateway-at91sam/Kconfig
Normal file
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@ -0,0 +1,12 @@
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if TARGET_GARDENA_SMART_GATEWAY_AT91SAM
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config SYS_BOARD
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default "smart-gateway-at91sam"
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config SYS_VENDOR
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default "gardena"
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config SYS_CONFIG_NAME
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default "gardena-smart-gateway-at91sam"
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endif
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7
board/gardena/smart-gateway-at91sam/MAINTAINERS
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7
board/gardena/smart-gateway-at91sam/MAINTAINERS
Normal file
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@ -0,0 +1,7 @@
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GARDENA_SMART_GATEWAY_AT91SAM BOARD
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M: Stefan Roese <sr@denx.de>
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S: Maintained
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F: board/gardena/smart-gateway-at91sam/
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F: include/configs/gardena-smart-gateway-at91sam.h
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F: configs/gardena-smart-gateway-at91sam_defconfig
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F: arch/arm/dts/gardena-smart-gateway-at91sam.dts
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7
board/gardena/smart-gateway-at91sam/Makefile
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7
board/gardena/smart-gateway-at91sam/Makefile
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@ -0,0 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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obj-y += board.o
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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endif
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59
board/gardena/smart-gateway-at91sam/board.c
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59
board/gardena/smart-gateway-at91sam/board.c
Normal file
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@ -0,0 +1,59 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Atmel Corporation
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* Copyright (C) 2019 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <led.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/clk.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void at91_prepare_cpu_var(void)
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{
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env_set("cpu", get_cpu_name());
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}
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int board_late_init(void)
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{
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at91_prepare_cpu_var();
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if (IS_ENABLED(CONFIG_LED))
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led_default_state();
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return 0;
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}
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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at91_seriald_hw_init();
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}
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#endif
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int board_early_init_f(void)
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{
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#ifdef CONFIG_DEBUG_UART
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debug_uart_init();
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#endif
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return 0;
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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135
board/gardena/smart-gateway-at91sam/spl.c
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135
board/gardena/smart-gateway-at91sam/spl.c
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@ -0,0 +1,135 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Atmel Corporation
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* Copyright (C) 2019 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <nand.h>
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#include <spl.h>
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#include <asm/arch/at91sam9x5_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/atmel_mpddrc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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static void at91sam9x5ek_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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unsigned long csa;
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/* Enable CS3 */
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csa = readl(&matrix->ebicsa);
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csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
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/* NAND flash on D16 */
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csa |= AT91_MATRIX_NFD0_ON_D16;
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/* Configure IO drive */
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csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
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writel(csa, &matrix->ebicsa);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
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AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_MODE_TDF_CYCLE(1),
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&smc->cs[3].mode);
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at91_periph_clk_enable(ATMEL_ID_PIOCD);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
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}
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void at91_spl_board_init(void)
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{
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at91sam9x5ek_nand_hw_init();
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}
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static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
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{
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ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
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ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
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ATMEL_MPDDRC_CR_NR_ROW_13 |
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ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
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ATMEL_MPDDRC_CR_NB_8BANKS |
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ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
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ddr2->rtr = 0x411;
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ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
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8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
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ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
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200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
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19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
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18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
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ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
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2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
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3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
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7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
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2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
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}
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void mem_init(void)
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{
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct atmel_mpddrc_config ddr2;
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unsigned long csa;
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ddr2_conf(&ddr2);
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/* Enable DDR2 clock */
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writel(AT91_PMC_DDR, &pmc->scer);
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/* Chip select 1 is for DDR2/SDRAM */
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csa = readl(&matrix->ebicsa);
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csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
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csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
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csa |= AT91_MATRIX_EBI_DBPD_OFF;
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csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
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writel(csa, &matrix->ebicsa);
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
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}
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83
configs/gardena-smart-gateway-at91sam_defconfig
Normal file
83
configs/gardena-smart-gateway-at91sam_defconfig
Normal file
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@ -0,0 +1,83 @@
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CONFIG_ARM=y
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CONFIG_SYS_THUMB_BUILD=y
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CONFIG_ARCH_AT91=y
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CONFIG_SYS_TEXT_BASE=0x22900000
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CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM=y
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CONFIG_SPL_GPIO_SUPPORT=y
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_SPL_SERIAL_SUPPORT=y
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CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
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CONFIG_SPL=y
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CONFIG_DEBUG_UART_BOARD_INIT=y
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CONFIG_DEBUG_UART_BASE=0xfffff200
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CONFIG_DEBUG_UART_CLOCK=132000000
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CONFIG_SMBIOS_PRODUCT_NAME="at91sam9x5ek"
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CONFIG_DEBUG_UART=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_FIT=y
|
||||
CONFIG_NAND_BOOT=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw"
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
CONFIG_ARCH_EARLY_INIT_R=y
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
# CONFIG_TPL_BANNER_PRINT is not set
|
||||
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
|
||||
CONFIG_SPL_NAND_SUPPORT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_DM=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_MTD=y
|
||||
CONFIG_CMD_NAND=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=nand0"
|
||||
CONFIG_MTDPARTS_DEFAULT="nand0:1536k(uboot),1024k(unused),512k(dtb_old),4608k(kernel_old),86528k(ubi),-(rootfs_old)"
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g25-gardena-smart-gateway"
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupts interrupt-parent interrupts-extended dmas dma-names"
|
||||
CONFIG_ENV_IS_IN_UBI=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_BLK=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_CLK_AT91=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_AT91_GPIO=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_NAND_ATMEL=y
|
||||
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
|
||||
# CONFIG_CONFIG_UBI_SILENCE_MSG is not set
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MACB=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_AT91=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_DEBUG_UART_ATMEL=y
|
||||
CONFIG_ATMEL_USART=y
|
||||
CONFIG_TIMER=y
|
||||
CONFIG_SPL_TIMER=y
|
||||
CONFIG_ATMEL_PIT_TIMER=y
|
||||
# CONFIG_SYS_WHITE_ON_BLACK is not set
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_WDT=y
|
||||
CONFIG_WDT_AT91=y
|
||||
# CONFIG_UBIFS_SILENCE_MSG is not set
|
||||
CONFIG_USE_TINY_PRINTF=y
|
||||
88
include/configs/gardena-smart-gateway-at91sam.h
Normal file
88
include/configs/gardena-smart-gateway-at91sam.h
Normal file
|
|
@ -0,0 +1,88 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2012 Atmel Corporation
|
||||
* Copyright (C) 2019 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* Configuation settings for the GARDENA smart Gateway (AT91SAM9G25)
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H__
|
||||
#define __CONFIG_H__
|
||||
|
||||
/* ARM asynchronous clock */
|
||||
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
|
||||
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#endif
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
|
||||
|
||||
/* general purpose I/O */
|
||||
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
|
||||
|
||||
/* SDRAM */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x20000000
|
||||
#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
|
||||
|
||||
/* NAND flash */
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_DBW_8 1
|
||||
/* our ALE is AD21 */
|
||||
#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
|
||||
/* our CLE is AD22 */
|
||||
#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
|
||||
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
|
||||
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
|
||||
|
||||
/* environment organization */
|
||||
#define CONFIG_ENV_UBI_PART "ubi"
|
||||
#define CONFIG_ENV_UBI_VOLUME "env"
|
||||
#define CONFIG_ENV_UBI_VOLUME_REDUND "env_r"
|
||||
#define CONFIG_ENV_SIZE (64 << 10)
|
||||
|
||||
/* SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x300000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x7000
|
||||
#define CONFIG_SPL_STACK 0x308000
|
||||
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
|
||||
|
||||
#define CONFIG_SYS_MASTER_CLOCK 132096000
|
||||
#define CONFIG_SYS_AT91_PLLA 0x20c73f03
|
||||
#define CONFIG_SYS_MCKR 0x1301
|
||||
#define CONFIG_SYS_MCKR_CSS 0x1302
|
||||
|
||||
#define CONFIG_SPL_NAND_DRIVERS
|
||||
#define CONFIG_SPL_NAND_BASE
|
||||
#define CONFIG_SPL_NAND_RAW_ONLY
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
|
||||
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_OOBSIZE 64
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
|
||||
#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
|
||||
#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user