Merge branch 'master' of http://git.denx.de/u-boot-sunxi

arch/arm/Kconfig

@@ -524,6 +524,7 @@ config ARCH_SUNXI
 	select OF_SEPARATE
 	select SPL_STACK_R if !MACH_SUN9I
 	select SPL_SYS_MALLOC_SIMPLE if !MACH_SUN9I
+	select SYS_NS16550
 	select USB
 	select USB_STORAGE
 	select USB_KEYBOARD

arch/arm/cpu/armv7/sunxi/Makefile

@@ -26,13 +26,18 @@ obj-$(CONFIG_MACH_SUN4I)	+= clock_sun4i.o
 obj-$(CONFIG_MACH_SUN5I)	+= clock_sun4i.o
 obj-$(CONFIG_MACH_SUN6I)	+= clock_sun6i.o
 obj-$(CONFIG_MACH_SUN7I)	+= clock_sun4i.o
+ifdef CONFIG_MACH_SUN8I_A83T
+obj-y				+= clock_sun8i_a83t.o
+else
 obj-$(CONFIG_MACH_SUN8I)	+= clock_sun6i.o
+endif
 obj-$(CONFIG_MACH_SUN9I)	+= clock_sun9i.o
 obj-$(CONFIG_MACH_SUN6I)	+= tzpc.o
 
 obj-$(CONFIG_AXP152_POWER)	+= pmic_bus.o
 obj-$(CONFIG_AXP209_POWER)	+= pmic_bus.o
 obj-$(CONFIG_AXP221_POWER)	+= pmic_bus.o
+obj-$(CONFIG_AXP818_POWER)	+= pmic_bus.o
 
 ifndef CONFIG_SPL_BUILD
 ifdef CONFIG_ARMV7_PSCI
@@ -49,6 +54,7 @@ obj-$(CONFIG_MACH_SUN6I)	+= dram_sun6i.o
 obj-$(CONFIG_MACH_SUN7I)	+= dram_sun4i.o
 obj-$(CONFIG_MACH_SUN8I_A23)	+= dram_sun8i_a23.o
 obj-$(CONFIG_MACH_SUN8I_A33)	+= dram_sun8i_a33.o
+obj-$(CONFIG_MACH_SUN8I_A83T)	+= dram_sun8i_a83t.o
 obj-$(CONFIG_MACH_SUN8I_H3)	+= dram_sun8i_h3.o
 obj-y	+= fel_utils.o
 endif

arch/arm/cpu/armv7/sunxi/board.c

@@ -76,6 +76,10 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
+	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);

arch/arm/cpu/armv7/sunxi/clock_sun4i.c

@@ -59,7 +59,7 @@ void clock_init_uart(void)
 
 	/* open the clock for uart */
 	setbits_le32(&ccm->apb1_gate,
-		CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1));
+		CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX - 1));
 }
 
 int clock_twi_onoff(int port, int state)
@@ -67,16 +67,13 @@ int clock_twi_onoff(int port, int state)
 	struct sunxi_ccm_reg *const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
-	if (port > 2)
-		return -1;
-
 	/* set the apb clock gate for twi */
 	if (state)
 		setbits_le32(&ccm->apb1_gate,
-			     CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
+			     CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
 	else
 		clrbits_le32(&ccm->apb1_gate,
-			     CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
+			     CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
 
 	return 0;
 }

arch/arm/cpu/armv7/sunxi/clock_sun6i.c

@@ -77,9 +77,6 @@ int clock_twi_onoff(int port, int state)
 	struct sunxi_ccm_reg *const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
-	if (port > 3)
-		return -1;
-
 	/* set the apb clock gate for twi */
 	if (state)
 		setbits_le32(&ccm->apb2_gate,

arch/arm/cpu/armv7/sunxi/clock_sun8i_a83t.c

@@ -0,0 +1,136 @@
+/*
+ * A83 specific clock code
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+#ifdef CONFIG_SPL_BUILD
+void clock_init_safe(void)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	clock_set_pll1(408000000);
+	/* enable pll_hsic, default is 480M */
+	writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg);
+	writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg);
+	while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {}
+
+	/* switch to default 24MHz before changing to hsic */
+	writel(0x0, &ccm->cci400_cfg);
+	sdelay(50);
+	writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg);
+	sdelay(100);
+
+	/* switch before changing pll6 */
+	clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK,
+			AHB1_CLK_SRC_OSC24M);
+	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+	while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {}
+
+	writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
+	writel(CCM_MBUS_RESET_RESET, &ccm->mbus_reset);
+	writel(MBUS_CLK_DEFAULT, &ccm->mbus_clk_cfg);
+
+	/* timestamp */
+	writel(1, 0x01720000);
+}
+#endif
+
+void clock_init_uart(void)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	/* uart clock source is apb2 */
+	writel(APB2_CLK_SRC_OSC24M|
+	       APB2_CLK_RATE_N_1|
+	       APB2_CLK_RATE_M(1),
+	       &ccm->apb2_div);
+
+	/* open the clock for uart */
+	setbits_le32(&ccm->apb2_gate,
+		     CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
+				       CONFIG_CONS_INDEX - 1));
+
+	/* deassert uart reset */
+	setbits_le32(&ccm->apb2_reset_cfg,
+		     1 << (APB2_RESET_UART_SHIFT +
+			   CONFIG_CONS_INDEX - 1));
+}
+
+#ifdef CONFIG_SPL_BUILD
+void clock_set_pll1(unsigned int clk)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	const int p = 0;
+
+	/* Switch to 24MHz clock while changing PLL1 */
+	writel(AXI_DIV_2 << AXI0_DIV_SHIFT |
+		AXI_DIV_2 << AXI1_DIV_SHIFT |
+		CPU_CLK_SRC_OSC24M << C0_CPUX_CLK_SRC_SHIFT |
+		CPU_CLK_SRC_OSC24M << C1_CPUX_CLK_SRC_SHIFT,
+	       &ccm->cpu_axi_cfg);
+
+	/* clk = 24*n/p, p is ignored if clock is >288MHz */
+	writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 |
+		CCM_PLL1_CTRL_N(clk / 24000000),
+		&ccm->pll1_c0_cfg);
+	while (!(readl(&ccm->pll_stable_status) & 0x01)) {}
+
+	writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 |
+		CCM_PLL1_CTRL_N(clk / (24000000)),
+		&ccm->pll1_c1_cfg);
+	while (!(readl(&ccm->pll_stable_status) & 0x02)) {}
+
+	/* Switch CPU to PLL1 */
+	writel(AXI_DIV_2 << AXI0_DIV_SHIFT |
+		AXI_DIV_2 << AXI1_DIV_SHIFT |
+		CPU_CLK_SRC_PLL1 << C0_CPUX_CLK_SRC_SHIFT |
+		CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT,
+	       &ccm->cpu_axi_cfg);
+}
+#endif
+
+void clock_set_pll5(unsigned int clk)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	unsigned int div1 = 0, div2 = 0;
+
+	/* A83T PLL5 DDR rate = 24000000 * (n+1)/(div1+1)/(div2+1) */
+	writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
+			CCM_PLL5_CTRL_N(clk / (24000000)) |
+			div2 << CCM_PLL5_DIV2_SHIFT |
+			div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg);
+
+	udelay(5500);
+}
+
+
+unsigned int clock_get_pll6(void)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	uint32_t rval = readl(&ccm->pll6_cfg);
+	int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
+	int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
+			CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
+	int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
+			CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
+	return 24000000 * n / div1 / div2;
+}

arch/arm/cpu/armv7/sunxi/cpu_info.c

@@ -73,6 +73,8 @@ int print_cpuinfo(void)
 	puts("CPU:   Allwinner H3 (SUN8I)\n");
 #elif defined CONFIG_MACH_SUN9I
 	puts("CPU:   Allwinner A80 (SUN9I)\n");
+#elif defined CONFIG_MACH_SUN8I_A83T
+	puts("CPU:   Allwinner A83T (SUN8I)\n");
 #else
 #warning Please update cpu_info.c with correct CPU information
 	puts("CPU:   SUNXI Family\n");

arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c

@@ -0,0 +1,424 @@
+/*
+ * Sun8i a33 platform dram controller init.
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ *                         Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015      Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2015      Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/prcm.h>
+
+#define DRAM_CLK_MUL 2
+#define DRAM_CLK_DIV 1
+
+struct dram_para {
+	u8 cs1;
+	u8 seq;
+	u8 bank;
+	u8 rank;
+	u8 rows;
+	u8 bus_width;
+	u16 page_size;
+};
+
+static void mctl_set_cr(struct dram_para *para)
+{
+	struct sunxi_mctl_com_reg * const mctl_com =
+			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+	writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
+		MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 |
+		(para->seq ? MCTL_CR_SEQUENCE : 0) |
+		((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
+		MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
+		MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
+		&mctl_com->cr);
+}
+
+static void auto_detect_dram_size(struct dram_para *para)
+{
+	u8 orig_rank = para->rank;
+	int rows, columns;
+
+	/* Row detect */
+	para->page_size = 512;
+	para->seq = 1;
+	para->rows = 16;
+	para->rank = 1;
+	mctl_set_cr(para);
+	for (rows = 11 ; rows < 16 ; rows++) {
+		if (mctl_mem_matches(1 << (rows + 9))) /* row-column */
+			break;
+	}
+
+	/* Column (page size) detect */
+	para->rows = 11;
+	para->page_size = 8192;
+	mctl_set_cr(para);
+	for (columns = 9 ; columns < 13 ; columns++) {
+		if (mctl_mem_matches(1 << columns))
+			break;
+	}
+
+	para->seq = 0;
+	para->rank = orig_rank;
+	para->rows = rows;
+	para->page_size = 1 << columns;
+	mctl_set_cr(para);
+}
+
+static inline int ns_to_t(int nanoseconds)
+{
+	const unsigned int ctrl_freq =
+		CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV;
+
+	return (ctrl_freq * nanoseconds + 999) / 1000;
+}
+
+static void auto_set_timing_para(struct dram_para *para)
+{
+	struct sunxi_mctl_ctl_reg * const mctl_ctl =
+		(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+	u32 reg_val;
+
+	u8 tccd		= 2;
+	u8 tfaw		= ns_to_t(50);
+	u8 trrd		= max(ns_to_t(10), 4);
+	u8 trcd		= ns_to_t(15);
+	u8 trc		= ns_to_t(53);
+	u8 txp		= max(ns_to_t(8), 3);
+	u8 twtr		= max(ns_to_t(8), 4);
+	u8 trtp		= max(ns_to_t(8), 4);
+	u8 twr		= max(ns_to_t(15), 3);
+	u8 trp		= ns_to_t(15);
+	u8 tras		= ns_to_t(38);
+
+	u16 trefi	= ns_to_t(7800) / 32;
+	u16 trfc	= ns_to_t(350);
+
+	/* Fixed timing parameters */
+	u8 tmrw		= 0;
+	u8 tmrd		= 4;
+	u8 tmod		= 12;
+	u8 tcke		= 3;
+	u8 tcksrx	= 5;
+	u8 tcksre	= 5;
+	u8 tckesr	= 4;
+	u8 trasmax	= 24;
+	u8 tcl		= 6; /* CL 12 */
+	u8 tcwl		= 4; /* CWL 8 */
+	u8 t_rdata_en	= 4;
+	u8 wr_latency	= 2;
+
+	u32 tdinit0	= (500 * CONFIG_DRAM_CLK) + 1;		/* 500us */
+	u32 tdinit1	= (360 * CONFIG_DRAM_CLK) / 1000 + 1;	/* 360ns */
+	u32 tdinit2	= (200 * CONFIG_DRAM_CLK) + 1;		/* 200us */
+	u32 tdinit3	= (1 * CONFIG_DRAM_CLK) + 1;		/* 1us */
+
+	u8 twtp		= tcwl + 2 + twr;	/* WL + BL / 2 + tWR */
+	u8 twr2rd	= tcwl + 2 + twtr;	/* WL + BL / 2 + tWTR */
+	u8 trd2wr	= tcl + 2 + 1 - tcwl;	/* RL + BL / 2 + 2 - WL */
+
+	/* Set work mode register */
+	mctl_set_cr(para);
+	/* Set mode register */
+	writel(MCTL_MR0, &mctl_ctl->mr0);
+	writel(MCTL_MR1, &mctl_ctl->mr1);
+	writel(MCTL_MR2, &mctl_ctl->mr2);
+	writel(MCTL_MR3, &mctl_ctl->mr3);
+	/* Set dram timing */
+	reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0);
+	writel(reg_val, &mctl_ctl->dramtmg0);
+	reg_val = (txp << 16) | (trtp << 8) | (trc << 0);
+	writel(reg_val, &mctl_ctl->dramtmg1);
+	reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0);
+	writel(reg_val, &mctl_ctl->dramtmg2);
+	reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0);
+	writel(reg_val, &mctl_ctl->dramtmg3);
+	reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0);
+	writel(reg_val, &mctl_ctl->dramtmg4);
+	reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
+	writel(reg_val, &mctl_ctl->dramtmg5);
+	/* Set two rank timing and exit self-refresh timing */
+	reg_val = readl(&mctl_ctl->dramtmg8);
+	reg_val &= ~(0xff << 8);
+	reg_val &= ~(0xff << 0);
+	reg_val |= (0x33 << 8);
+	reg_val |= (0x8 << 0);
+	writel(reg_val, &mctl_ctl->dramtmg8);
+	/* Set phy interface time */
+	reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
+			| (wr_latency << 0);
+	/* PHY interface write latency and read latency configure */
+	writel(reg_val, &mctl_ctl->pitmg0);
+	/* Set phy time  PTR0-2 use default */
+	writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3);
+	writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4);
+	/* Set refresh timing */
+	reg_val = (trefi << 16) | (trfc << 0);
+	writel(reg_val, &mctl_ctl->rfshtmg);
+}
+
+static void mctl_set_pir(u32 val)
+{
+	struct sunxi_mctl_ctl_reg * const mctl_ctl =
+		(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+	writel(val, &mctl_ctl->pir);
+	mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1);
+}
+
+static void mctl_data_train_cfg(struct dram_para *para)
+{
+	struct sunxi_mctl_ctl_reg * const mctl_ctl =
+		(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+	if (para->rank == 2)
+		clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);
+	else
+		clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);
+}
+
+static int mctl_train_dram(struct dram_para *para)
+{
+	struct sunxi_mctl_ctl_reg * const mctl_ctl =
+		(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+	mctl_data_train_cfg(para);
+	mctl_set_pir(0x5f3);
+
+	return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0;
+}
+
+static void set_master_priority(void)
+{
+	writel(0x00a0000d, MCTL_MASTER_CFG0(0));
+	writel(0x00500064, MCTL_MASTER_CFG1(0));
+	writel(0x07000009, MCTL_MASTER_CFG0(1));
+	writel(0x00000600, MCTL_MASTER_CFG1(1));
+	writel(0x01000009, MCTL_MASTER_CFG0(3));
+	writel(0x00000064, MCTL_MASTER_CFG1(3));
+	writel(0x08000009, MCTL_MASTER_CFG0(4));
+	writel(0x00000640, MCTL_MASTER_CFG1(4));
+	writel(0x20000308, MCTL_MASTER_CFG0(8));
+	writel(0x00001000, MCTL_MASTER_CFG1(8));
+	writel(0x02800009, MCTL_MASTER_CFG0(9));
+	writel(0x00000100, MCTL_MASTER_CFG1(9));
+	writel(0x01800009, MCTL_MASTER_CFG0(5));
+	writel(0x00000100, MCTL_MASTER_CFG1(5));
+	writel(0x01800009, MCTL_MASTER_CFG0(7));
+	writel(0x00000100, MCTL_MASTER_CFG1(7));
+	writel(0x00640009, MCTL_MASTER_CFG0(6));
+	writel(0x00000032, MCTL_MASTER_CFG1(6));
+	writel(0x0100000d, MCTL_MASTER_CFG0(2));
+	writel(0x00500080, MCTL_MASTER_CFG1(2));
+}
+
+static int mctl_channel_init(struct dram_para *para)
+{
+	struct sunxi_mctl_ctl_reg * const mctl_ctl =
+		(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+	struct sunxi_mctl_com_reg * const mctl_com =
+		(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+	u32 low_data_lines_status;  /* Training status of datalines 0 - 7 */
+	u32 high_data_lines_status; /* Training status of datalines 8 - 15 */
+	u32 i, rval;
+
+	auto_set_timing_para(para);
+
+	/* Set dram master access priority */
+	writel(0x000101a0, &mctl_com->bwcr);
+	/* set cpu high priority */
+	writel(0x1, &mctl_com->mapr);
+	set_master_priority();
+	udelay(250);
+
+	/* Disable dram VTC */
+	clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0 | 0x1 << 30);
+	clrsetbits_le32(&mctl_ctl->pgcr1, 0x1 << 24, 0x1 << 26);
+
+	writel(0x94be6fa3, MCTL_PROTECT);
+	udelay(100);
+	clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 26);
+	writel(0x0, MCTL_PROTECT);
+	udelay(100);
+
+
+	/* Set ODT */
+	if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
+		rval = 0x0;
+	else
+		rval = 0x2;
+
+	for (i = 0 ; i < 11 ; i++) {
+		clrsetbits_le32(DATX0IOCR(i), (0x3 << 24) | (0x3 << 16),
+				rval << 24);
+		clrsetbits_le32(DATX1IOCR(i), (0x3 << 24) | (0x3 << 16),
+				rval << 24);
+		clrsetbits_le32(DATX2IOCR(i), (0x3 << 24) | (0x3 << 16),
+				rval << 24);
+		clrsetbits_le32(DATX3IOCR(i), (0x3 << 24) | (0x3 << 16),
+				rval << 24);
+	}
+
+	for (i = 0; i < 31; i++)
+		clrsetbits_le32(CAIOCR(i), 0x3 << 26 | 0x3 << 16, 0x2 << 26);
+
+	/* set PLL configuration */
+	if (CONFIG_DRAM_CLK >= 480)
+		setbits_le32(&mctl_ctl->pllgcr, 0x1 << 19);
+	else
+		setbits_le32(&mctl_ctl->pllgcr, 0x3 << 19);
+
+	/* Auto detect dram config, set 2 rank and 16bit bus-width */
+	para->cs1 = 0;
+	para->rank = 2;
+	para->bus_width = 16;
+	mctl_set_cr(para);
+
+	/* Open DQS gating */
+	clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
+	clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));
+
+	if (readl(&mctl_com->cr) & 0x1)
+		writel(0x00000303, &mctl_ctl->odtmap);
+	else
+		writel(0x00000201, &mctl_ctl->odtmap);
+
+	mctl_data_train_cfg(para);
+	/* ZQ calibration */
+	clrsetbits_le32(ZQnPR(0), 0x000000ff, CONFIG_DRAM_ZQ & 0xff);
+	clrsetbits_le32(ZQnPR(1), 0x000000ff, (CONFIG_DRAM_ZQ >> 8) & 0xff);
+	/* CA calibration */
+	mctl_set_pir(0x0201f3 | 0x1<<10);
+
+	/* DQS gate training */
+	if (mctl_train_dram(para) != 0) {
+		low_data_lines_status  = (readl(DXnGSR0(0)) >> 24) & 0x03;
+		high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03;
+
+		if (low_data_lines_status == 0x3)
+			return -EIO;
+
+		/* DRAM has only one rank */
+		para->rank = 1;
+		mctl_set_cr(para);
+
+		if (low_data_lines_status == high_data_lines_status)
+			goto done; /* 16 bit bus, 1 rank */
+
+		if (!(low_data_lines_status & high_data_lines_status)) {
+			/* Retry 16 bit bus-width with CS1 set */
+			para->cs1 = 1;
+			mctl_set_cr(para);
+			if (mctl_train_dram(para) == 0)
+				goto done;
+		}
+
+		/* Try 8 bit bus-width */
+		writel(0x0, DXnGCR0(1)); /* Disable high DQ */
+		para->cs1 = 0;
+		para->bus_width = 8;
+		mctl_set_cr(para);
+		if (mctl_train_dram(para) != 0)
+			return -EIO;
+	}
+done:
+	/* Check the dramc status */
+	mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
+
+	/* Close DQS gating */
+	setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);
+
+	/* set PGCR3,CKE polarity */
+	writel(0x00aa0060, &mctl_ctl->pgcr3);
+	/* Enable master access */
+	writel(0xffffffff, &mctl_com->maer);
+
+	return 0;
+}
+
+static void mctl_sys_init(struct dram_para *para)
+{
+	struct sunxi_ccm_reg * const ccm =
+			(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	struct sunxi_mctl_ctl_reg * const mctl_ctl =
+			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+	clrbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
+	clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+	clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+	clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+	clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
+	clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31);
+
+	clock_set_pll5(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL);
+
+	clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK,
+			CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) |
+			CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD);
+	mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
+
+	setbits_le32(&ccm->ahb_reset0_cfg, 1 << 14);
+	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+	setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+	setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
+
+	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+	setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+	setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
+
+	/* Set dram master access priority */
+	writel(0x0000e00f, &mctl_ctl->clken);	/* normal */
+
+	udelay(250);
+}
+
+unsigned long sunxi_dram_init(void)
+{
+	struct sunxi_mctl_com_reg * const mctl_com =
+			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+	struct sunxi_mctl_ctl_reg * const mctl_ctl =
+			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+	struct dram_para para = {
+		.cs1 = 0,
+		.bank = 1,
+		.rank = 1,
+		.rows = 15,
+		.bus_width = 16,
+		.page_size = 2048,
+	};
+
+	setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8);
+
+	writel(0, (SUNXI_PRCM_BASE + 0x1e8));
+	udelay(10);
+
+	mctl_sys_init(&para);
+
+	if (mctl_channel_init(&para) != 0)
+		return 0;
+
+	auto_detect_dram_size(&para);
+
+	/* Enable master software clk */
+	writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr);
+
+	/* Set DRAM ODT MAP */
+	if (para.rank == 2)
+		writel(0x00000303, &mctl_ctl->odtmap);
+	else
+		writel(0x00000201, &mctl_ctl->odtmap);
+
+	return para.page_size * (para.bus_width / 8) *
+		(1 << (para.bank + para.rank + para.rows));
+}

arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c

@@ -73,10 +73,10 @@ static void mctl_dq_delay(u32 read, u32 write)
 
 	for (i = 0; i < 4; i++) {
 		val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) |
-		      DATX_IOCR_READ_DELAY((read >> (i * 4)) & 0xf);
+		      DATX_IOCR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2);
 
 		for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++)
-			setbits_le32(&mctl_ctl->datx[i].iocr[j], val);
+			writel(val, &mctl_ctl->datx[i].iocr[j]);
 	}
 
 	clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
@@ -85,8 +85,8 @@ static void mctl_dq_delay(u32 read, u32 write)
 		val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) |
 		      DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf);
 
-		setbits_le32(&mctl_ctl->datx[i].iocr[DATX_IOCR_DQS], val);
-		setbits_le32(&mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN], val);
+		writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQS]);
+		writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN]);
 	}
 
 	setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
@@ -436,8 +436,8 @@ unsigned long sunxi_dram_init(void)
 			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 
 	struct dram_para para = {
-		.read_delays = 0x00007979,
-		.write_delays = 0x6aaa0000,
+		.read_delays = 0x00007979,	/* dram_tpr12 */
+		.write_delays = 0x6aaa0000,	/* dram_tpr11 */
 		.dual_rank = 0,
 		.bus_width = 32,
 		.row_bits = 15,

arch/arm/cpu/armv7/sunxi/pmic_bus.c

@@ -23,6 +23,7 @@
 #define AXP221_CTRL_ADDR		0x3e
 #define AXP221_INIT_DATA		0x3e
 
+/* AXP818 device and runtime addresses are same as AXP223 */
 #define AXP223_DEVICE_ADDR		0x3a3
 #define AXP223_RUNTIME_ADDR		0x2d
 
@@ -35,7 +36,7 @@ int pmic_bus_init(void)
 	if (!needs_init)
 		return 0;
 
-#ifdef CONFIG_AXP221_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	p2wi_init();
 	ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
@@ -61,7 +62,7 @@ int pmic_bus_read(u8 reg, u8 *data)
 	return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
 #elif defined CONFIG_AXP209_POWER
 	return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP221_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	return p2wi_read(reg, data);
 # else
@@ -76,7 +77,7 @@ int pmic_bus_write(u8 reg, u8 data)
 	return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1);
 #elif defined CONFIG_AXP209_POWER
 	return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP221_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	return p2wi_write(reg, data);
 # else

arch/arm/dts/Makefile

@@ -176,6 +176,8 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
 	sun8i-a33-ga10h-v1.1.dtb \
 	sun8i-a33-q8-tablet.dtb \
 	sun8i-a33-sinlinx-sina33.dtb
+dtb-$(CONFIG_MACH_SUN8I_A83T) += \
+	sun8i-a83t-allwinner-h8homlet-v2.dtb
 dtb-$(CONFIG_MACH_SUN8I_H3) += \
 	sun8i-h3-orangepi-pc.dtb \
 	sun8i-h3-orangepi-plus.dtb

arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts

@@ -0,0 +1,64 @@
+/*
+ * Copyright 2015 Vishnu Patekar
+ * Vishnu Patekar <vishnupatekar0510@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+
+/ {
+	model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
+	compatible = "allwinner,h8homlet-v2", "allwinner,sun8i-a83t";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_b>;
+	status = "okay";
+};

arch/arm/dts/sun8i-a83t.dtsi

@@ -0,0 +1,247 @@
+/*
+ * Copyright 2015 Vishnu Patekar
+ *
+ * Vishnu Patekar <vishnupatekar0510@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+
+ */
+
+#include "skeleton.dtsi"
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	interrupt-parent = <&gic>;
+
+	chosen {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <1>;
+		};
+
+		cpu@2 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <2>;
+		};
+
+		cpu@3 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <3>;
+		};
+		cpu@100 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0x100>;
+		};
+
+		cpu@101 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0x101>;
+		};
+		cpu@102 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0x102>;
+		};
+
+		cpu@103 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0x103>;
+		};
+	};
+
+	memory {
+		reg = <0x40000000 0x80000000>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <24000000>;
+		arm,cpu-registers-not-fw-configured;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		osc24M: osc24M_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "osc24M";
+		};
+
+		osc32k: osc32k_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			clock-output-names = "osc32k";
+		};
+	};
+
+	soc@01c00000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		gic: interrupt-controller@01c81000 {
+			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+			reg = <0x01c81000 0x1000>,
+			      <0x01c82000 0x1000>,
+			      <0x01c84000 0x2000>,
+			      <0x01c86000 0x2000>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+		pio: pinctrl@01c20800 {
+			compatible = "allwinner,sun8i-a83t-pinctrl";
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x01c20800 0x400>;
+			clocks = <&osc24M>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#gpio-cells = <3>;
+
+			i2c0_pins_a: i2c0@0 {
+				allwinner,pins = "PH0", "PH1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			i2c1_pins_a: i2c1@0 {
+				allwinner,pins = "PH2", "PH3";
+				allwinner,function = "i2c1";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			i2c2_pins_a: i2c2@0 {
+				allwinner,pins = "PH4", "PH5";
+				allwinner,function = "i2c2";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			mmc0_pins_a: mmc0@0 {
+				allwinner,pins = "PF0", "PF1", "PF2",
+						 "PF3", "PF4", "PF5";
+				allwinner,function = "mmc0";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			mmc1_pins_a: mmc1@0 {
+				allwinner,pins = "PG0", "PG1", "PG2",
+						 "PG3", "PG4", "PG5";
+				allwinner,function = "mmc1";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			mmc2_8bit_pins: mmc2_8bit {
+				allwinner,pins = "PC5", "PC6", "PC8",
+						 "PC9", "PC10", "PC11",
+						 "PC12", "PC13", "PC14",
+						 "PC15";
+				allwinner,function = "mmc2";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart0_pins_a: uart0@0 {
+				allwinner,pins = "PF2", "PF4";
+				allwinner,function = "uart0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart0_pins_b: uart0@1 {
+				allwinner,pins = "PB9", "PB10";
+				allwinner,function = "uart0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+		};
+
+		uart0: serial@01c28000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28000 0x400>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&osc24M>;
+			status = "disabled";
+		};
+	};
+};

arch/arm/include/asm/arch-sunxi/clock.h

@@ -15,7 +15,9 @@
 #define CLK_GATE_CLOSE			0x0
 
 /* clock control module regs definition */
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN8I_A83T)
+#include <asm/arch/clock_sun8i_a83t.h>
+#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
 #include <asm/arch/clock_sun6i.h>
 #elif defined(CONFIG_MACH_SUN9I)
 #include <asm/arch/clock_sun9i.h>

arch/arm/include/asm/arch-sunxi/clock_sun6i.h

@@ -220,11 +220,7 @@ struct sunxi_ccm_reg {
 #define CCM_PLL11_CTRL_UPD		(0x1 << 30)
 #define CCM_PLL11_CTRL_EN		(0x1 << 31)
 
-#if defined CONFIG_MACH_SUN8I_H3
 #define AHB1_ABP1_DIV_DEFAULT		0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
-#else
-#define AHB1_ABP1_DIV_DEFAULT		0x00002020 /* AHB1=AXI/4, APB1=AHB1/2 */
-#endif
 
 #define AXI_GATE_OFFSET_DRAM		0
 

arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h

@@ -0,0 +1,304 @@
+/*
+ * sun8i a83t clock register definitions
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * from sun6i.h
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_CLOCK_SUN8I_A83T_H
+#define _SUNXI_CLOCK_SUN8I_A83T_H
+
+struct sunxi_ccm_reg {
+	u32 pll1_c0_cfg;	/* 0x00 c1cpu# pll control */
+	u32 pll1_c1_cfg;	/* 0x04 c1cpu# pll control */
+	u32 pll2_cfg;		/* 0x08 pll2 audio control */
+	u32 reserved1;
+	u32 pll3_cfg;		/* 0x10 pll3 video0 control */
+	u32 reserved2;
+	u32 pll4_cfg;		/* 0x18 pll4 ve control */
+	u32 reserved3;
+	u32 pll5_cfg;		/* 0x20 pll5 ddr control */
+	u32 reserved4;
+	u32 pll6_cfg;		/* 0x28 pll6 peripheral control */
+	u32 reserved5[3];	/* 0x2c */
+	u32 pll7_cfg;		/* 0x38 pll7 gpu control */
+	u32 reserved6[2];	/* 0x3c */
+	u32 pll8_cfg;		/* 0x44 pll8 hsic control */
+	u32 pll9_cfg;		/* 0x48 pll9 de control */
+	u32 pll10_cfg;		/* 0x4c pll10 video1 control */
+	u32 cpu_axi_cfg;	/* 0x50 CPU/AXI divide ratio */
+	u32 ahb1_apb1_div;	/* 0x54 AHB1/APB1 divide ratio */
+	u32 apb2_div;		/* 0x58 APB2 divide ratio */
+	u32 ahb2_div;		/* 0x5c AHB2 divide ratio */
+	u32 ahb_gate0;		/* 0x60 ahb module clock gating 0 */
+	u32 ahb_gate1;		/* 0x64 ahb module clock gating 1 */
+	u32 apb1_gate;		/* 0x68 apb1 module clock gating 3 */
+	u32 apb2_gate;		/* 0x6c apb2 module clock gating 4 */
+	u32 reserved7[2];	/* 0x70 */
+	u32 cci400_cfg;		/* 0x78 cci400 clock configuration A83T only */
+	u32 reserved8;		/* 0x7c */
+	u32 nand0_clk_cfg;	/* 0x80 nand clock control */
+	u32 reserved9;		/* 0x84 */
+	u32 sd0_clk_cfg;	/* 0x88 sd0 clock control */
+	u32 sd1_clk_cfg;	/* 0x8c sd1 clock control */
+	u32 sd2_clk_cfg;	/* 0x90 sd2 clock control */
+	u32 sd3_clk_cfg;	/* 0x94 sd3 clock control */
+	u32 reserved10;		/* 0x98 */
+	u32 ss_clk_cfg;		/* 0x9c security system clock control */
+	u32 spi0_clk_cfg;	/* 0xa0 spi0 clock control */
+	u32 spi1_clk_cfg;	/* 0xa4 spi1 clock control */
+	u32 reserved11[2];	/* 0xa8 */
+	u32 i2s0_clk_cfg;	/* 0xb0 I2S0 clock control */
+	u32 i2s1_clk_cfg;	/* 0xb4 I2S1 clock control */
+	u32 i2s2_clk_cfg;	/* 0xb8 I2S2 clock control */
+	u32 tdm_clk_cfg;	/* 0xbc TDM clock control */
+	u32 spdif_clk_cfg;      /* 0xc0 SPDIF clock control */
+	u32 reserved12[2];	/* 0xc4 */
+	u32 usb_clk_cfg;	/* 0xcc USB clock control */
+	u32 reserved13[9];	/* 0xd0 */
+	u32 dram_clk_cfg;	/* 0xf4 DRAM configuration clock control */
+	u32 dram_pll_cfg;	/* 0xf8 PLL_DDR cfg register */
+	u32 mbus_reset;		/* 0xfc MBUS reset control */
+	u32 dram_clk_gate;	/* 0x100 DRAM module gating */
+	u32 reserved14[5];	/* 0x104 BE0 */
+	u32 lcd0_clk_cfg;	/* 0x118 LCD0 module clock */
+	u32 lcd1_clk_cfg;	/* 0x11c LCD1 module clock */
+	u32 reserved15[4];	/* 0x120 */
+	u32 mipi_csi_clk_cfg;	/* 0x130 MIPI CSI module clock */
+	u32 csi_clk_cfg;	/* 0x134 CSI module clock */
+	u32 reserved16;		/* 0x138 */
+	u32 ve_clk_cfg;		/* 0x13c VE module clock */
+	u32 reserved17;		/* 0x140 */
+	u32 avs_clk_cfg;	/* 0x144 AVS module clock */
+	u32 reserved18[2];	/* 0x148 */
+	u32 hdmi_clk_cfg;	/* 0x150 HDMI module clock */
+	u32 hdmi_slow_clk_cfg;	/* 0x154 HDMI slow module clock */
+	u32 reserved19;		/* 0x158 */
+	u32 mbus_clk_cfg;	/* 0x15c MBUS module clock */
+	u32 reserved20[2];	/* 0x160 */
+	u32 mipi_dsi_clk_cfg;	/* 0x168 MIPI DSI clock control */
+	u32 reserved21[13];	/* 0x16c */
+	u32 gpu_core_clk_cfg;	/* 0x1a0 GPU core clock config */
+	u32 gpu_mem_clk_cfg;	/* 0x1a4 GPU memory clock config */
+	u32 gpu_hyd_clk_cfg;	/* 0x1a8 GPU HYD clock config */
+	u32 reserved22[21];	/* 0x1ac */
+	u32 pll_stable0;	/* 0x200 PLL stable time 0 */
+	u32 pll_stable1;	/* 0x204 PLL stable time 1 */
+	u32 reserved23;		/* 0x208 */
+	u32 pll_stable_status;	/* 0x20c PLL stable status register */
+	u32 reserved24[4];	/* 0x210 */
+	u32 pll1_c0_bias_cfg;	/* 0x220 PLL1 c0cpu# Bias config */
+	u32 pll2_bias_cfg;	/* 0x224 PLL2 audio Bias config */
+	u32 pll3_bias_cfg;	/* 0x228 PLL3 video Bias config */
+	u32 pll4_bias_cfg;	/* 0x22c PLL4 ve Bias config */
+	u32 pll5_bias_cfg;	/* 0x230 PLL5 ddr Bias config */
+	u32 pll6_bias_cfg;	/* 0x234 PLL6 periph Bias config */
+	u32 pll1_c1_bias_cfg;	/* 0x238 PLL1 c1cpu# Bias config */
+	u32 pll8_bias_cfg;	/* 0x23c PLL7 Bias config */
+	u32 reserved25;		/* 0x240 */
+	u32 pll9_bias_cfg;	/* 0x244 PLL9 hsic Bias config */
+	u32 de_bias_cfg;	/* 0x248 display engine Bias config */
+	u32 video1_bias_cfg;	/* 0x24c pll video1 bias register */
+	u32 c0_tuning_cfg;	/* 0x250 pll c0cpu# tuning register */
+	u32 c1_tuning_cfg;	/* 0x254 pll c1cpu# tuning register */
+	u32 reserved26[11];	/* 0x258 */
+	u32 pll2_pattern_cfg0;	/* 0x284 PLL2 Pattern register 0 */
+	u32 pll3_pattern_cfg0;	/* 0x288 PLL3 Pattern register 0 */
+	u32 reserved27;		/* 0x28c */
+	u32 pll5_pattern_cfg0;	/* 0x290 PLL5 Pattern register 0*/
+	u32 reserved28[4];	/* 0x294 */
+	u32 pll2_pattern_cfg1;	/* 0x2a4 PLL2 Pattern register 1 */
+	u32 pll3_pattern_cfg1;	/* 0x2a8 PLL3 Pattern register 1 */
+	u32 reserved29;		/* 0x2ac */
+	u32 pll5_pattern_cfg1;	/* 0x2b0 PLL5 Pattern register 1 */
+	u32 reserved30[3];	/* 0x2b4 */
+	u32 ahb_reset0_cfg;	/* 0x2c0 AHB1 Reset 0 config */
+	u32 ahb_reset1_cfg;	/* 0x2c4 AHB1 Reset 1 config */
+	u32 ahb_reset2_cfg;	/* 0x2c8 AHB1 Reset 2 config */
+	u32 reserved31;
+	u32 ahb_reset3_cfg;	/* 0x2d0 AHB1 Reset 3 config */
+	u32 reserved32;		/* 0x2d4 */
+	u32 apb2_reset_cfg;	/* 0x2d8 BUS Reset 4 config */
+};
+
+/* apb2 bit field */
+#define APB2_CLK_SRC_LOSC		(0x0 << 24)
+#define APB2_CLK_SRC_OSC24M		(0x1 << 24)
+#define APB2_CLK_SRC_PLL6		(0x2 << 24)
+#define APB2_CLK_SRC_MASK		(0x3 << 24)
+#define APB2_CLK_RATE_N_1		(0x0 << 16)
+#define APB2_CLK_RATE_N_2		(0x1 << 16)
+#define APB2_CLK_RATE_N_4		(0x2 << 16)
+#define APB2_CLK_RATE_N_8		(0x3 << 16)
+#define APB2_CLK_RATE_N_MASK		(3 << 16)
+#define APB2_CLK_RATE_M(m)		(((m)-1) << 0)
+#define APB2_CLK_RATE_M_MASK            (0x1f << 0)
+
+/* apb2 gate field */
+#define APB2_GATE_UART_SHIFT	(16)
+#define APB2_GATE_UART_MASK		(0xff << APB2_GATE_UART_SHIFT)
+#define APB2_GATE_TWI_SHIFT	(0)
+#define APB2_GATE_TWI_MASK		(0xf << APB2_GATE_TWI_SHIFT)
+
+/* cpu_axi_cfg bits */
+#define AXI0_DIV_SHIFT			0
+#define AXI1_DIV_SHIFT			16
+#define C0_CPUX_CLK_SRC_SHIFT		12
+#define C1_CPUX_CLK_SRC_SHIFT		28
+
+#define AXI_DIV_1			0
+#define AXI_DIV_2			1
+#define AXI_DIV_3			2
+#define AXI_DIV_4			3
+#define CPU_CLK_SRC_OSC24M		0
+#define CPU_CLK_SRC_PLL1		1
+
+#define CCM_PLL1_CTRL_N(n)		((((n) - 1) & 0xff) << 8)
+#define CCM_PLL1_CTRL_P(n)		(((n) & 0x1) << 16)
+#define CCM_PLL1_CTRL_EN		(0x1 << 31)
+#define CMM_PLL1_CLOCK_TIME_2		(0x2 << 24)
+
+#define PLL8_CFG_DEFAULT		0x42800
+#define CCM_CCI400_CLK_SEL_HSIC		(0x2<<24)
+
+#define CCM_PLL5_DIV1_SHIFT		16
+#define CCM_PLL5_DIV2_SHIFT		18
+#define CCM_PLL5_CTRL_N(n)		(((n) - 1) << 8)
+#define CCM_PLL5_CTRL_UPD		(0x1 << 30)
+#define CCM_PLL5_CTRL_EN		(0x1 << 31)
+
+#define PLL6_CFG_DEFAULT		0x80001900 /* 600 MHz */
+#define CCM_PLL6_CTRL_N_SHIFT		8
+#define CCM_PLL6_CTRL_N_MASK		(0xff << CCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_DIV1_SHIFT	16
+#define CCM_PLL6_CTRL_DIV1_MASK		(0x1 << CCM_PLL6_CTRL_DIV1_SHIFT)
+#define CCM_PLL6_CTRL_DIV2_SHIFT	18
+#define CCM_PLL6_CTRL_DIV2_MASK		(0x1 << CCM_PLL6_CTRL_DIV2_SHIFT)
+
+#define AHB1_ABP1_DIV_DEFAULT		0x00002190
+#define AHB1_CLK_SRC_MASK		(0x3<<12)
+#define AHB1_CLK_SRC_INTOSC		(0x0<<12)
+#define AHB1_CLK_SRC_OSC24M		(0x1<<12)
+#define AHB1_CLK_SRC_PLL6		(0x2<<12)
+
+#define AXI_GATE_OFFSET_DRAM		0
+
+/* ahb_gate0 offsets */
+#define AHB_GATE_OFFSET_USB_OHCI1	30
+#define AHB_GATE_OFFSET_USB_OHCI0	29
+#define AHB_GATE_OFFSET_USB_EHCI1	27
+#define AHB_GATE_OFFSET_USB_EHCI0	26
+#define AHB_GATE_OFFSET_USB0		24
+#define AHB_GATE_OFFSET_SPI1		21
+#define AHB_GATE_OFFSET_SPI0		20
+#define AHB_GATE_OFFSET_HSTIMER		19
+#define AHB_GATE_OFFSET_EMAC		17
+#define AHB_GATE_OFFSET_MCTL		14
+#define AHB_GATE_OFFSET_GMAC		17
+#define AHB_GATE_OFFSET_NAND0		13
+#define AHB_GATE_OFFSET_MMC0		8
+#define AHB_GATE_OFFSET_MMC(n)		(AHB_GATE_OFFSET_MMC0 + (n))
+#define AHB_GATE_OFFSET_DMA		6
+#define AHB_GATE_OFFSET_SS		5
+
+/* ahb_gate1 offsets */
+#define AHB_GATE_OFFSET_DRC0		25
+#define AHB_GATE_OFFSET_DE_FE0		14
+#define AHB_GATE_OFFSET_DE_BE0		12
+#define AHB_GATE_OFFSET_HDMI		11
+#define AHB_GATE_OFFSET_LCD1		5
+#define AHB_GATE_OFFSET_LCD0		4
+
+#define CCM_MMC_CTRL_M(x)		((x) - 1)
+#define CCM_MMC_CTRL_OCLK_DLY(x)	((x) << 8)
+#define CCM_MMC_CTRL_N(x)		((x) << 16)
+#define CCM_MMC_CTRL_SCLK_DLY(x)	((x) << 20)
+#define CCM_MMC_CTRL_OSCM24		(0x0 << 24)
+#define CCM_MMC_CTRL_PLL6		(0x1 << 24)
+#define CCM_MMC_CTRL_ENABLE		(0x1 << 31)
+
+#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
+#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
+#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+/* There is no global phy clk gate on sun6i, define as 0 */
+#define CCM_USB_CTRL_PHYGATE 0
+#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8)
+#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
+#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
+
+#define CCM_GMAC_CTRL_TX_CLK_SRC_MII	0x0
+#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
+#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
+#define CCM_GMAC_CTRL_GPIT_MII		(0x0 << 2)
+#define CCM_GMAC_CTRL_GPIT_RGMII	(0x1 << 2)
+#define CCM_GMAC_CTRL_RX_CLK_DELAY(x)	((x) << 5)
+#define CCM_GMAC_CTRL_TX_CLK_DELAY(x)	((x) << 10)
+
+#define MDFS_CLK_DEFAULT		0x81000002 /* PLL6 / 3 */
+
+#define CCM_DRAMCLK_CFG_DIV(x)		((x - 1) << 0)
+#define CCM_DRAMCLK_CFG_DIV_MASK	(0xf << 0)
+#define CCM_DRAMCLK_CFG_DIV0(x)		((x - 1) << 8)
+#define CCM_DRAMCLK_CFG_DIV0_MASK	(0xf << 8)
+#define CCM_DRAMCLK_CFG_UPD		(0x1 << 16)
+#define CCM_DRAMCLK_CFG_RST		(0x1 << 31)
+
+#define CCM_DRAMPLL_CFG_SRC_PLL5	(0x0 << 16) /* Select PLL5 (DDR0) */
+#define CCM_DRAMPLL_CFG_SRC_PLL11	(0x1 << 16) /* Select PLL11 (DDR1) */
+#define CCM_DRAMPLL_CFG_SRC_MASK	(0x1 << 16)
+
+#define CCM_MBUS_RESET_RESET		(0x1 << 31)
+
+#define CCM_DRAM_GATE_OFFSET_DE_FE0	24
+#define CCM_DRAM_GATE_OFFSET_DE_FE1	25
+#define CCM_DRAM_GATE_OFFSET_DE_BE0	26
+#define CCM_DRAM_GATE_OFFSET_DE_BE1	27
+
+
+#define MBUS_CLK_DEFAULT		0x81000002 /* PLL6 / 2 */
+
+#define MBUS_CLK_GATE			(0x1 << 31)
+
+/* ahb_reset0 offsets */
+#define AHB_RESET_OFFSET_GMAC		17
+#define AHB_RESET_OFFSET_MCTL		14
+#define AHB_RESET_OFFSET_MMC3		11
+#define AHB_RESET_OFFSET_MMC2		10
+#define AHB_RESET_OFFSET_MMC1		9
+#define AHB_RESET_OFFSET_MMC0		8
+#define AHB_RESET_OFFSET_MMC(n)		(AHB_RESET_OFFSET_MMC0 + (n))
+#define AHB_RESET_OFFSET_SS		5
+
+/* ahb_reset1 offsets */
+#define AHB_RESET_OFFSET_SAT		26
+#define AHB_RESET_OFFSET_DRC0		25
+#define AHB_RESET_OFFSET_DE_FE0		14
+#define AHB_RESET_OFFSET_DE_BE0		12
+#define AHB_RESET_OFFSET_HDMI		11
+#define AHB_RESET_OFFSET_LCD1		5
+#define AHB_RESET_OFFSET_LCD0		4
+
+/* ahb_reset2 offsets */
+#define AHB_RESET_OFFSET_LVDS		0
+
+/* apb2 reset */
+#define APB2_RESET_UART_SHIFT		(16)
+#define APB2_RESET_UART_MASK		(0xff << APB2_RESET_UART_SHIFT)
+#define APB2_RESET_TWI_SHIFT		(0)
+#define APB2_RESET_TWI_MASK		(0xf << APB2_RESET_TWI_SHIFT)
+
+
+#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int hz);
+void clock_set_pll5(unsigned int clk);
+unsigned int clock_get_pll6(void);
+#endif
+
+#endif /* _SUNXI_CLOCK_SUN8I_A83T_H */

arch/arm/include/asm/arch-sunxi/dram.h

@@ -22,6 +22,8 @@
 #include <asm/arch/dram_sun8i_a23.h>
 #elif defined(CONFIG_MACH_SUN8I_A33)
 #include <asm/arch/dram_sun8i_a33.h>
+#elif defined(CONFIG_MACH_SUN8I_A83T)
+#include <asm/arch/dram_sun8i_a83t.h>
 #elif defined(CONFIG_MACH_SUN8I_H3)
 #include <asm/arch/dram_sun8i_h3.h>
 #else

arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h

@@ -0,0 +1,201 @@
+/*
+ * Sun8i platform dram controller register and constant defines
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ *                         Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015      Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_DRAM_SUN8I_A83T_H
+#define _SUNXI_DRAM_SUN8I_A83T_H
+
+struct sunxi_mctl_com_reg {
+	u32 cr;			/* 0x00 */
+	u32 ccr;		/* 0x04 controller configuration register */
+	u32 dbgcr;		/* 0x08 */
+	u8 res0[0x4];		/* 0x0c */
+	u32 mcr0_0;		/* 0x10 */
+	u32 mcr1_0;		/* 0x14 */
+	u32 mcr0_1;		/* 0x18 */
+	u32 mcr1_1;		/* 0x1c */
+	u32 mcr0_2;		/* 0x20 */
+	u32 mcr1_2;		/* 0x24 */
+	u32 mcr0_3;		/* 0x28 */
+	u32 mcr1_3;		/* 0x2c */
+	u32 mcr0_4;		/* 0x30 */
+	u32 mcr1_4;		/* 0x34 */
+	u32 mcr0_5;		/* 0x38 */
+	u32 mcr1_5;		/* 0x3c */
+	u32 mcr0_6;		/* 0x40 */
+	u32 mcr1_6;		/* 0x44 */
+	u32 mcr0_7;		/* 0x48 */
+	u32 mcr1_7;		/* 0x4c */
+	u32 mcr0_8;		/* 0x50 */
+	u32 mcr1_8;		/* 0x54 */
+	u32 mcr0_9;		/* 0x58 */
+	u32 mcr1_9;		/* 0x5c */
+	u32 mcr0_10;		/* 0x60 */
+	u32 mcr1_10;		/* 0x64 */
+	u32 mcr0_11;		/* 0x68 */
+	u32 mcr1_11;		/* 0x6c */
+	u32 mcr0_12;		/* 0x70 */
+	u32 mcr1_12;		/* 0x74 */
+	u32 mcr0_13;		/* 0x78 */
+	u32 mcr1_13;		/* 0x7c */
+	u32 mcr0_14;		/* 0x80 */
+	u32 mcr1_14;		/* 0x84 */
+	u32 mcr0_15;		/* 0x88 */
+	u32 mcr1_15;		/* 0x8c */
+	u32 bwcr;		/* 0x90 */
+	u32 maer;		/* 0x94 */
+	u32 mapr;		/* 0x98 */
+	u32 mcgcr;		/* 0x9c */
+	u32 bwctr;		/* 0xa0 */
+	u8 res2[0x8];		/* 0xa4 */
+	u32 swoffr;		/* 0xac */
+	u8 res3[0x10];		/* 0xb0 */
+	u32 swonr;		/* 0xc0 */
+	u8 res4[0x3c];		/* 0xc4 */
+	u32 mdfscr;		/* 0x100 */
+	u32 mdfsmer;		/* 0x104 */
+};
+
+struct sunxi_mctl_ctl_reg {
+	u32 pir;		/* 0x00 */
+	u32 pwrctl;		/* 0x04 */
+	u32 mrctrl0;		/* 0x08 */
+	u32 clken;		/* 0x0c */
+	u32 pgsr0;		/* 0x10 */
+	u32 pgsr1;		/* 0x14 */
+	u32 statr;		/* 0x18 */
+	u8 res1[0x14];		/* 0x1c */
+	u32 mr0;		/* 0x30 */
+	u32 mr1;		/* 0x34 */
+	u32 mr2;		/* 0x38 */
+	u32 mr3;		/* 0x3c */
+	u32 pllgcr;		/* 0x40 */
+	u32 ptr0;		/* 0x44 */
+	u32 ptr1;		/* 0x48 */
+	u32 ptr2;		/* 0x4c */
+	u32 ptr3;		/* 0x50 */
+	u32 ptr4;		/* 0x54 */
+	u32 dramtmg0;		/* 0x58 dram timing parameters register 0 */
+	u32 dramtmg1;		/* 0x5c dram timing parameters register 1 */
+	u32 dramtmg2;		/* 0x60 dram timing parameters register 2 */
+	u32 dramtmg3;		/* 0x64 dram timing parameters register 3 */
+	u32 dramtmg4;		/* 0x68 dram timing parameters register 4 */
+	u32 dramtmg5;		/* 0x6c dram timing parameters register 5 */
+	u32 dramtmg6;		/* 0x70 dram timing parameters register 6 */
+	u32 dramtmg7;		/* 0x74 dram timing parameters register 7 */
+	u32 dramtmg8;		/* 0x78 dram timing parameters register 8 */
+	u32 odtcfg;		/* 0x7c */
+	u32 pitmg0;		/* 0x80 */
+	u32 pitmg1;		/* 0x84 */
+	u8 res2[0x4];		/* 0x88 */
+	u32 rfshctl0;		/* 0x8c */
+	u32 rfshtmg;		/* 0x90 */
+	u32 rfshctl1;		/* 0x94 */
+	u32 pwrtmg;		/* 0x98 */
+	u8  res3[0x20];		/* 0x9c */
+	u32 dqsgmr;		/* 0xbc */
+	u32 dtcr;		/* 0xc0 */
+	u32 dtar0;		/* 0xc4 */
+	u32 dtar1;		/* 0xc8 */
+	u32 dtar2;		/* 0xcc */
+	u32 dtar3;		/* 0xd0 */
+	u32 dtdr0;		/* 0xd4 */
+	u32 dtdr1;		/* 0xd8 */
+	u32 dtmr0;		/* 0xdc */
+	u32 dtmr1;		/* 0xe0 */
+	u32 dtbmr;		/* 0xe4 */
+	u32 catr0;		/* 0xe8 */
+	u32 catr1;		/* 0xec */
+	u32 dtedr0;		/* 0xf0 */
+	u32 dtedr1;		/* 0xf4 */
+	u8 res4[0x8];		/* 0xf8 */
+	u32 pgcr0;		/* 0x100 */
+	u32 pgcr1;		/* 0x104 */
+	u32 pgcr2;		/* 0x108 */
+	u32 pgcr3;		/* 0x10c */
+	u32 iovcr0;		/* 0x110 */
+	u32 iovcr1;		/* 0x114 */
+	u32 dqsdr;		/* 0x118 */
+	u32 dxccr;		/* 0x11c */
+	u32 odtmap;		/* 0x120 */
+	u32 zqctl0;		/* 0x124 */
+	u32 zqctl1;		/* 0x128 */
+	u8 res6[0x14];		/* 0x12c */
+	u32 zqncr;		/* 0x140 zq control register 0 */
+	u32 zqnpr;		/* 0x144 zq control register 1 */
+	u32 zqndr;		/* 0x148 zq control register 2 */
+	u32 zqnsr;		/* 0x14c zq status register 0 */
+	u32 res7;		/* 0x150 zq status register 1 */
+	u8 res8[0x6c];		/* 0x154 */
+	u32 sched;		/* 0x1c0 */
+	u32 perfhpr0;		/* 0x1c4 */
+	u32 perfhpr1;		/* 0x1c8 */
+	u32 perflpr0;		/* 0x1cc */
+	u32 perflpr1;		/* 0x1d0 */
+	u32 perfwr0;		/* 0x1d4 */
+	u32 perfwr1;		/* 0x1d8 */
+};
+
+
+#define ZQnPR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x)
+#define ZQnDR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x)
+#define ZQnSR(x)	(SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x)
+
+#define DXnGTR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x)
+#define DXnGCR0(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x)
+#define DXnGSR0(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x)
+#define DXnGSR1(x)	(SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x)
+#define DXnGSR2(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x)
+
+#define CAIOCR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000210 + 0x4 * (x))
+#define DXnMDLR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000300 + 0x80 * x)
+#define DXMDLR0		(SUNXI_DRAM_CTL0_BASE + 0x00000300)
+#define DXnLCDLR0(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000304 + 0x80 * x)
+#define DXnLCDLR1(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000308 + 0x80 * x)
+#define DXnLCDLR2(x)	(SUNXI_DRAM_CTL0_BASE + 0x0000030c + 0x80 * x)
+#define DATX0IOCR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000310 + 0x4 * x)
+#define DATX1IOCR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000390 + 0x4 * x)
+#define DATX2IOCR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000410 + 0x4 * x)
+#define DATX3IOCR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000490 + 0x4 * x)
+#define MX_UPD0		(SUNXI_DRAM_CTL0_BASE + 0x00000880)
+#define MX_UPD2		(SUNXI_DRAM_CTL0_BASE + 0x00000888)
+
+#define MCTL_PROTECT		(SUNXI_DRAM_COM_BASE + 0x800)
+#define MCTL_MASTER_CFG0(x)	(SUNXI_DRAM_COM_BASE + 0x10 + 0x8 * x)
+#define MCTL_MASTER_CFG1(x)	(SUNXI_DRAM_COM_BASE + 0x14 + 0x8 * x)
+
+/*
+ * DRAM common (sunxi_mctl_com_reg) register constants.
+ */
+#define MCTL_CR_RANK_MASK		(3 << 0)
+#define MCTL_CR_RANK(x)			(((x) - 1) << 0)
+#define MCTL_CR_BANK_MASK		(3 << 2)
+#define MCTL_CR_BANK(x)			((x) << 2)
+#define MCTL_CR_ROW_MASK		(0xf << 4)
+#define MCTL_CR_ROW(x)			(((x) - 1) << 4)
+#define MCTL_CR_PAGE_SIZE_MASK		(0xf << 8)
+#define MCTL_CR_PAGE_SIZE(x)		((fls(x) - 4) << 8)
+#define MCTL_CR_BUSW_MASK		(7 << 12)
+#define MCTL_CR_BUSW8			(0 << 12)
+#define MCTL_CR_BUSW16			(1 << 12)
+#define MCTL_CR_SEQUENCE		(1 << 15)
+#define MCTL_CR_DDR3			(3 << 16)
+#define MCTL_CR_CHANNEL_MASK		(1 << 19)
+#define MCTL_CR_CHANNEL(x)		(((x) - 1) << 19)
+#define MCTL_CR_UNKNOWN			(0x4 << 20)
+#define MCTL_CR_CS1_CONTROL(x)		((x) << 24)
+
+/* DRAM control (sunxi_mctl_ctl_reg) register constants */
+#define MCTL_MR0			0x1c70 /* CL=11, WR=12 */
+#define MCTL_MR1			0x40
+#define MCTL_MR2			0x18 /* CWL=8 */
+#define MCTL_MR3			0x0
+
+#endif /* _SUNXI_DRAM_SUN8I_A83T_H */

arch/arm/include/asm/arch-sunxi/gpio.h

@@ -158,6 +158,7 @@ enum sunxi_gpio_number {
 #define SUN5I_GPB_UART0		2
 #define SUN8I_GPB_UART2		2
 #define SUN8I_A33_GPB_UART0	3
+#define SUN8I_A83T_GPB_UART0	2
 
 #define SUNXI_GPC_NAND		2
 #define SUNXI_GPC_SDC2		3

board/sunxi/Kconfig

@@ -74,6 +74,12 @@ config MACH_SUN8I_H3
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 
+config MACH_SUN8I_A83T
+	bool "sun8i (Allwinner A83T)"
+	select CPU_V7
+	select SUNXI_GEN_SUN6I
+	select SUPPORT_SPL
+
 config MACH_SUN9I
 	bool "sun9i (Allwinner A80)"
 	select CPU_V7
@@ -84,7 +90,7 @@ endchoice
 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
 config MACH_SUN8I
 	bool
-	default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3
+	default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
 
 
 config DRAM_CLK
@@ -373,6 +379,7 @@ config AXP_GPIO
 
 config VIDEO
 	boolean "Enable graphical uboot console on HDMI, LCD or VGA"
+	depends on !MACH_SUN8I_A83T
 	default y
 	---help---
 	Say Y here to add support for using a cfb console on the HDMI, LCD

board/sunxi/MAINTAINERS

@@ -101,6 +101,11 @@ M:	Priit Laes <plaes@plaes.org>
 S:	Maintained
 F:	configs/sunxi_Gemei_G9_defconfig
 
+H8HOMLET PROTO A83T BOARD
+M:	VishnuPatekar <vishnupatekar0510@gmail.com>
+S:	Maintained
+F:	configs/h8_homlet_v2_defconfig
+
 HUMMINGBIRD-A31 BOARD
 M:	Chen-Yu Tsai <wens@csie.org>
 S:	Maintained

board/sunxi/board.c

@@ -430,26 +430,29 @@ void sunxi_board_init(void)
 	int power_failed = 0;
 	unsigned long ramsize;
 
-#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER
+#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
+	defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
 	power_failed = axp_init();
 
-#ifdef CONFIG_AXP221_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
 #endif
 	power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
 	power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
-#ifndef CONFIG_AXP209_POWER
+#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
 	power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
 #endif
-#ifdef CONFIG_AXP221_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
 #endif
 
 #ifdef CONFIG_AXP221_POWER
 	power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
 #endif
+#ifndef CONFIG_AXP818_POWER
 	power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
-#ifndef CONFIG_AXP152_POWER
+#endif
+#if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP818_POWER)
 	power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
 #endif
 #ifdef CONFIG_AXP209_POWER

configs/A10-OLinuXino-Lime_defconfig

@@ -13,5 +13,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/A10s-OLinuXino-M_defconfig

@@ -15,5 +15,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_AXP152_POWER=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/A13-OLinuXinoM_defconfig

@@ -19,5 +19,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_SUNXI_NO_PMIC=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/A13-OLinuXino_defconfig

@@ -20,6 +20,5 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y

configs/A20-OLinuXino-Lime2_defconfig

@@ -14,5 +14,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/A20-OLinuXino-Lime_defconfig

@@ -12,5 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/A20-OLinuXino_MICRO_defconfig

@@ -15,5 +15,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/A20-Olimex-SOM-EVB_defconfig

@@ -14,5 +14,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Ainol_AW1_defconfig

@@ -18,5 +18,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y

configs/Ampe_A76_defconfig

@@ -20,5 +20,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y

configs/Auxtek-T003_defconfig

@@ -13,5 +13,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_AXP152_POWER=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Auxtek-T004_defconfig

@@ -11,5 +11,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_AXP152_POWER=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Bananapi_defconfig

@@ -14,5 +14,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 CONFIG_CMD_GPIO=y
 CONFIG_NETCONSOLE=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Bananapro_defconfig

@@ -16,5 +16,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 CONFIG_CMD_GPIO=y
 CONFIG_NETCONSOLE=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/CHIP_defconfig

@@ -12,5 +12,4 @@ CONFIG_CMD_GPIO=y
 CONFIG_AXP_DCDC2_VOLT=1300
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_GADGET=y

configs/CSQ_CS908_defconfig

@@ -15,6 +15,5 @@ CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y

configs/Chuwi_V7_CW0825_defconfig

@@ -18,7 +18,6 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_VIDEO_LCD_SPI_CS="PA0"
 CONFIG_VIDEO_LCD_SPI_SCLK="PA1"

configs/Colombus_defconfig

@@ -24,5 +24,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Cubieboard2_defconfig

@@ -12,5 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Cubieboard_defconfig

@@ -11,5 +11,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Cubietruck_defconfig

@@ -17,6 +17,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12)"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y

configs/Hummingbird_A31_defconfig

@@ -16,5 +16,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Hyundai_A7HD_defconfig

@@ -19,5 +19,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y

configs/Lamobo_R1_defconfig

@@ -13,5 +13,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,SATAPWR=SUN
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Linksprite_pcDuino3_Nano_defconfig

@@ -14,5 +14,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2)"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Linksprite_pcDuino3_defconfig

@@ -12,5 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2)"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Linksprite_pcDuino_defconfig

@@ -11,5 +11,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/MK808C_defconfig

@@ -9,5 +9,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/MSI_Primo73_defconfig

@@ -14,4 +14,3 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y

configs/MSI_Primo81_defconfig

@@ -18,7 +18,6 @@ CONFIG_SPL=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_AXP_DLDO1_VOLT=3300
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27
 CONFIG_VIDEO_LCD_SSD2828_RESET="PA26"

configs/Marsboard_A10_defconfig

@@ -9,5 +9,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Mele_A1000G_quad_defconfig

@@ -17,6 +17,5 @@ CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_DLDO4_VOLT=3300
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y

configs/Mele_A1000_defconfig

@@ -11,5 +11,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Mele_I7_defconfig

@@ -17,5 +17,4 @@ CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_DLDO4_VOLT=3300
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Mele_M3_defconfig

@@ -15,5 +15,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Mele_M5_defconfig

@@ -14,5 +14,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,STATUSLED=234"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Mele_M9_defconfig

@@ -17,5 +17,4 @@ CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_DLDO4_VOLT=3300
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Merrii_A80_Optimus_defconfig

@@ -12,4 +12,3 @@ CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y

configs/Mini-X_defconfig

@@ -10,6 +10,5 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y

configs/Orangepi_defconfig

@@ -16,5 +16,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Orangepi_mini_defconfig

@@ -18,5 +18,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Sinlinx_SinA33_defconfig

@@ -10,4 +10,3 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y

configs/Sinovoip_BPI_M2_defconfig

@@ -16,5 +16,4 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_ALDO2_VOLT=1800
 CONFIG_AXP_DLDO1_VOLT=3000
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/UTOO_P66_defconfig

@@ -25,5 +25,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y

configs/Wexler_TAB7200_defconfig

@@ -17,6 +17,5 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y

configs/Wits_Pro_A20_DKT_defconfig

@@ -17,5 +17,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Wobo_i5_defconfig

@@ -11,5 +11,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/Yones_Toptech_BD1078_defconfig

@@ -23,5 +23,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y

configs/ba10_tv_box_defconfig

@@ -14,6 +14,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y

configs/ga10h_v1_1_defconfig

@@ -23,6 +23,5 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_AXP_DLDO1_VOLT=3300
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y

configs/gt90h_v4_defconfig

@@ -22,5 +22,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_AXP_DLDO1_VOLT=3300
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y

configs/h8_homlet_v2_defconfig

@@ -0,0 +1,24 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A83T=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=15355
+CONFIG_DRAM_ODT_EN=y
+#CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+#CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_AXP_GPIO=y
+#CONFIG_USB_MUSB_HOST=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_AXP_DCDC1_VOLT=3000
+CONFIG_AXP_DCDC2_VOLT=900
+CONFIG_AXP_DCDC3_VOLT=900
+CONFIG_AXP_DCDC4_VOLT=0
+CONFIG_AXP_DCDC5_VOLT=1500
+CONFIG_AXP_ALDO2_VOLT=0
+CONFIG_AXP_ALDO3_VOLT=0
+CONFIG_AXP_DLDO4_VOLT=0

configs/i12-tvbox_defconfig

@@ -12,5 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,MACPWR=SUNXI_GPH(21)"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/iNet_3F_defconfig

@@ -18,5 +18,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y

configs/iNet_3W_defconfig

@@ -18,5 +18,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y

configs/iNet_86VS_defconfig

@@ -17,5 +17,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y

configs/inet1_defconfig

@@ -18,6 +18,5 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y

configs/inet97fv2_defconfig

@@ -17,5 +17,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y

configs/inet98v_rev2_defconfig

@@ -20,5 +20,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y

configs/inet9f_rev03_defconfig

@@ -17,5 +17,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y

configs/jesurun_q5_defconfig

@@ -12,6 +12,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(19)"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y

configs/mixtile_loftq_defconfig

@@ -15,5 +15,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
 CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/mk802_a10s_defconfig

@@ -12,5 +12,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_AXP152_POWER=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/mk802_defconfig

@@ -11,5 +11,4 @@ CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_SUNXI_NO_PMIC=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/mk802ii_defconfig

@@ -8,5 +8,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/orangepi_pc_defconfig

@@ -12,4 +12,3 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y

configs/orangepi_plus_defconfig

@@ -12,4 +12,3 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y

configs/pov_protab2_ips9_defconfig

@@ -18,5 +18,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y

configs/q8_a13_tablet_defconfig

@@ -20,5 +20,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y

configs/q8_a23_tablet_800x480_defconfig

@@ -22,5 +22,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_AXP_DLDO1_VOLT=3300
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y

configs/q8_a33_tablet_1024x600_defconfig

@@ -22,5 +22,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_AXP_DLDO1_VOLT=3300
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y

configs/q8_a33_tablet_800x480_defconfig

@@ -22,5 +22,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_AXP_DLDO1_VOLT=3300
-CONFIG_SYS_NS16550=y
 CONFIG_USB_MUSB_HOST=y

configs/r7-tv-dongle_defconfig

@@ -11,5 +11,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_AXP152_POWER=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

configs/sunxi_Gemei_G9_defconfig

@@ -15,5 +15,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SYS_NS16550=y
 CONFIG_USB_EHCI_HCD=y

drivers/power/Kconfig

@@ -9,6 +9,7 @@ choice
 	depends on ARCH_SUNXI
 	default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 	default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
+	default AXP818_POWER if MACH_SUN8I_A83T
 	default SUNXI_NO_PMIC if MACH_SUN8I_H3
 
 config SUNXI_NO_PMIC
@@ -37,22 +38,32 @@ config AXP221_POWER
 	Select this to enable support for the axp221/axp223 pmic found on most
 	A23 and A31 boards.
 
+config AXP818_POWER
+	boolean "axp818 pmic support"
+	depends on MACH_SUN8I_A83T
+	---help---
+	Say y here to enable support for the axp818 pmic found on
+	A83T dev board.
+
 endchoice
 
 config AXP_DCDC1_VOLT
 	int "axp pmic dcdc1 voltage"
-	depends on AXP221_POWER
+	depends on AXP221_POWER || AXP818_POWER
+	default 3300 if AXP818_POWER
 	default 3000 if MACH_SUN6I || MACH_SUN8I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to
 	disable dcdc1. On A23 / A31 / A33 (axp221) boards dcdc1 is used for
 	generic 3.3V IO voltage for external devices like the lcd-panal and
 	sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to
-	safe battery. On A31 devices dcdc1 is also used for VCC-IO.
+	safe battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T
+	dcdc1 is used for VCC-IO, nand, usb0, sd , etc.
 
 config AXP_DCDC2_VOLT
 	int "axp pmic dcdc2 voltage"
-	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER
+	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER
+	default 900 if AXP818_POWER
 	default 1400 if AXP152_POWER || AXP209_POWER
 	default 1200 if MACH_SUN6I
 	default 1100 if MACH_SUN8I
@@ -62,10 +73,12 @@ config AXP_DCDC2_VOLT
 	On A10(s) / A13 / A20 boards dcdc2 is VDD-CPU and should be 1.4V.
 	On A31 boards dcdc2 is used for VDD-GPU and should be 1.2V.
 	On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V.
+	On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V.
 
 config AXP_DCDC3_VOLT
 	int "axp pmic dcdc3 voltage"
-	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER
+	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER
+	default 900 if AXP818_POWER
 	default 1500 if AXP152_POWER
 	default 1250 if AXP209_POWER
 	default 1200 if MACH_SUN6I || MACH_SUN8I
@@ -76,10 +89,11 @@ config AXP_DCDC3_VOLT
 	should be 1.25V.
 	On A10s boards with an axp152 dcdc3 is VCC-DRAM and should be 1.5V.
 	On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V.
+	On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V.
 
 config AXP_DCDC4_VOLT
 	int "axp pmic dcdc4 voltage"
-	depends on AXP152_POWER || AXP221_POWER
+	depends on AXP152_POWER || AXP221_POWER || AXP818_POWER
 	default 1250 if AXP152_POWER
 	default 1200 if MACH_SUN6I
 	default 0 if MACH_SUN8I
@@ -89,15 +103,18 @@ config AXP_DCDC4_VOLT
 	On A10s boards with an axp152 dcdc4 is VDD-INT-DLL and should be 1.25V.
 	On A31 boards dcdc4 is used for VDD-SYS and should be 1.2V.
 	On A23 / A33 boards dcdc4 is unused and should be disabled.
+	On A83T boards dcdc4 is used for VDD-GPU.
 
 config AXP_DCDC5_VOLT
 	int "axp pmic dcdc5 voltage"
-	depends on AXP221_POWER
+	depends on AXP221_POWER || AXP818_POWER
+	default 1800 if AXP818_POWER
 	default 1500 if MACH_SUN6I || MACH_SUN8I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to
 	disable dcdc5.
-	On A23 / A31 / A33 boards dcdc5 is VCC-DRAM and should be 1.5V.
+	On A23 / A31 / A33 / A83T boards dcdc5 is VCC-DRAM and should be 1.5V,
+	1.8V for A83T.
 
 config AXP_ALDO1_VOLT
 	int "axp pmic (a)ldo1 voltage"
@@ -112,7 +129,7 @@ config AXP_ALDO1_VOLT
 
 config AXP_ALDO2_VOLT
 	int "axp pmic (a)ldo2 voltage"
-	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER
+	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER
 	default 3000 if AXP152_POWER || AXP209_POWER
 	default 0 if MACH_SUN6I
 	default 2500 if MACH_SUN8I
@@ -126,14 +143,15 @@ config AXP_ALDO2_VOLT
 
 config AXP_ALDO3_VOLT
 	int "axp pmic (a)ldo3 voltage"
-	depends on AXP209_POWER || AXP221_POWER
-	default 0 if AXP209_POWER
+	depends on AXP209_POWER || AXP221_POWER || AXP818_POWER
+	default 0 if AXP209_POWER || AXP818_POWER
 	default 3000 if MACH_SUN6I || MACH_SUN8I
 	---help---
 	Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to
 	disable aldo3.
 	On A10(s) / A13 / A20 boards aldo3 should be 2.8V.
 	On A23 / A31 / A33 boards aldo3 is VCC-PLL and AVCC and should be 3.0V.
+	On A83T aldo3 is used for LVDS, DSI, MIPI, HDMI, etc.
 
 config AXP_ALDO4_VOLT
 	int "axp pmic (a)ldo4 voltage"
@@ -172,7 +190,7 @@ config AXP_DLDO3_VOLT
 
 config AXP_DLDO4_VOLT
 	int "axp pmic dldo4 voltage"
-	depends on AXP221_POWER
+	depends on AXP221_POWER || AXP818_POWER
 	default 0
 	---help---
 	Set the voltage (mV) to program the axp pmic dldo4 at, set to 0 to

drivers/power/Makefile

@@ -9,6 +9,7 @@ obj-$(CONFIG_AS3722_POWER)	+= as3722.o
 obj-$(CONFIG_AXP152_POWER)	+= axp152.o
 obj-$(CONFIG_AXP209_POWER)	+= axp209.o
 obj-$(CONFIG_AXP221_POWER)	+= axp221.o
+obj-$(CONFIG_AXP818_POWER)	+= axp818.o
 obj-$(CONFIG_EXYNOS_TMU)	+= exynos-tmu.o
 obj-$(CONFIG_FTPMU010_POWER)	+= ftpmu010.o
 obj-$(CONFIG_TPS6586X_POWER)	+= tps6586x.o

drivers/power/axp818.c

@@ -0,0 +1,132 @@
+/*
+ * AXP818 driver based on AXP221 driver
+ *
+ *
+ * (C) Copyright 2015 Vishnu Patekar <vishnuptekar0510@gmail.com>
+ *
+ * Based on axp221.c
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pmic_bus.h>
+#include <axp_pmic.h>
+
+static u8 axp818_mvolt_to_cfg(int mvolt, int min, int max, int div)
+{
+	if (mvolt < min)
+		mvolt = min;
+	else if (mvolt > max)
+		mvolt = max;
+
+	return  (mvolt - min) / div;
+}
+
+int axp_set_dcdc1(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg = axp818_mvolt_to_cfg(mvolt, 1600, 3400, 100);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP818_OUTPUT_CTRL1,
+					AXP818_OUTPUT_CTRL1_DCDC1_EN);
+
+	ret = pmic_bus_write(AXP818_DCDC1_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP818_OUTPUT_CTRL1,
+				AXP818_OUTPUT_CTRL1_DCDC1_EN);
+}
+
+int axp_set_dcdc2(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg;
+
+	if (mvolt >= 1220)
+		cfg = 70 + axp818_mvolt_to_cfg(mvolt, 1220, 1300, 20);
+	else
+		cfg = axp818_mvolt_to_cfg(mvolt, 500, 1200, 10);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP818_OUTPUT_CTRL1,
+					AXP818_OUTPUT_CTRL1_DCDC2_EN);
+
+	ret = pmic_bus_write(AXP818_DCDC2_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP818_OUTPUT_CTRL1,
+				AXP818_OUTPUT_CTRL1_DCDC2_EN);
+}
+
+int axp_set_dcdc3(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg;
+
+	if (mvolt >= 1220)
+		cfg = 70 + axp818_mvolt_to_cfg(mvolt, 1220, 1300, 20);
+	else
+		cfg = axp818_mvolt_to_cfg(mvolt, 500, 1200, 10);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP818_OUTPUT_CTRL1,
+					AXP818_OUTPUT_CTRL1_DCDC3_EN);
+
+	ret = pmic_bus_write(AXP818_DCDC3_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP818_OUTPUT_CTRL1,
+				AXP818_OUTPUT_CTRL1_DCDC3_EN);
+}
+
+int axp_set_dcdc5(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg;
+
+	if (mvolt >= 1140)
+		cfg = 32 + axp818_mvolt_to_cfg(mvolt, 1140, 1840, 20);
+	else
+		cfg = axp818_mvolt_to_cfg(mvolt, 800, 1120, 10);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP818_OUTPUT_CTRL1,
+					AXP818_OUTPUT_CTRL1_DCDC5_EN);
+
+	ret = pmic_bus_write(AXP818_DCDC5_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP818_OUTPUT_CTRL1,
+				AXP818_OUTPUT_CTRL1_DCDC5_EN);
+}
+
+int axp_init(void)
+{
+	u8 axp_chip_id;
+	int ret;
+
+	ret = pmic_bus_init();
+	if (ret)
+		return ret;
+
+	ret = pmic_bus_read(AXP818_CHIP_ID, &axp_chip_id);
+	if (ret)
+		return ret;
+
+	if (!(axp_chip_id == 0x51))
+		return -ENODEV;
+	else
+		return ret;
+
+	return 0;
+}

include/axp818.h

@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ *
+ * X-Powers AXP818 Power Management IC driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define AXP818_CHIP_ID		0x03
+
+#define AXP818_OUTPUT_CTRL1	0x10
+#define AXP818_OUTPUT_CTRL1_DCDC1_EN	(1 << 0)
+#define AXP818_OUTPUT_CTRL1_DCDC2_EN	(1 << 1)
+#define AXP818_OUTPUT_CTRL1_DCDC3_EN	(1 << 2)
+#define AXP818_OUTPUT_CTRL1_DCDC4_EN	(1 << 3)
+#define AXP818_OUTPUT_CTRL1_DCDC5_EN	(1 << 4)
+#define AXP818_OUTPUT_CTRL1_DCDC6_EN	(1 << 5)
+#define AXP818_OUTPUT_CTRL1_DCDC7_EN	(1 << 6)
+#define AXP818_OUTPUT_CTRL2	0x12
+#define AXP818_OUTPUT_CTRL2_ELDO1_EN	(1 << 0)
+#define AXP818_OUTPUT_CTRL2_ELDO2_EN	(1 << 1)
+#define AXP818_OUTPUT_CTRL2_ELDO3_EN	(1 << 2)
+#define AXP818_OUTPUT_CTRL2_DLDO1_EN	(1 << 3)
+#define AXP818_OUTPUT_CTRL2_DLDO2_EN	(1 << 4)
+#define AXP818_OUTPUT_CTRL2_DLDO3_EN	(1 << 5)
+#define AXP818_OUTPUT_CTRL2_DLDO4_EN	(1 << 6)
+#define AXP818_OUTPUT_CTRL3	0x13
+#define AXP818_OUTPUT_CTRL3_FLDO1_EN	(1 << 2)
+#define AXP818_OUTPUT_CTRL3_FLDO2_EN	(1 << 3)
+#define AXP818_OUTPUT_CTRL3_FLDO3_EN	(1 << 4)
+#define AXP818_OUTPUT_CTRL3_ALDO1_EN	(1 << 5)
+#define AXP818_OUTPUT_CTRL3_ALDO2_EN	(1 << 6)
+#define AXP818_OUTPUT_CTRL3_ALDO3_EN	(1 << 7)
+
+#define AXP818_DCDC1_CTRL	0x20
+#define AXP818_DCDC2_CTRL	0x21
+#define AXP818_DCDC3_CTRL	0x22
+#define AXP818_DCDC4_CTRL	0x23
+#define AXP818_DCDC5_CTRL	0x24
+#define AXP818_DCDC6_CTRL	0x25
+
+#define AXP818_DLDO1_CTRL	0x15
+#define AXP818_DLDO2_CTRL	0x16
+#define AXP818_DLDO3_CTRL	0x17
+#define AXP818_DLDO4_CTRL	0x18
+#define AXP818_ELDO1_CTRL	0x19
+#define AXP818_ELDO2_CTRL	0x1a
+#define AXP818_ELDO3_CTRL	0x1b
+#define AXP818_ELDO3_CTRL	0x1b
+#define AXP818_FLDO1_CTRL	0x1c
+#define AXP818_FLDO2_3_CTRL	0x1d
+#define AXP818_DCDC1_CTRL	0x20
+#define AXP818_DCDC2_CTRL	0x21
+#define AXP818_DCDC3_CTRL	0x22
+#define AXP818_DCDC4_CTRL	0x23
+#define AXP818_DCDC5_CTRL	0x24
+#define AXP818_DCDC6_CTRL	0x25
+#define AXP818_DCDC7_CTRL	0x26
+
+#define AXP818_ALDO1_CTRL	0x28
+#define AXP818_ALDO2_CTRL	0x29
+#define AXP818_ALDO3_CTRL	0x2a
+
+int axp818_init(void);
+
+/* For axp_gpio.c */
+#define AXP_POWER_STATUS		0x00
+#define AXP_POWER_STATUS_VBUS_PRESENT	(1 << 5)
+#define AXP_GPIO0_CTRL			0x90
+#define AXP_GPIO1_CTRL			0x92
+#define AXP_GPIO_CTRL_OUTPUT_LOW	0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH	0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT		0x02 /* Input */
+#define AXP_GPIO_STATE			0x94
+#define AXP_GPIO_STATE_OFFSET		0