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board/freescale/common: IDT8T49N222A configuration code
Add code for configuring IDT8T49N222A device for various output refclks
- The IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer with
alarm and monitoring functions suitable for networking and
communications applications. It is able to generate wide range of output
frequencies.
- In B4860QDS, it has been used to generate different refclks to SerDes modules
- Programming of these devices are performed by I2C interface.
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Shaveta Leekha
York Sun
parent
f9d379a707
commit
a5b225181e
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@ -54,6 +54,7 @@ COBJS-$(CONFIG_P4080DS) += ics307_clk.o
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COBJS-$(CONFIG_P5020DS) += ics307_clk.o
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COBJS-$(CONFIG_P5040DS) += ics307_clk.o
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COBJS-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
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COBJS-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
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# deal with common files for P-series corenet based devices
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SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o
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220
board/freescale/common/idt8t49n222a_serdes_clk.c
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220
board/freescale/common/idt8t49n222a_serdes_clk.c
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@ -0,0 +1,220 @@
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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* Author: Shaveta Leekha <shaveta@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "idt8t49n222a_serdes_clk.h"
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#define DEVICE_ID_REG 0x00
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static int check_pll_status(u8 idt_addr)
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{
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u8 val = 0;
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int ret;
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ret = i2c_read(idt_addr, 0x17, 1, &val, 1);
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if (ret < 0) {
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printf("IDT:0x%x could not read status register from device.\n",
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idt_addr);
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return ret;
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}
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if (val & 0x04) {
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debug("idt8t49n222a PLL is LOCKED: %x\n", val);
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} else {
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printf("idt8t49n222a PLL is not LOCKED: %x\n", val);
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return -1;
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}
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return 0;
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}
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int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
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enum serdes_refclk refclk1,
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enum serdes_refclk refclk2, u8 feedback)
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{
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u8 dev_id = 0;
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int i, ret;
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debug("IDT:Configuring idt8t49n222a device at I2C address: 0x%2x\n",
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idt_addr);
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ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1);
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if (ret < 0) {
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debug("IDT:0x%x could not read DEV_ID from device.\n",
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idt_addr);
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return ret;
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}
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if ((dev_id != 0x00) && (dev_id != 0x24) && (dev_id != 0x2a)) {
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debug("IDT: device at address 0x%x is not idt8t49n222a.\n",
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idt_addr);
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}
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if (serdes_num != 1 && serdes_num != 2) {
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debug("serdes_num should be 1 for SerDes1 and"
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" 2 for SerDes2.\n");
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return -1;
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}
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if ((refclk1 == SERDES_REFCLK_122_88 && refclk2 != SERDES_REFCLK_122_88)
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|| (refclk1 != SERDES_REFCLK_122_88
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&& refclk2 == SERDES_REFCLK_122_88)) {
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debug("Only one refclk at 122.88MHz is not supported."
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" Please set both refclk1 & refclk2 to 122.88MHz"
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" or both not to 122.88MHz.\n");
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return -1;
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}
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if (refclk1 != SERDES_REFCLK_100 && refclk1 != SERDES_REFCLK_122_88
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&& refclk1 != SERDES_REFCLK_125
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&& refclk1 != SERDES_REFCLK_156_25) {
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debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz"
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" or 156.25MHz.\n");
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return -1;
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}
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if (refclk2 != SERDES_REFCLK_100 && refclk2 != SERDES_REFCLK_122_88
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&& refclk2 != SERDES_REFCLK_125
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&& refclk2 != SERDES_REFCLK_156_25) {
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debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz"
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" or 156.25MHz.\n");
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return -1;
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}
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if (feedback != 0 && feedback != 1) {
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debug("valid values for feedback are 0(default) or 1.\n");
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return -1;
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 122.88MHz Refclk2 = 122.88MHz
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*/
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if (refclk1 == SERDES_REFCLK_122_88 &&
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refclk2 == SERDES_REFCLK_122_88) {
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printf("Setting refclk1:122.88 and refclk2:122.88\n");
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for (i = 0; i < NUM_IDT_REGS; i++)
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i2c_reg_write(idt_addr, idt_conf_122_88[i][0],
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idt_conf_122_88[i][1]);
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if (feedback) {
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for (i = 0; i < NUM_IDT_REGS_FEEDBACK; i++)
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i2c_reg_write(idt_addr,
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idt_conf_122_88_feedback[i][0],
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idt_conf_122_88_feedback[i][1]);
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}
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}
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if (refclk1 != SERDES_REFCLK_122_88 &&
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refclk2 != SERDES_REFCLK_122_88) {
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for (i = 0; i < NUM_IDT_REGS; i++)
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i2c_reg_write(idt_addr, idt_conf_not_122_88[i][0],
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idt_conf_not_122_88[i][1]);
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 100MHz Refclk2 = 125MHz
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*/
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if (refclk1 == SERDES_REFCLK_100 && refclk2 == SERDES_REFCLK_125) {
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printf("Setting refclk1:100 and refclk2:125\n");
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i2c_reg_write(idt_addr, 0x11, 0x10);
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 125MHz Refclk2 = 125MHz
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*/
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if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_125) {
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printf("Setting refclk1:125 and refclk2:125\n");
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i2c_reg_write(idt_addr, 0x10, 0x10);
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i2c_reg_write(idt_addr, 0x11, 0x10);
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 125MHz Refclk2 = 100MHz
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*/
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if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_100) {
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printf("Setting refclk1:125 and refclk2:100\n");
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i2c_reg_write(idt_addr, 0x10, 0x10);
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 156.25MHz Refclk2 = 156.25MHz
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*/
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if (refclk1 == SERDES_REFCLK_156_25 &&
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refclk2 == SERDES_REFCLK_156_25) {
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printf("Setting refclk1:156.25 and refclk2:156.25\n");
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for (i = 0; i < NUM_IDT_REGS_156_25; i++)
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i2c_reg_write(idt_addr, idt_conf_156_25[i][0],
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idt_conf_156_25[i][1]);
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 100MHz Refclk2 = 156.25MHz
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*/
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if (refclk1 == SERDES_REFCLK_100 &&
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refclk2 == SERDES_REFCLK_156_25) {
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printf("Setting refclk1:100 and refclk2:156.25\n");
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for (i = 0; i < NUM_IDT_REGS_156_25; i++)
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i2c_reg_write(idt_addr, idt_conf_100_156_25[i][0],
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idt_conf_100_156_25[i][1]);
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 125MHz Refclk2 = 156.25MHz
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*/
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if (refclk1 == SERDES_REFCLK_125 &&
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refclk2 == SERDES_REFCLK_156_25) {
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printf("Setting refclk1:125 and refclk2:156.25\n");
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for (i = 0; i < NUM_IDT_REGS_156_25; i++)
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i2c_reg_write(idt_addr, idt_conf_125_156_25[i][0],
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idt_conf_125_156_25[i][1]);
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 156.25MHz Refclk2 = 100MHz
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*/
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if (refclk1 == SERDES_REFCLK_156_25 &&
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refclk2 == SERDES_REFCLK_100) {
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printf("Setting refclk1:156.25 and refclk2:100\n");
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for (i = 0; i < NUM_IDT_REGS_156_25; i++)
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i2c_reg_write(idt_addr, idt_conf_156_25_100[i][0],
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idt_conf_156_25_100[i][1]);
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 156.25MHz Refclk2 = 125MHz
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*/
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if (refclk1 == SERDES_REFCLK_156_25 &&
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refclk2 == SERDES_REFCLK_125) {
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printf("Setting refclk1:156.25 and refclk2:125\n");
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for (i = 0; i < NUM_IDT_REGS_156_25; i++)
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i2c_reg_write(idt_addr, idt_conf_156_25_125[i][0],
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idt_conf_156_25_125[i][1]);
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}
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/* waiting for maximum of 1 second if PLL doesn'r get locked
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* initially. then check the status again.
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*/
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if (check_pll_status(idt_addr)) {
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mdelay(1000);
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if (check_pll_status(idt_addr))
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return -1;
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}
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return 0;
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}
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120
board/freescale/common/idt8t49n222a_serdes_clk.h
Normal file
120
board/freescale/common/idt8t49n222a_serdes_clk.h
Normal file
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@ -0,0 +1,120 @@
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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* Author: Shaveta Leekha <shaveta@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __IDT8T49N222A_SERDES_CLK_H_
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#define __IDT8T49N222A_SERDES_CLK_H_ 1
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#include <common.h>
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#include <i2c.h>
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#include "qixis.h"
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#include "../b4860qds/b4860qds_qixis.h"
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#include <errno.h>
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#define NUM_IDT_REGS 23
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#define NUM_IDT_REGS_FEEDBACK 12
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#define NUM_IDT_REGS_156_25 11
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/* CLK */
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enum serdes_refclk {
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SERDES_REFCLK_100, /* refclk 100Mhz */
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SERDES_REFCLK_122_88, /* refclk 122.88Mhz */
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SERDES_REFCLK_125, /* refclk 125Mhz */
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SERDES_REFCLK_156_25, /* refclk 156.25Mhz */
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SERDES_REFCLK_NONE = -1,
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};
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/* configuration values for IDT registers for Output Refclks:
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* Refclk1 = 122.88MHz Refclk2 = 122.88MHz
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*/
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static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00},
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{0x02, 0x9F}, {0x03, 0x00}, {0x04, 0x0B}, {0x05, 0x00},
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{0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
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{0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
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{0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x12}, {0x11, 0x12},
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{0x12, 0xB9}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
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{0x16, 0xA0} };
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/* configuration values for IDT registers for Output Refclks:
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* Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
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*/
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static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00},
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{0x02, 0x00}, {0x03, 0x00}, {0x04, 0x0A}, {0x05, 0x00},
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{0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
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{0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
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{0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x14}, {0x11, 0x14},
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{0x12, 0x35}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
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{0x16, 0xA0} };
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/* Reconfiguration values for some of IDT registers for
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* Output Refclks:
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* Refclk1 = 122.88MHz Refclk2 = 122.88MHz
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* and with feedback as 1
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*/
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static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7},
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{0x04, 0x89}, {0x06, 0xC3}, {0x08, 0xC0}, {0x0A, 0x07},
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{0x0C, 0x80}, {0x10, 0x10}, {0x11, 0x10}, {0x12, 0x1B},
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{0x14, 0x00}, {0x15, 0xE8} };
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/* configuration values for IDT registers for Output Refclks:
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* Refclk1 : 156.25MHz Refclk2 : 156.25MHz
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*/
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static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
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{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
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{0x10, 0x10}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
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{0x15, 0xE8} };
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/* configuration values for IDT registers for Output Refclks:
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* Refclk1 : 100MHz Refclk2 : 156.25MHz
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*/
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static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
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{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
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{0x10, 0x19}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
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{0x15, 0xE8} };
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/* configuration values for IDT registers for Output Refclks:
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* Refclk1 : 125MHz Refclk2 : 156.25MHz
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*/
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static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
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{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
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{0x10, 0x14}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
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{0x15, 0xE8} };
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/* configuration values for IDT registers for Output Refclks:
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* Refclk1 : 156.25MHz Refclk2 : 100MHz
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*/
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static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03},
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{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
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{0x10, 0x10}, {0x11, 0x19}, {0x12, 0xB5}, {0x13, 0x3C},
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{0x15, 0xE8} };
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/* configuration values for IDT registers for Output Refclks:
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* Refclk1 : 156.25MHz Refclk2 : 125MHz
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*/
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static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03},
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{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
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{0x10, 0x10}, {0x11, 0x14}, {0x12, 0xB5}, {0x13, 0x3C},
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{0x15, 0xE8} };
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int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
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enum serdes_refclk refclk1,
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enum serdes_refclk refclk2, u8 feedback);
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#endif /*__IDT8T49N222A_SERDES_CLK_H_ */
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