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https://github.com/brain-hackers/u-boot-brain
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EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequency
Adds functions to extract clock frequency of Exynos4x12 IPs. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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@ -112,6 +112,36 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
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return exynos_get_pll_clk(pllreg, r, k);
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return exynos_get_pll_clk(pllreg, r, k);
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}
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}
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/* exynos4x12: return pll clock frequency */
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static unsigned long exynos4x12_get_pll_clk(int pllreg)
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{
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struct exynos4x12_clock *clk =
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(struct exynos4x12_clock *)samsung_get_base_clock();
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unsigned long r, k = 0;
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switch (pllreg) {
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case APLL:
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r = readl(&clk->apll_con0);
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break;
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case MPLL:
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r = readl(&clk->mpll_con0);
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break;
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case EPLL:
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r = readl(&clk->epll_con0);
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k = readl(&clk->epll_con1);
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break;
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case VPLL:
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r = readl(&clk->vpll_con0);
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k = readl(&clk->vpll_con1);
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break;
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default:
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printf("Unsupported PLL (%d)\n", pllreg);
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return 0;
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}
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return exynos_get_pll_clk(pllreg, r, k);
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}
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/* exynos5: return pll clock frequency */
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/* exynos5: return pll clock frequency */
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static unsigned long exynos5_get_pll_clk(int pllreg)
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static unsigned long exynos5_get_pll_clk(int pllreg)
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{
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{
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@ -193,6 +223,28 @@ static unsigned long exynos4_get_arm_clk(void)
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return armclk;
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return armclk;
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}
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}
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/* exynos4x12: return ARM clock frequency */
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static unsigned long exynos4x12_get_arm_clk(void)
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{
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struct exynos4x12_clock *clk =
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(struct exynos4x12_clock *)samsung_get_base_clock();
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unsigned long div;
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unsigned long armclk;
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unsigned int core_ratio;
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unsigned int core2_ratio;
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div = readl(&clk->div_cpu0);
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/* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
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core_ratio = (div >> 0) & 0x7;
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core2_ratio = (div >> 28) & 0x7;
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armclk = get_pll_clk(APLL) / (core_ratio + 1);
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armclk /= (core2_ratio + 1);
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return armclk;
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}
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/* exynos5: return ARM clock frequency */
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/* exynos5: return ARM clock frequency */
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static unsigned long exynos5_get_arm_clk(void)
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static unsigned long exynos5_get_arm_clk(void)
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{
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{
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@ -258,6 +310,20 @@ static unsigned long exynos4_get_pwm_clk(void)
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return pclk;
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return pclk;
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}
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}
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/* exynos4x12: return pwm clock frequency */
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static unsigned long exynos4x12_get_pwm_clk(void)
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{
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unsigned long pclk, sclk;
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unsigned int ratio;
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sclk = get_pll_clk(MPLL);
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ratio = 8;
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pclk = sclk / (ratio + 1);
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return pclk;
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}
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/* exynos5: return pwm clock frequency */
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/* exynos5: return pwm clock frequency */
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static unsigned long exynos5_get_pwm_clk(void)
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static unsigned long exynos5_get_pwm_clk(void)
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{
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{
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@ -326,6 +392,51 @@ static unsigned long exynos4_get_uart_clk(int dev_index)
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return uclk;
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return uclk;
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}
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}
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/* exynos4x12: return uart clock frequency */
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static unsigned long exynos4x12_get_uart_clk(int dev_index)
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{
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struct exynos4x12_clock *clk =
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(struct exynos4x12_clock *)samsung_get_base_clock();
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unsigned long uclk, sclk;
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unsigned int sel;
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unsigned int ratio;
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/*
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* CLK_SRC_PERIL0
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* UART0_SEL [3:0]
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* UART1_SEL [7:4]
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* UART2_SEL [8:11]
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* UART3_SEL [12:15]
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* UART4_SEL [16:19]
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*/
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sel = readl(&clk->src_peril0);
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sel = (sel >> (dev_index << 2)) & 0xf;
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if (sel == 0x6)
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sclk = get_pll_clk(MPLL);
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else if (sel == 0x7)
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sclk = get_pll_clk(EPLL);
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else if (sel == 0x8)
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sclk = get_pll_clk(VPLL);
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else
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return 0;
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/*
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* CLK_DIV_PERIL0
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* UART0_RATIO [3:0]
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* UART1_RATIO [7:4]
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* UART2_RATIO [8:11]
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* UART3_RATIO [12:15]
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* UART4_RATIO [16:19]
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*/
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ratio = readl(&clk->div_peril0);
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ratio = (ratio >> (dev_index << 2)) & 0xf;
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uclk = sclk / (ratio + 1);
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return uclk;
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}
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/* exynos5: return uart clock frequency */
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/* exynos5: return uart clock frequency */
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static unsigned long exynos5_get_uart_clk(int dev_index)
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static unsigned long exynos5_get_uart_clk(int dev_index)
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{
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{
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@ -400,6 +511,33 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
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writel(val, addr);
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writel(val, addr);
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}
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}
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/* exynos4x12: set the mmc clock */
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static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
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{
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struct exynos4x12_clock *clk =
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(struct exynos4x12_clock *)samsung_get_base_clock();
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unsigned int addr;
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unsigned int val;
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/*
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* CLK_DIV_FSYS1
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* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
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* CLK_DIV_FSYS2
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* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
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*/
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if (dev_index < 2) {
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addr = (unsigned int)&clk->div_fsys1;
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} else {
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addr = (unsigned int)&clk->div_fsys2;
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dev_index -= 2;
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}
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val = readl(addr);
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val &= ~(0xff << ((dev_index << 4) + 8));
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val |= (div & 0xff) << ((dev_index << 4) + 8);
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writel(val, addr);
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}
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/* exynos5: set the mmc clock */
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/* exynos5: set the mmc clock */
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static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
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static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
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{
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{
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@ -940,16 +1078,22 @@ unsigned long get_pll_clk(int pllreg)
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{
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{
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if (cpu_is_exynos5())
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if (cpu_is_exynos5())
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return exynos5_get_pll_clk(pllreg);
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return exynos5_get_pll_clk(pllreg);
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else
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else {
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if (proid_is_exynos4412())
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return exynos4x12_get_pll_clk(pllreg);
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return exynos4_get_pll_clk(pllreg);
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return exynos4_get_pll_clk(pllreg);
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}
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}
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}
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unsigned long get_arm_clk(void)
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unsigned long get_arm_clk(void)
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{
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{
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if (cpu_is_exynos5())
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if (cpu_is_exynos5())
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return exynos5_get_arm_clk();
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return exynos5_get_arm_clk();
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else
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else {
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if (proid_is_exynos4412())
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return exynos4x12_get_arm_clk();
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return exynos4_get_arm_clk();
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return exynos4_get_arm_clk();
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}
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}
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}
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unsigned long get_i2c_clk(void)
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unsigned long get_i2c_clk(void)
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@ -968,24 +1112,33 @@ unsigned long get_pwm_clk(void)
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{
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{
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if (cpu_is_exynos5())
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if (cpu_is_exynos5())
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return exynos5_get_pwm_clk();
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return exynos5_get_pwm_clk();
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else
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else {
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if (proid_is_exynos4412())
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return exynos4x12_get_pwm_clk();
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return exynos4_get_pwm_clk();
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return exynos4_get_pwm_clk();
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}
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}
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}
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unsigned long get_uart_clk(int dev_index)
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unsigned long get_uart_clk(int dev_index)
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{
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{
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if (cpu_is_exynos5())
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if (cpu_is_exynos5())
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return exynos5_get_uart_clk(dev_index);
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return exynos5_get_uart_clk(dev_index);
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else
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else {
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if (proid_is_exynos4412())
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return exynos4x12_get_uart_clk(dev_index);
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return exynos4_get_uart_clk(dev_index);
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return exynos4_get_uart_clk(dev_index);
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}
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}
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}
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void set_mmc_clk(int dev_index, unsigned int div)
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void set_mmc_clk(int dev_index, unsigned int div)
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{
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{
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if (cpu_is_exynos5())
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if (cpu_is_exynos5())
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exynos5_set_mmc_clk(dev_index, div);
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exynos5_set_mmc_clk(dev_index, div);
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else
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else {
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if (proid_is_exynos4412())
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exynos4x12_set_mmc_clk(dev_index, div);
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exynos4_set_mmc_clk(dev_index, div);
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exynos4_set_mmc_clk(dev_index, div);
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}
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}
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}
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unsigned long get_lcd_clk(void)
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unsigned long get_lcd_clk(void)
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