Rockchip-focused changes for v2018.11-rc2:
- fixes to rkimage for SPL boot via USB - fixes to make_fit_atf.py, incl. entry-point calculation and python3 compatibility - OP-TEE support for ARMv7-based SoCs - fixes to RGMII/GMII selection on the RK3328 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJbt0FOAAoJECaAFcEOcohNZmcH/A1mKO0/R4tHCqFP2j0I+OuP PClkA1HUZuD5phvPMaxdHQBwsq7sAa8AljK1oPCNkslP7mFxToUUBx7xc0vB89P/ D+XsI4uce89hIyTULR2FdhR22MOk41zaLVeNicpQ1keCNbzCwsHsHTA+B4XN/xNe tdPpu6wN2D+g88DAv+/ebVYgjmxRvFD4qpL9bbZpOqqA8XCcD31ukCR2E4fsESgn mzwKaKcX6SeYgTVCT8Q15SLTNI1WRUY1Y1laj1WKl4abY+HsTt4Whm9imM2l3K5W ODj6vnFlwEC9rgdxmtXGcmBfwtyXubSfuZDrMGFAiOlyIUgpPXWZI7i8LYQbZ7s= =NdBl -----END PGP SIGNATURE----- Merge tag 'rockchip-for-v2018.11-rc2' of git://git.denx.de/u-boot-rockchip Rockchip-focused changes for v2018.11-rc2: - fixes to rkimage for SPL boot via USB - fixes to make_fit_atf.py, incl. entry-point calculation and python3 compatibility - OP-TEE support for ARMv7-based SoCs - fixes to RGMII/GMII selection on the RK3328 Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
commit
a4b38fca7e
5
Makefile
5
Makefile
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@ -1074,7 +1074,10 @@ U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
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else
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else
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ifneq ($(CONFIG_SPL_FIT_GENERATOR),"")
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ifneq ($(CONFIG_SPL_FIT_GENERATOR),"")
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U_BOOT_ITS := u-boot.its
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U_BOOT_ITS := u-boot.its
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$(U_BOOT_ITS): FORCE
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ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py")
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U_BOOT_ITS_DEPS += u-boot
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endif
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$(U_BOOT_ITS): $(U_BOOT_ITS_DEPS) FORCE
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$(srctree)/$(CONFIG_SPL_FIT_GENERATOR) \
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$(srctree)/$(CONFIG_SPL_FIT_GENERATOR) \
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$(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) > $@
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$(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) > $@
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endif
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endif
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@ -0,0 +1,50 @@
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/*
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* Copyright (C) 2017 Rockchip Electronic Co.,Ltd
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*
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* Simple U-boot fit source file containing U-Boot, dtb and optee
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*/
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/dts-v1/;
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/ {
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description = "Simple image with OP-TEE support";
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#address-cells = <1>;
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images {
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uboot@1 {
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description = "U-Boot";
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data = /incbin/("../../../u-boot-nodtb.bin");
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type = "standalone";
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os = "U-Boot";
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arch = "arm";
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compression = "none";
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load = <0x61000000>;
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};
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optee@1 {
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description = "OP-TEE";
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data = /incbin/("../../../tee.bin");
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type = "firmware";
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arch = "arm";
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os = "tee";
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compression = "none";
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load = <0x68400000>;
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entry = <0x68400000>;
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};
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fdt@1 {
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description = "dtb";
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data = /incbin/("../../../u-boot.dtb");
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type = "flat_dt";
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compression = "none";
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};
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};
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configurations {
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default = "conf@1";
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conf@1 {
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description = "Rockchip armv7 with OP-TEE";
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firmware = "optee@1";
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loadables = "uboot@1";
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fdt = "fdt@1";
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};
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};
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};
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@ -1,4 +1,4 @@
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#!/usr/bin/env python2
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#!/usr/bin/env python
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"""
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"""
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A script to generate FIT image source for rockchip boards
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A script to generate FIT image source for rockchip boards
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with ARM Trusted Firmware
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with ARM Trusted Firmware
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@ -34,7 +34,7 @@ DT_HEADER="""// SPDX-License-Identifier: GPL-2.0+ OR X11
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#address-cells = <1>;
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#address-cells = <1>;
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|
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images {
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images {
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uboot@1 {
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uboot {
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description = "U-Boot (64-bit)";
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description = "U-Boot (64-bit)";
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data = /incbin/("u-boot-nodtb.bin");
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data = /incbin/("u-boot-nodtb.bin");
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type = "standalone";
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type = "standalone";
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@ -43,6 +43,7 @@ DT_HEADER="""// SPDX-License-Identifier: GPL-2.0+ OR X11
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compression = "none";
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compression = "none";
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load = <0x%08x>;
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load = <0x%08x>;
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};
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};
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"""
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"""
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DT_IMAGES_NODE_END="""
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DT_IMAGES_NODE_END="""
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@ -53,23 +54,23 @@ DT_END="""
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};
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};
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"""
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"""
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def append_atf_node(file, atf_index, phy_addr):
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def append_atf_node(file, atf_index, phy_addr, elf_entry):
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"""
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"""
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Append ATF DT node to input FIT dts file.
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Append ATF DT node to input FIT dts file.
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"""
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"""
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data = 'bl31_0x%08x.bin' % phy_addr
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data = 'bl31_0x%08x.bin' % phy_addr
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print >> file, '\t\tatf@%d {' % atf_index
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file.write('\t\tatf_%d {\n' % atf_index)
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print >> file, '\t\t\tdescription = \"ARM Trusted Firmware\";'
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file.write('\t\t\tdescription = \"ARM Trusted Firmware\";\n')
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print >> file, '\t\t\tdata = /incbin/("%s");' % data
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file.write('\t\t\tdata = /incbin/("%s");\n' % data)
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print >> file, '\t\t\ttype = "firmware";'
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file.write('\t\t\ttype = "firmware";\n')
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print >> file, '\t\t\tarch = "arm64";'
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file.write('\t\t\tarch = "arm64";\n')
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print >> file, '\t\t\tos = "arm-trusted-firmware";'
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file.write('\t\t\tos = "arm-trusted-firmware";\n')
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print >> file, '\t\t\tcompression = "none";'
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file.write('\t\t\tcompression = "none";\n')
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print >> file, '\t\t\tload = <0x%08x>;' % phy_addr
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file.write('\t\t\tload = <0x%08x>;\n' % phy_addr)
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if atf_index == 1:
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if atf_index == 1:
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print >> file, '\t\t\tentry = <0x%08x>;' % phy_addr
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file.write('\t\t\tentry = <0x%08x>;\n' % elf_entry)
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print >> file, '\t\t};'
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file.write('\t\t};\n')
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print >> file, ''
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file.write('\n')
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def append_fdt_node(file, dtbs):
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def append_fdt_node(file, dtbs):
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"""
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"""
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@ -78,43 +79,43 @@ def append_fdt_node(file, dtbs):
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cnt = 1
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cnt = 1
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for dtb in dtbs:
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for dtb in dtbs:
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dtname = os.path.basename(dtb)
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dtname = os.path.basename(dtb)
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print >> file, '\t\tfdt@%d {' % cnt
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file.write('\t\tfdt_%d {\n' % cnt)
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print >> file, '\t\t\tdescription = "%s";' % dtname
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file.write('\t\t\tdescription = "%s";\n' % dtname)
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print >> file, '\t\t\tdata = /incbin/("%s");' % dtb
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file.write('\t\t\tdata = /incbin/("%s");\n' % dtb)
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print >> file, '\t\t\ttype = "flat_dt";'
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file.write('\t\t\ttype = "flat_dt";\n')
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print >> file, '\t\t\tcompression = "none";'
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file.write('\t\t\tcompression = "none";\n')
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print >> file, '\t\t};'
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file.write('\t\t};\n')
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print >> file, ''
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file.write('\n')
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cnt = cnt + 1
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cnt = cnt + 1
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def append_conf_section(file, cnt, dtname, atf_cnt):
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def append_conf_section(file, cnt, dtname, atf_cnt):
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print >> file, '\t\tconfig@%d {' % cnt
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file.write('\t\tconfig_%d {\n' % cnt)
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print >> file, '\t\t\tdescription = "%s";' % dtname
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file.write('\t\t\tdescription = "%s";\n' % dtname)
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print >> file, '\t\t\tfirmware = "atf@1";'
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file.write('\t\t\tfirmware = "atf_1";\n')
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print >> file, '\t\t\tloadables = "uboot@1",',
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file.write('\t\t\tloadables = "uboot",')
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for i in range(1, atf_cnt):
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for i in range(1, atf_cnt):
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print >> file, '"atf@%d"' % (i+1),
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file.write('"atf_%d"' % (i+1))
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if i != (atf_cnt - 1):
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if i != (atf_cnt - 1):
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print >> file, ',',
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file.write(',')
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else:
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else:
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print >> file, ';'
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file.write(';\n')
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print >> file, '\t\t\tfdt = "fdt@1";'
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file.write('\t\t\tfdt = "fdt_1";\n')
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print >> file, '\t\t};'
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file.write('\t\t};\n')
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print >> file, ''
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file.write('\n')
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def append_conf_node(file, dtbs, atf_cnt):
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def append_conf_node(file, dtbs, atf_cnt):
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"""
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"""
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Append configeration nodes.
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Append configeration nodes.
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"""
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"""
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cnt = 1
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cnt = 1
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print >> file, '\tconfigurations {'
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file.write('\tconfigurations {\n')
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print >> file, '\t\tdefault = "config@1";'
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file.write('\t\tdefault = "config_1";\n')
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for dtb in dtbs:
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for dtb in dtbs:
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dtname = os.path.basename(dtb)
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dtname = os.path.basename(dtb)
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append_conf_section(file, cnt, dtname, atf_cnt)
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append_conf_section(file, cnt, dtname, atf_cnt)
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cnt = cnt + 1
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cnt = cnt + 1
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print >> file, '\t};'
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file.write('\t};\n')
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print >> file, ''
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file.write('\n')
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def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_file_name):
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def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_file_name):
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"""
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"""
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@ -127,7 +128,7 @@ def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_fi
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|
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num_load_seg = 0
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num_load_seg = 0
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p_paddr = 0xFFFFFFFF
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p_paddr = 0xFFFFFFFF
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with open(uboot_file_name) as uboot_file:
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with open(uboot_file_name, 'rb') as uboot_file:
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uboot = ELFFile(uboot_file)
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uboot = ELFFile(uboot_file)
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for i in range(uboot.num_segments()):
|
for i in range(uboot.num_segments()):
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seg = uboot.get_segment(i)
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seg = uboot.get_segment(i)
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@ -137,27 +138,28 @@ def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_fi
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|
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assert (p_paddr != 0xFFFFFFFF and num_load_seg == 1)
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assert (p_paddr != 0xFFFFFFFF and num_load_seg == 1)
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|
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print >> fit_file, DT_HEADER % p_paddr
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fit_file.write(DT_HEADER % p_paddr)
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|
|
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with open(bl31_file_name) as bl31_file:
|
with open(bl31_file_name, 'rb') as bl31_file:
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bl31 = ELFFile(bl31_file)
|
bl31 = ELFFile(bl31_file)
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|
elf_entry = bl31.header['e_entry']
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for i in range(bl31.num_segments()):
|
for i in range(bl31.num_segments()):
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seg = bl31.get_segment(i)
|
seg = bl31.get_segment(i)
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if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)):
|
if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)):
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paddr = seg.__getitem__(ELF_SEG_P_PADDR)
|
paddr = seg.__getitem__(ELF_SEG_P_PADDR)
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p= seg.__getitem__(ELF_SEG_P_PADDR)
|
p= seg.__getitem__(ELF_SEG_P_PADDR)
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append_atf_node(fit_file, i+1, paddr)
|
append_atf_node(fit_file, i+1, paddr, elf_entry)
|
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atf_cnt = i+1
|
atf_cnt = i+1
|
||||||
append_fdt_node(fit_file, dtbs_file_name)
|
append_fdt_node(fit_file, dtbs_file_name)
|
||||||
print >> fit_file, '%s' % DT_IMAGES_NODE_END
|
fit_file.write('%s\n' % DT_IMAGES_NODE_END)
|
||||||
append_conf_node(fit_file, dtbs_file_name, atf_cnt)
|
append_conf_node(fit_file, dtbs_file_name, atf_cnt)
|
||||||
print >> fit_file, '%s' % DT_END
|
fit_file.write('%s\n' % DT_END)
|
||||||
|
|
||||||
if fit_file_name != sys.stdout:
|
if fit_file_name != sys.stdout:
|
||||||
fit_file.close()
|
fit_file.close()
|
||||||
|
|
||||||
def generate_atf_binary(bl31_file_name):
|
def generate_atf_binary(bl31_file_name):
|
||||||
with open(bl31_file_name) as bl31_file:
|
with open(bl31_file_name, 'rb') as bl31_file:
|
||||||
bl31 = ELFFile(bl31_file)
|
bl31 = ELFFile(bl31_file)
|
||||||
|
|
||||||
num = bl31.num_segments()
|
num = bl31.num_segments()
|
||||||
|
@ -178,17 +180,17 @@ def get_bl31_segments_info(bl31_file_name):
|
||||||
bl31 = ELFFile(bl31_file)
|
bl31 = ELFFile(bl31_file)
|
||||||
|
|
||||||
num = bl31.num_segments()
|
num = bl31.num_segments()
|
||||||
print 'Number of Segments : %d' % bl31.num_segments()
|
print('Number of Segments : %d' % bl31.num_segments())
|
||||||
for i in range(num):
|
for i in range(num):
|
||||||
print 'Segment %d' % i
|
print('Segment %d' % i)
|
||||||
seg = bl31.get_segment(i)
|
seg = bl31.get_segment(i)
|
||||||
ptype = seg[ELF_SEG_P_TYPE]
|
ptype = seg[ELF_SEG_P_TYPE]
|
||||||
poffset = seg[ELF_SEG_P_OFFSET]
|
poffset = seg[ELF_SEG_P_OFFSET]
|
||||||
pmemsz = seg[ELF_SEG_P_MEMSZ]
|
pmemsz = seg[ELF_SEG_P_MEMSZ]
|
||||||
pfilesz = seg[ELF_SEG_P_FILESZ]
|
pfilesz = seg[ELF_SEG_P_FILESZ]
|
||||||
print 'type: %s\nfilesz: %08x\nmemsz: %08x\noffset: %08x' % (ptype, pfilesz, pmemsz, poffset)
|
print('type: %s\nfilesz: %08x\nmemsz: %08x\noffset: %08x' % (ptype, pfilesz, pmemsz, poffset))
|
||||||
paddr = seg[ELF_SEG_P_PADDR]
|
paddr = seg[ELF_SEG_P_PADDR]
|
||||||
print 'paddr: %08x' % paddr
|
print('paddr: %08x' % paddr)
|
||||||
|
|
||||||
def main():
|
def main():
|
||||||
uboot_elf="./u-boot"
|
uboot_elf="./u-boot"
|
||||||
|
@ -204,7 +206,7 @@ def main():
|
||||||
elif opt == "-b":
|
elif opt == "-b":
|
||||||
bl31_elf=val
|
bl31_elf=val
|
||||||
elif opt == "-h":
|
elif opt == "-h":
|
||||||
print __doc__
|
print(__doc__)
|
||||||
sys.exit(2)
|
sys.exit(2)
|
||||||
|
|
||||||
dtbs = args
|
dtbs = args
|
||||||
|
|
|
@ -832,6 +832,13 @@ config SPL_AM33XX_ENABLE_RTC32K_OSC
|
||||||
Enable access to the AM33xx RTC and select the external 32kHz clock
|
Enable access to the AM33xx RTC and select the external 32kHz clock
|
||||||
source.
|
source.
|
||||||
|
|
||||||
|
config SPL_OPTEE
|
||||||
|
bool "Support OP-TEE Trusted OS"
|
||||||
|
depends on ARM
|
||||||
|
help
|
||||||
|
OP-TEE is an open source Trusted OS which is loaded by SPL.
|
||||||
|
More detail at: https://github.com/OP-TEE/optee_os
|
||||||
|
|
||||||
config TPL
|
config TPL
|
||||||
bool
|
bool
|
||||||
depends on SUPPORT_TPL
|
depends on SUPPORT_TPL
|
||||||
|
|
|
@ -21,6 +21,7 @@ obj-$(CONFIG_$(SPL_TPL_)UBI) += spl_ubi.o
|
||||||
obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o
|
obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o
|
||||||
obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o
|
obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o
|
||||||
obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o
|
obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o
|
||||||
|
obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o
|
||||||
obj-$(CONFIG_$(SPL_TPL_)USB_SUPPORT) += spl_usb.o
|
obj-$(CONFIG_$(SPL_TPL_)USB_SUPPORT) += spl_usb.o
|
||||||
obj-$(CONFIG_$(SPL_TPL_)FAT_SUPPORT) += spl_fat.o
|
obj-$(CONFIG_$(SPL_TPL_)FAT_SUPPORT) += spl_fat.o
|
||||||
obj-$(CONFIG_$(SPL_TPL_)EXT_SUPPORT) += spl_ext.o
|
obj-$(CONFIG_$(SPL_TPL_)EXT_SUPPORT) += spl_ext.o
|
||||||
|
|
|
@ -536,6 +536,13 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
|
||||||
spl_invoke_atf(&spl_image);
|
spl_invoke_atf(&spl_image);
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
|
#if CONFIG_IS_ENABLED(OPTEE)
|
||||||
|
case IH_OS_TEE:
|
||||||
|
debug("Jumping to U-Boot via OP-TEE\n");
|
||||||
|
spl_optee_entry(NULL, NULL, spl_image.fdt_addr,
|
||||||
|
(void *)spl_image.entry_point);
|
||||||
|
break;
|
||||||
|
#endif
|
||||||
#ifdef CONFIG_SPL_OS_BOOT
|
#ifdef CONFIG_SPL_OS_BOOT
|
||||||
case IH_OS_LINUX:
|
case IH_OS_LINUX:
|
||||||
debug("Jumping to Linux\n");
|
debug("Jumping to Linux\n");
|
||||||
|
|
|
@ -0,0 +1,12 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2017 Rockchip Electronic Co.,Ltd
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/linkage.h>
|
||||||
|
#include <asm/assembler.h>
|
||||||
|
|
||||||
|
ENTRY(spl_optee_entry)
|
||||||
|
ldr lr, =CONFIG_SYS_TEXT_BASE
|
||||||
|
mov pc, r3
|
||||||
|
ENDPROC(spl_optee_entry)
|
|
@ -24,6 +24,11 @@
|
||||||
#include <dt-bindings/clock/rk3288-cru.h>
|
#include <dt-bindings/clock/rk3288-cru.h>
|
||||||
#include "designware.h"
|
#include "designware.h"
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
#define DELAY_ENABLE(soc, tx, rx) \
|
||||||
|
(((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
|
||||||
|
((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Platform data for the gmac
|
* Platform data for the gmac
|
||||||
*
|
*
|
||||||
|
@ -286,8 +291,7 @@ static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
|
||||||
RK3228_RXCLK_DLY_ENA_GMAC_MASK |
|
RK3228_RXCLK_DLY_ENA_GMAC_MASK |
|
||||||
RK3228_TXCLK_DLY_ENA_GMAC_MASK,
|
RK3228_TXCLK_DLY_ENA_GMAC_MASK,
|
||||||
RK3228_GMAC_PHY_INTF_SEL_RGMII |
|
RK3228_GMAC_PHY_INTF_SEL_RGMII |
|
||||||
RK3228_RXCLK_DLY_ENA_GMAC_ENABLE |
|
DELAY_ENABLE(RK3228, pdata->tx_delay, pdata->rx_delay));
|
||||||
RK3228_TXCLK_DLY_ENA_GMAC_ENABLE);
|
|
||||||
|
|
||||||
rk_clrsetreg(&grf->mac_con[0],
|
rk_clrsetreg(&grf->mac_con[0],
|
||||||
RK3228_CLK_RX_DL_CFG_GMAC_MASK |
|
RK3228_CLK_RX_DL_CFG_GMAC_MASK |
|
||||||
|
@ -310,8 +314,7 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
|
||||||
RK3288_TXCLK_DLY_ENA_GMAC_MASK |
|
RK3288_TXCLK_DLY_ENA_GMAC_MASK |
|
||||||
RK3288_CLK_RX_DL_CFG_GMAC_MASK |
|
RK3288_CLK_RX_DL_CFG_GMAC_MASK |
|
||||||
RK3288_CLK_TX_DL_CFG_GMAC_MASK,
|
RK3288_CLK_TX_DL_CFG_GMAC_MASK,
|
||||||
RK3288_RXCLK_DLY_ENA_GMAC_ENABLE |
|
DELAY_ENABLE(RK3288, pdata->rx_delay, pdata->tx_delay) |
|
||||||
RK3288_TXCLK_DLY_ENA_GMAC_ENABLE |
|
|
||||||
pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
|
pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
|
||||||
pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
|
pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
|
||||||
}
|
}
|
||||||
|
@ -350,8 +353,7 @@ static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
|
||||||
RK3328_RXCLK_DLY_ENA_GMAC_MASK |
|
RK3328_RXCLK_DLY_ENA_GMAC_MASK |
|
||||||
RK3328_TXCLK_DLY_ENA_GMAC_MASK,
|
RK3328_TXCLK_DLY_ENA_GMAC_MASK,
|
||||||
RK3328_GMAC_PHY_INTF_SEL_RGMII |
|
RK3328_GMAC_PHY_INTF_SEL_RGMII |
|
||||||
RK3328_RXCLK_DLY_ENA_GMAC_MASK |
|
DELAY_ENABLE(RK3328, pdata->tx_delay, pdata->rx_delay));
|
||||||
RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
|
|
||||||
|
|
||||||
rk_clrsetreg(&grf->mac_con[0],
|
rk_clrsetreg(&grf->mac_con[0],
|
||||||
RK3328_CLK_RX_DL_CFG_GMAC_MASK |
|
RK3328_CLK_RX_DL_CFG_GMAC_MASK |
|
||||||
|
@ -392,8 +394,7 @@ static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
|
||||||
RK3368_TXCLK_DLY_ENA_GMAC_MASK |
|
RK3368_TXCLK_DLY_ENA_GMAC_MASK |
|
||||||
RK3368_CLK_RX_DL_CFG_GMAC_MASK |
|
RK3368_CLK_RX_DL_CFG_GMAC_MASK |
|
||||||
RK3368_CLK_TX_DL_CFG_GMAC_MASK,
|
RK3368_CLK_TX_DL_CFG_GMAC_MASK,
|
||||||
RK3368_RXCLK_DLY_ENA_GMAC_ENABLE |
|
DELAY_ENABLE(RK3368, pdata->tx_delay, pdata->rx_delay) |
|
||||||
RK3368_TXCLK_DLY_ENA_GMAC_ENABLE |
|
|
||||||
pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
|
pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
|
||||||
pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
|
pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
|
||||||
}
|
}
|
||||||
|
@ -413,8 +414,7 @@ static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
|
||||||
RK3399_TXCLK_DLY_ENA_GMAC_MASK |
|
RK3399_TXCLK_DLY_ENA_GMAC_MASK |
|
||||||
RK3399_CLK_RX_DL_CFG_GMAC_MASK |
|
RK3399_CLK_RX_DL_CFG_GMAC_MASK |
|
||||||
RK3399_CLK_TX_DL_CFG_GMAC_MASK,
|
RK3399_CLK_TX_DL_CFG_GMAC_MASK,
|
||||||
RK3399_RXCLK_DLY_ENA_GMAC_ENABLE |
|
DELAY_ENABLE(RK3399, pdata->tx_delay, pdata->rx_delay) |
|
||||||
RK3399_TXCLK_DLY_ENA_GMAC_ENABLE |
|
|
||||||
pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
|
pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
|
||||||
pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
|
pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
|
||||||
}
|
}
|
||||||
|
@ -451,40 +451,86 @@ static int gmac_rockchip_probe(struct udevice *dev)
|
||||||
|
|
||||||
switch (eth_pdata->phy_interface) {
|
switch (eth_pdata->phy_interface) {
|
||||||
case PHY_INTERFACE_MODE_RGMII:
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
/*
|
|
||||||
* If the gmac clock is from internal pll, need to set and
|
|
||||||
* check the return value for gmac clock at RGMII mode. If
|
|
||||||
* the gmac clock is from external source, the clock rate
|
|
||||||
* is not set, because of it is bypassed.
|
|
||||||
*/
|
|
||||||
if (!pdata->clock_input) {
|
|
||||||
rate = clk_set_rate(&clk, 125000000);
|
|
||||||
if (rate != 125000000)
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Set to RGMII mode */
|
/* Set to RGMII mode */
|
||||||
if (ops->set_to_rgmii)
|
if (ops->set_to_rgmii)
|
||||||
ops->set_to_rgmii(pdata);
|
ops->set_to_rgmii(pdata);
|
||||||
else
|
else
|
||||||
return -EPERM;
|
return -EPERM;
|
||||||
|
|
||||||
break;
|
/*
|
||||||
case PHY_INTERFACE_MODE_RMII:
|
* If the gmac clock is from internal pll, need to set and
|
||||||
/* The commet is the same as RGMII mode */
|
* check the return value for gmac clock at RGMII mode. If
|
||||||
|
* the gmac clock is from external source, the clock rate
|
||||||
|
* is not set, because of it is bypassed.
|
||||||
|
*/
|
||||||
|
|
||||||
if (!pdata->clock_input) {
|
if (!pdata->clock_input) {
|
||||||
rate = clk_set_rate(&clk, 50000000);
|
rate = clk_set_rate(&clk, 125000000);
|
||||||
if (rate != 50000000)
|
if (rate != 125000000)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
|
/* Set to RGMII mode */
|
||||||
|
if (ops->set_to_rgmii) {
|
||||||
|
pdata->tx_delay = 0;
|
||||||
|
pdata->rx_delay = 0;
|
||||||
|
ops->set_to_rgmii(pdata);
|
||||||
|
} else
|
||||||
|
return -EPERM;
|
||||||
|
|
||||||
|
if (!pdata->clock_input) {
|
||||||
|
rate = clk_set_rate(&clk, 125000000);
|
||||||
|
if (rate != 125000000)
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case PHY_INTERFACE_MODE_RMII:
|
||||||
/* Set to RMII mode */
|
/* Set to RMII mode */
|
||||||
if (ops->set_to_rmii)
|
if (ops->set_to_rmii)
|
||||||
ops->set_to_rmii(pdata);
|
ops->set_to_rmii(pdata);
|
||||||
else
|
else
|
||||||
return -EPERM;
|
return -EPERM;
|
||||||
|
|
||||||
|
if (!pdata->clock_input) {
|
||||||
|
rate = clk_set_rate(&clk, 50000000);
|
||||||
|
if (rate != 50000000)
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
/* Set to RGMII_RXID mode */
|
||||||
|
if (ops->set_to_rgmii) {
|
||||||
|
pdata->tx_delay = 0;
|
||||||
|
ops->set_to_rgmii(pdata);
|
||||||
|
} else
|
||||||
|
return -EPERM;
|
||||||
|
|
||||||
|
if (!pdata->clock_input) {
|
||||||
|
rate = clk_set_rate(&clk, 125000000);
|
||||||
|
if (rate != 125000000)
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
/* Set to RGMII_TXID mode */
|
||||||
|
if (ops->set_to_rgmii) {
|
||||||
|
pdata->rx_delay = 0;
|
||||||
|
ops->set_to_rgmii(pdata);
|
||||||
|
} else
|
||||||
|
return -EPERM;
|
||||||
|
|
||||||
|
if (!pdata->clock_input) {
|
||||||
|
rate = clk_set_rate(&clk, 125000000);
|
||||||
|
if (rate != 125000000)
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
debug("NO interface defined!\n");
|
debug("NO interface defined!\n");
|
||||||
return -ENXIO;
|
return -ENXIO;
|
||||||
|
|
|
@ -288,6 +288,19 @@ int spl_mmc_load_image(struct spl_image_info *spl_image,
|
||||||
*/
|
*/
|
||||||
void spl_invoke_atf(struct spl_image_info *spl_image);
|
void spl_invoke_atf(struct spl_image_info *spl_image);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* spl_optee_entry - entry function for optee
|
||||||
|
*
|
||||||
|
* args defind in op-tee project
|
||||||
|
* https://github.com/OP-TEE/optee_os/
|
||||||
|
* core/arch/arm/kernel/generic_entry_a32.S
|
||||||
|
* @arg0: pagestore
|
||||||
|
* @arg1: (ARMv7 standard bootarg #1)
|
||||||
|
* @arg2: device tree address, (ARMv7 standard bootarg #2)
|
||||||
|
* @arg3: non-secure entry address (ARMv7 bootarg #0)
|
||||||
|
*/
|
||||||
|
void spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* board_return_to_bootrom - allow for boards to continue with the boot ROM
|
* board_return_to_bootrom - allow for boards to continue with the boot ROM
|
||||||
*
|
*
|
||||||
|
|
|
@ -15,8 +15,7 @@ static uint32_t header;
|
||||||
static void rkimage_set_header(void *buf, struct stat *sbuf, int ifd,
|
static void rkimage_set_header(void *buf, struct stat *sbuf, int ifd,
|
||||||
struct image_tool_params *params)
|
struct image_tool_params *params)
|
||||||
{
|
{
|
||||||
memcpy(buf + RK_SPL_HDR_START, rkcommon_get_spl_hdr(params),
|
memcpy(buf, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE);
|
||||||
RK_SPL_HDR_SIZE);
|
|
||||||
|
|
||||||
if (rkcommon_need_rc4_spl(params))
|
if (rkcommon_need_rc4_spl(params))
|
||||||
rkcommon_rc4_encode_spl(buf, 4, params->file_size);
|
rkcommon_rc4_encode_spl(buf, 4, params->file_size);
|
||||||
|
@ -36,7 +35,7 @@ static int rkimage_check_image_type(uint8_t type)
|
||||||
U_BOOT_IMAGE_TYPE(
|
U_BOOT_IMAGE_TYPE(
|
||||||
rkimage,
|
rkimage,
|
||||||
"Rockchip Boot Image support",
|
"Rockchip Boot Image support",
|
||||||
4,
|
0,
|
||||||
&header,
|
&header,
|
||||||
rkcommon_check_params,
|
rkcommon_check_params,
|
||||||
NULL,
|
NULL,
|
||||||
|
|
Loading…
Reference in New Issue