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https://github.com/brain-hackers/u-boot-brain
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video: omap: use BIT() and GENMASK() macros
Use the standard BIT() and GENMASK() macros for bitfield definitions. Signed-off-by: Dario Binacchi <dariobin@libero.it>
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@ -27,11 +27,11 @@
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/* LCD Control Register */
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#define LCD_CLK_DIVISOR(x) ((x) << 8)
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#define LCD_RASTER_MODE 0x01
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#define LCD_RASTER_MODE BIT(0)
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/* LCD Clock Enable Register */
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#define LCD_CORECLKEN (0x01 << 0)
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#define LCD_LIDDCLKEN (0x01 << 1)
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#define LCD_DMACLKEN (0x01 << 2)
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#define LCD_CORECLKEN BIT(0)
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#define LCD_LIDDCLKEN BIT(1)
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#define LCD_DMACLKEN BIT(2)
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/* LCD DMA Control Register */
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#define LCD_DMA_BURST_SIZE(x) ((x) << 4)
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#define LCD_DMA_BURST_1 0x0
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@ -40,28 +40,28 @@
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#define LCD_DMA_BURST_8 0x3
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#define LCD_DMA_BURST_16 0x4
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/* LCD Timing_0 Register */
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#define LCD_HBPLSB(x) ((((x)-1) & 0xFF) << 24)
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#define LCD_HFPLSB(x) ((((x)-1) & 0xFF) << 16)
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#define LCD_HSWLSB(x) ((((x)-1) & 0x3F) << 10)
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#define LCD_HORLSB(x) (((((x) >> 4)-1) & 0x3F) << 4)
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#define LCD_HBPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 24)
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#define LCD_HFPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 16)
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#define LCD_HSWLSB(x) ((((x) - 1) & GENMASK(5, 0)) << 10)
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#define LCD_HORLSB(x) (((((x) >> 4) - 1) & GENMASK(5, 0)) << 4)
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#define LCD_HORMSB(x) (((((x) >> 4)-1) & 0x40) >> 4)
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/* LCD Timing_1 Register */
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#define LCD_VBP(x) ((x) << 24)
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#define LCD_VFP(x) ((x) << 16)
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#define LCD_VSW(x) (((x)-1) << 10)
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#define LCD_VERLSB(x) (((x)-1) & 0x3FF)
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#define LCD_VERLSB(x) (((x) - 1) & GENMASK(9, 0))
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/* LCD Timing_2 Register */
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#define LCD_HSWMSB(x) ((((x)-1) & 0x3C0) << 21)
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#define LCD_VERMSB(x) ((((x)-1) & 0x400) << 16)
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#define LCD_HBPMSB(x) ((((x)-1) & 0x300) >> 4)
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#define LCD_HFPMSB(x) ((((x)-1) & 0x300) >> 8)
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#define LCD_INVMASK(x) ((x) & 0x3F00000)
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#define LCD_HSWMSB(x) ((((x) - 1) & GENMASK(9, 6)) << 21)
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#define LCD_VERMSB(x) ((((x) - 1) & BIT(10)) << 16)
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#define LCD_HBPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 4)
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#define LCD_HFPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 8)
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#define LCD_INVMASK(x) ((x) & GENMASK(25, 20))
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/* LCD Raster Ctrl Register */
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#define LCD_TFT_24BPP_MODE (1 << 25)
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#define LCD_TFT_24BPP_UNPACK (1 << 26)
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#define LCD_TFT_24BPP_MODE BIT(25)
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#define LCD_TFT_24BPP_UNPACK BIT(26)
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#define LCD_PALMODE_RAWDATA (0x02 << 20)
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#define LCD_TFT_MODE (0x01 << 7)
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#define LCD_RASTER_ENABLE (0x01 << 0)
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#define LCD_TFT_MODE BIT(7)
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#define LCD_RASTER_ENABLE BIT(0)
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/* Macro definitions */
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@ -7,7 +7,7 @@
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#ifndef AM335X_FB_H
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#define AM335X_FB_H
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#define HSVS_CONTROL (0x01 << 25) /*
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#define HSVS_CONTROL BIT(25) /*
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* 0 = lcd_lp and lcd_fp are driven on
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* opposite edges of pixel clock than
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* the lcd_pixel_o
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@ -17,7 +17,7 @@
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* Matrix displays the edge timing is
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* fixed
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*/
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#define HSVS_RISEFALL (0x01 << 24) /*
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#define HSVS_RISEFALL BIT(24) /*
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* 0 = lcd_lp and lcd_fp are driven on
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* the rising edge of pixel clock (bit
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* 25 must be set to 1)
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@ -25,19 +25,19 @@
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* the falling edge of pixel clock (bit
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* 25 must be set to 1)
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*/
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#define DE_INVERT (0x01 << 23) /*
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#define DE_INVERT BIT(23) /*
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* 0 = DE is low-active
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* 1 = DE is high-active
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*/
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#define PXCLK_INVERT (0x01 << 22) /*
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#define PXCLK_INVERT BIT(22) /*
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* 0 = pix-clk is high-active
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* 1 = pic-clk is low-active
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*/
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#define HSYNC_INVERT (0x01 << 21) /*
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#define HSYNC_INVERT BIT(21) /*
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* 0 = HSYNC is active high
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* 1 = HSYNC is avtive low
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*/
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#define VSYNC_INVERT (0x01 << 20) /*
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#define VSYNC_INVERT BIT(20) /*
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* 0 = VSYNC is active high
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* 1 = VSYNC is active low
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*/
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