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ARM: remove cm4008 and cm41xx board support 

These are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Greg Ungerer <greg.ungerer@opengear.com>
Acked-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Masahiro Yamada 2015-02-24 11:45:07 +09:00 committed by Tom Rini
parent 346cfba4f0
commit a2f39e830e
30 changed files with 2 additions and 2168 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/Kconfig
View File

@ -88,14 +88,6 @@ config TARGET_SCB9328
bool "Support scb9328"
select CPU_ARM920T
config TARGET_CM4008
bool "Support cm4008"
select CPU_ARM920T
config TARGET_CM41XX
bool "Support cm41xx"
select CPU_ARM920T
config TARGET_VCMA9
bool "Support VCMA9"
select CPU_ARM920T
@ -769,8 +761,6 @@ source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
source "board/cm4008/Kconfig"
source "board/cm41xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"

1
arch/arm/cpu/arm920t/Makefile
View File

@ -13,5 +13,4 @@ obj-$(CONFIG_USE_IRQ) += interrupts.o
obj-$(if $(filter a320,$(SOC)),y) += a320/
obj-$(CONFIG_EP93XX) += ep93xx/
obj-$(CONFIG_IMX) += imx/
obj-$(CONFIG_KS8695) += ks8695/
obj-$(CONFIG_S3C24X0) += s3c24x0/

9
arch/arm/cpu/arm920t/ks8695/Makefile
View File

@ -1,9 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = lowlevel_init.o
obj-y += timer.o

189
arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
View File

@ -1,189 +0,0 @@
/*
* lowlevel_init.S - basic hardware initialization for the KS8695 CPU
*
* Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <version.h>
#include <asm/arch/platform.h>
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*
*************************************************************************
*
* Handy dandy macros
*
*************************************************************************
*/
/* Delay a bit */
.macro DELAY_FOR cycles, reg0
ldr \reg0, =\cycles
subs \reg0, \reg0, #1
subne pc, pc, #0xc
.endm
/*
*************************************************************************
*
* Some local storage.
*
*************************************************************************
*/
/* Should we boot with an interactive console or not */
.globl serial_console
/*
*************************************************************************
*
* Raw hardware initialization code. The important thing is to get
* SDRAM setup and running. We do some other basic things here too,
* like getting the PLL set for high speed, and init the LEDs.
*
*************************************************************************
*/
.globl lowlevel_init
lowlevel_init:
#if DEBUG
/*
* enable UART for early debug trace
*/
ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
mov r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
str r2, [r1]
ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
mov r2, #KS8695_UART_LINEC_WLEN8
str r2, [r1] /* 8 data bits, no parity, 1 stop */
ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
mov r2, #0x41
str r2, [r1] /* write 'A' */
#endif
#if DEBUG
ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
mov r2, #0x42
str r2, [r1]
#endif
/*
* remap the memory and flash regions. we want to end up with
* ram from address 0, and flash at 32MB.
*/
ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
ldr r2, =0xbfc00040
str r2, [r1] /* large flash map */
ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */
highflash:
ldr r2, =0x8fe00040
str r2, [r1] /* remap flash range */
/*
* remap the second select region to the 4MB immediately after
* the first region. This way if you have a larger flash (say 8Mb)
* then you can have it all mapped nicely. Has no effect if you
* only have a 4Mb or smaller flash.
*/
ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
ldr r2, =0x9fe40040
str r2, [r1] /* remap flash2 region, contiguous */
ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
ldr r2, =0x30000005
str r2, [r1] /* enable both flash selects */
#ifdef CONFIG_CM41xx
/*
* map the second flash chip, using the external IO lines.
*/
ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
ldr r2, =0xafe80b6d
str r2, [r1] /* remap io0 region, contiguous */
ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
ldr r2, =0xbfec0b6d
str r2, [r1] /* remap io1 region, contiguous */
ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
ldr r2, =0x30050005
str r2, [r1] /* enable second flash */
#endif
/*
* before relocating, we have to setup RAM timing
*/
ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
#if (PHYS_SDRAM_1_SIZE == 0x02000000)
ldr r2, =0x7fc0000e /* 32MB */
#else
ldr r2, =0x3fc0000e /* 16MB */
#endif
str r2, [r1] /* configure sdram bank0 setup */
ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
mov r2, #0
str r2, [r1] /* configure sdram bank1 setup */
ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
ldr r2, =0x0000000a
str r2, [r1] /* set RAS/CAS timing */
ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
ldr r2, =0x00030000
str r2, [r1] /* send NOP command */
DELAY_FOR 0x100, r0
ldr r2, =0x00010000
str r2, [r1] /* send PRECHARGE-ALL */
DELAY_FOR 0x100, r0
ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
ldr r2, =0x00000020
str r2, [r1] /* set for fast refresh */
DELAY_FOR 0x100, r0
ldr r2, =0x00000190
str r2, [r1] /* set normal refresh timing */
ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
ldr r2, =0x00020033
str r2, [r1] /* send mode command */
DELAY_FOR 0x100, r0
ldr r2, =0x01f00000
str r2, [r1] /* enable sdram fifos */
/*
* set pll to top speed
*/
ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
mov r2, #0
str r2, [r1] /* set pll clock to 166MHz */
ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
ldr r2, [r1] /* Get switch ctrl0 register */
and r2, r2, #0x0fc00000 /* Mask out LED control bits */
orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */
str r2, [r1]
#ifdef CONFIG_CM4008
ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
ldr r2, =0x0000fe30
str r2, [r1] /* enable LED's as outputs */
ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
ldr r2, =0x0000fe20
str r2, [r1] /* turn on power LED */
#endif
#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
ldr r2, [r1] /* get current GPIO input data */
tst r2, #0x8 /* check if "erase" depressed */
beq nobutton
mov r2, #0 /* be quiet on boot, no console */
ldr r1, =serial_console
str r2, [r1]
nobutton:
#endif
add lr, lr, #0x02000000 /* flash is now mapped high */
add ip, ip, #0x02000000 /* this is a hack */
mov pc, lr /* all done, return */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

77
arch/arm/cpu/arm920t/ks8695/timer.c
View File

@ -1,77 +0,0 @@
/*
* (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/platform.h>
/*
* Initial timer set constants. Nothing complicated, just set for a 1ms
* tick.
*/
#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1)
#define TIMER_COUNT (TIMER_INTERVAL / 2)
#define TIMER_PULSE TIMER_COUNT
/*
* Handy KS8695 register access functions.
*/
#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a)))
#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
ulong timer_ticks;
int timer_init (void)
{
/* Set the hadware timer for 1ms */
ks8695_write(KS8695_TIMER1, TIMER_COUNT);
ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
ks8695_write(KS8695_TIMER_CTRL, 0x2);
timer_ticks = 0;
return 0;
}
ulong get_timer_masked(void)
{
/* Check for timer wrap */
if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
/* Clear interrupt condition */
ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
timer_ticks++;
}
return timer_ticks;
}
ulong get_timer(ulong base)
{
return (get_timer_masked() - base);
}
void __udelay(ulong usec)
{
ulong start = get_timer_masked();
ulong end;
/* Only 1ms resolution :-( */
end = usec / 1000;
while (get_timer(start) < end)
;
}
void reset_cpu (ulong ignored)
{
ulong tc;
/* Set timer0 to watchdog, and let it timeout */
tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
ks8695_write(KS8695_TIMER_CTRL, tc);
ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
/* Should only wait here till watchdog resets */
for (;;)
;
}

294
arch/arm/include/asm/arch-ks8695/platform.h
View File

@ -1,294 +0,0 @@
/*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __address_h
#define __address_h 1
#define KS8695_SDRAM_START 0x00000000
#define KS8695_SDRAM_SIZE 0x01000000
#define KS8695_MEM_SIZE KS8695_SDRAM_SIZE
#define KS8695_MEM_START KS8695_SDRAM_START
#define KS8695_PCMCIA_IO_BASE 0x03800000
#define KS8695_PCMCIA_IO_SIZE 0x00040000
#define KS8695_IO_BASE 0x03FF0000
#define KS8695_IO_SIZE 0x00010000
#define KS8695_SYSTEN_CONFIG 0x00
#define KS8695_SYSTEN_BUS_CLOCK 0x04
#define KS8695_FLASH_START 0x02800000
#define KS8695_FLASH_SIZE 0x00400000
/*i/o control registers offset difinitions*/
#define KS8695_IO_CTRL0 0x4000
#define KS8695_IO_CTRL1 0x4004
#define KS8695_IO_CTRL2 0x4008
#define KS8695_IO_CTRL3 0x400C
/*memory control registers offset difinitions*/
#define KS8695_MEM_CTRL0 0x4010
#define KS8695_MEM_CTRL1 0x4014
#define KS8695_MEM_CTRL2 0x4018
#define KS8695_MEM_CTRL3 0x401C
#define KS8695_MEM_GENERAL 0x4020
#define KS8695_SDRAM_CTRL0 0x4030
#define KS8695_SDRAM_CTRL1 0x4034
#define KS8695_SDRAM_GENERAL 0x4038
#define KS8695_SDRAM_BUFFER 0x403C
#define KS8695_SDRAM_REFRESH 0x4040
/*WAN control registers offset difinitions*/
#define KS8695_WAN_DMA_TX 0x6000
#define KS8695_WAN_DMA_RX 0x6004
#define KS8695_WAN_DMA_TX_START 0x6008
#define KS8695_WAN_DMA_RX_START 0x600C
#define KS8695_WAN_TX_LIST 0x6010
#define KS8695_WAN_RX_LIST 0x6014
#define KS8695_WAN_MAC_LOW 0x6018
#define KS8695_WAN_MAC_HIGH 0x601C
#define KS8695_WAN_MAC_ELOW 0x6080
#define KS8695_WAN_MAC_EHIGH 0x6084
/*LAN control registers offset difinitions*/
#define KS8695_LAN_DMA_TX 0x8000
#define KS8695_LAN_DMA_RX 0x8004
#define KS8695_LAN_DMA_TX_START 0x8008
#define KS8695_LAN_DMA_RX_START 0x800C
#define KS8695_LAN_TX_LIST 0x8010
#define KS8695_LAN_RX_LIST 0x8014
#define KS8695_LAN_MAC_LOW 0x8018
#define KS8695_LAN_MAC_HIGH 0x801C
#define KS8695_LAN_MAC_ELOW 0X8080
#define KS8695_LAN_MAC_EHIGH 0X8084
/*HPNA control registers offset difinitions*/
#define KS8695_HPNA_DMA_TX 0xA000
#define KS8695_HPNA_DMA_RX 0xA004
#define KS8695_HPNA_DMA_TX_START 0xA008
#define KS8695_HPNA_DMA_RX_START 0xA00C
#define KS8695_HPNA_TX_LIST 0xA010
#define KS8695_HPNA_RX_LIST 0xA014
#define KS8695_HPNA_MAC_LOW 0xA018
#define KS8695_HPNA_MAC_HIGH 0xA01C
#define KS8695_HPNA_MAC_ELOW 0xA080
#define KS8695_HPNA_MAC_EHIGH 0xA084
/*UART control registers offset difinitions*/
#define KS8695_UART_RX_BUFFER 0xE000
#define KS8695_UART_TX_HOLDING 0xE004
#define KS8695_UART_FIFO_CTRL 0xE008
#define KS8695_UART_FIFO_TRIG01 0x00
#define KS8695_UART_FIFO_TRIG04 0x80
#define KS8695_UART_FIFO_TXRST 0x03
#define KS8695_UART_FIFO_RXRST 0x02
#define KS8695_UART_FIFO_FEN 0x01
#define KS8695_UART_LINE_CTRL 0xE00C
#define KS8695_UART_LINEC_BRK 0x40
#define KS8695_UART_LINEC_EPS 0x10
#define KS8695_UART_LINEC_PEN 0x08
#define KS8695_UART_LINEC_STP2 0x04
#define KS8695_UART_LINEC_WLEN8 0x03
#define KS8695_UART_LINEC_WLEN7 0x02
#define KS8695_UART_LINEC_WLEN6 0x01
#define KS8695_UART_LINEC_WLEN5 0x00
#define KS8695_UART_MODEM_CTRL 0xE010
#define KS8695_UART_MODEMC_RTS 0x02
#define KS8695_UART_MODEMC_DTR 0x01
#define KS8695_UART_LINE_STATUS 0xE014
#define KS8695_UART_LINES_TXFE 0x20
#define KS8695_UART_LINES_BE 0x10
#define KS8695_UART_LINES_FE 0x08
#define KS8695_UART_LINES_PE 0x04
#define KS8695_UART_LINES_OE 0x02
#define KS8695_UART_LINES_RXFE 0x01
#define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE)
#define KS8695_UART_MODEM_STATUS 0xE018
#define KS8695_UART_MODEM_DCD 0x80
#define KS8695_UART_MODEM_DSR 0x20
#define KS8695_UART_MODEM_CTS 0x10
#define KS8695_UART_MODEM_DDCD 0x08
#define KS8695_UART_MODEM_DDSR 0x02
#define KS8695_UART_MODEM_DCTS 0x01
#define UART8695_MODEM_ANY 0xFF
#define KS8695_UART_DIVISOR 0xE01C
#define KS8695_UART_STATUS 0xE020
/*Interrupt controlller registers offset difinitions*/
#define KS8695_INT_CONTL 0xE200
#define KS8695_INT_ENABLE 0xE204
#define KS8695_INT_ENABLE_MODEM 0x0800
#define KS8695_INT_ENABLE_ERR 0x0400
#define KS8695_INT_ENABLE_RX 0x0200
#define KS8695_INT_ENABLE_TX 0x0100
#define KS8695_INT_STATUS 0xE208
#define KS8695_INT_WAN_PRIORITY 0xE20C
#define KS8695_INT_HPNA_PRIORITY 0xE210
#define KS8695_INT_LAN_PRIORITY 0xE214
#define KS8695_INT_TIMER_PRIORITY 0xE218
#define KS8695_INT_UART_PRIORITY 0xE21C
#define KS8695_INT_EXT_PRIORITY 0xE220
#define KS8695_INT_CHAN_PRIORITY 0xE224
#define KS8695_INT_BUSERROR_PRO 0xE228
#define KS8695_INT_MASK_STATUS 0xE22C
#define KS8695_FIQ_PEND_PRIORITY 0xE230
#define KS8695_IRQ_PEND_PRIORITY 0xE234
/*timer registers offset difinitions*/
#define KS8695_TIMER_CTRL 0xE400
#define KS8695_TIMER1 0xE404
#define KS8695_TIMER0 0xE408
#define KS8695_TIMER1_PCOUNT 0xE40C
#define KS8695_TIMER0_PCOUNT 0xE410
/*GPIO registers offset difinitions*/
#define KS8695_GPIO_MODE 0xE600
#define KS8695_GPIO_CTRL 0xE604
#define KS8695_GPIO_DATA 0xE608
/*SWITCH registers offset difinitions*/
#define KS8695_SWITCH_CTRL0 0xE800
#define KS8695_SWITCH_CTRL1 0xE804
#define KS8695_SWITCH_PORT1 0xE808
#define KS8695_SWITCH_PORT2 0xE80C
#define KS8695_SWITCH_PORT3 0xE810
#define KS8695_SWITCH_PORT4 0xE814
#define KS8695_SWITCH_PORT5 0xE818
#define KS8695_SWITCH_AUTO0 0xE81C
#define KS8695_SWITCH_AUTO1 0xE820
#define KS8695_SWITCH_LUE_CTRL 0xE824
#define KS8695_SWITCH_LUE_HIGH 0xE828
#define KS8695_SWITCH_LUE_LOW 0xE82C
#define KS8695_SWITCH_ADVANCED 0xE830
#define KS8695_SWITCH_LPPM12 0xE874
#define KS8695_SWITCH_LPPM34 0xE878
/*host communication registers difinitions*/
#define KS8695_DSCP_HIGH 0xE834
#define KS8695_DSCP_LOW 0xE838
#define KS8695_SWITCH_MAC_HIGH 0xE83C
#define KS8695_SWITCH_MAC_LOW 0xE840
/*miscellaneours registers difinitions*/
#define KS8695_MANAGE_COUNTER 0xE844
#define KS8695_MANAGE_DATA 0xE848
#define KS8695_LAN12_POWERMAGR 0xE84C
#define KS8695_LAN34_POWERMAGR 0xE850
#define KS8695_DEVICE_ID 0xEA00
#define KS8695_REVISION_ID 0xEA04
#define KS8695_MISC_CONTROL 0xEA08
#define KS8695_WAN_CONTROL 0xEA0C
#define KS8695_WAN_POWERMAGR 0xEA10
#define KS8695_WAN_PHY_CONTROL 0xEA14
#define KS8695_WAN_PHY_STATUS 0xEA18
/* bus clock definitions*/
#define KS8695_BUS_CLOCK_125MHZ 0x0
#define KS8695_BUS_CLOCK_100MHZ 0x1
#define KS8695_BUS_CLOCK_62MHZ 0x2
#define KS8695_BUS_CLOCK_50MHZ 0x3
#define KS8695_BUS_CLOCK_41MHZ 0x4
#define KS8695_BUS_CLOCK_33MHZ 0x5
#define KS8695_BUS_CLOCK_31MHZ 0x6
#define KS8695_BUS_CLOCK_25MHZ 0x7
/* -------------------------------------------------------------------------------
* definations for IRQ
* -------------------------------------------------------------------------------*/
#define KS8695_INT_EXT_INT0 2
#define KS8695_INT_EXT_INT1 3
#define KS8695_INT_EXT_INT2 4
#define KS8695_INT_EXT_INT3 5
#define KS8695_INT_TIMERINT0 6
#define KS8695_INT_TIMERINT1 7
#define KS8695_INT_UART_TX 8
#define KS8695_INT_UART_RX 9
#define KS8695_INT_UART_LINE_ERR 10
#define KS8695_INT_UART_MODEMS 11
#define KS8695_INT_LAN_STOP_RX 12
#define KS8695_INT_LAN_STOP_TX 13
#define KS8695_INT_LAN_BUF_RX_STATUS 14
#define KS8695_INT_LAN_BUF_TX_STATUS 15
#define KS8695_INT_LAN_RX_STATUS 16
#define KS8695_INT_LAN_TX_STATUS 17
#define KS8695_INT_HPAN_STOP_RX 18
#define KS8695_INT_HPNA_STOP_TX 19
#define KS8695_INT_HPNA_BUF_RX_STATUS 20
#define KS8695_INT_HPNA_BUF_TX_STATUS 21
#define KS8695_INT_HPNA_RX_STATUS 22
#define KS8695_INT_HPNA_TX_STATUS 23
#define KS8695_INT_BUS_ERROR 24
#define KS8695_INT_WAN_STOP_RX 25
#define KS8695_INT_WAN_STOP_TX 26
#define KS8695_INT_WAN_BUF_RX_STATUS 27
#define KS8695_INT_WAN_BUF_TX_STATUS 28
#define KS8695_INT_WAN_RX_STATUS 29
#define KS8695_INT_WAN_TX_STATUS 30
#define KS8695_INT_UART KS8695_INT_UART_TX
/* -------------------------------------------------------------------------------
* Interrupt bit positions
*
* -------------------------------------------------------------------------------
*/
#define KS8695_INTMASK_EXT_INT0 ( 1 << KS8695_INT_EXT_INT0 )
#define KS8695_INTMASK_EXT_INT1 ( 1 << KS8695_INT_EXT_INT1 )
#define KS8695_INTMASK_EXT_INT2 ( 1 << KS8695_INT_EXT_INT2 )
#define KS8695_INTMASK_EXT_INT3 ( 1 << KS8695_INT_EXT_INT3 )
#define KS8695_INTMASK_TIMERINT0 ( 1 << KS8695_INT_TIMERINT0 )
#define KS8695_INTMASK_TIMERINT1 ( 1 << KS8695_INT_TIMERINT1 )
#define KS8695_INTMASK_UART_TX ( 1 << KS8695_INT_UART_TX )
#define KS8695_INTMASK_UART_RX ( 1 << KS8695_INT_UART_RX )
#define KS8695_INTMASK_UART_LINE_ERR ( 1 << KS8695_INT_UART_LINE_ERR )
#define KS8695_INTMASK_UART_MODEMS ( 1 << KS8695_INT_UART_MODEMS )
#define KS8695_INTMASK_LAN_STOP_RX ( 1 << KS8695_INT_LAN_STOP_RX )
#define KS8695_INTMASK_LAN_STOP_TX ( 1 << KS8695_INT_LAN_STOP_TX )
#define KS8695_INTMASK_LAN_BUF_RX_STATUS ( 1 << KS8695_INT_LAN_BUF_RX_STATUS )
#define KS8695_INTMASK_LAN_BUF_TX_STATUS ( 1 << KS8695_INT_LAN_BUF_TX_STATUS )
#define KS8695_INTMASK_LAN_RX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
#define KS8695_INTMASK_LAN_TX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
#define KS8695_INTMASK_HPAN_STOP_RX ( 1 << KS8695_INT_HPAN_STOP_RX )
#define KS8695_INTMASK_HPNA_STOP_TX ( 1 << KS8695_INT_HPNA_STOP_TX )
#define KS8695_INTMASK_HPNA_BUF_RX_STATUS ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS )
#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS
#define KS8695_INTMASK_HPNA_RX_STATUS ( 1 << KS8695_INT_HPNA_RX_STATUS )
#define KS8695_INTMASK_HPNA_TX_STATUS ( 1 << KS8695_INT_HPNA_TX_STATUS )
#define KS8695_INTMASK_BUS_ERROR ( 1 << KS8695_INT_BUS_ERROR )
#define KS8695_INTMASK_WAN_STOP_RX ( 1 << KS8695_INT_WAN_STOP_RX )
#define KS8695_INTMASK_WAN_STOP_TX ( 1 << KS8695_INT_WAN_STOP_TX )
#define KS8695_INTMASK_WAN_BUF_RX_STATUS ( 1 << KS8695_INT_WAN_BUF_RX_STATUS )
#define KS8695_INTMASK_WAN_BUF_TX_STATUS ( 1 << KS8695_INT_WAN_BUF_TX_STATUS )
#define KS8695_INTMASK_WAN_RX_STATUS ( 1 << KS8695_INT_WAN_RX_STATUS )
#define KS8695_INTMASK_WAN_TX_STATUS ( 1 << KS8695_INT_WAN_TX_STATUS )
#define KS8695_SC_VALID_INT 0xFFFFFFFF
#define MAXIRQNUM 31
/*
* Timer definitions
*
* Use timer 1 & 2
* (both run at 25MHz).
*
*/
#define TICKS_PER_uSEC 25
#define mSEC_1 1000
#define mSEC_10 (mSEC_1 * 10)
#endif
/* END */

12
board/cm4008/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_CM4008
config SYS_BOARD
default "cm4008"
config SYS_SOC
default "ks8695"
config SYS_CONFIG_NAME
default "cm4008"
endif

6
board/cm4008/MAINTAINERS
View File

@ -1,6 +0,0 @@
CM4008 BOARD
M: Greg Ungerer <greg.ungerer@opengear.com>
S: Maintained
F: board/cm4008/
F: include/configs/cm4008.h
F: configs/cm4008_defconfig

8
board/cm4008/Makefile
View File

@ -1,8 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := cm4008.o flash.o

88
board/cm4008/cm4008.c
View File

@ -1,88 +0,0 @@
/*
* (C) Copyright 2005
* Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
*
* (C) Copyright 2002
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/platform.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
int env_flash_cmdline (void)
{
char *sp = (char *) 0x0201c020;
char *ep;
int len;
/* Check if "erase" push button is depressed */
if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
printf("### Entering network recovery mode...\n");
setenv("bootargs", "console=ttyAM0,115200 mem=16M initrd=0x400000,6M root=/dev/ram0");
setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
setenv("bootdelay", "2");
return 0;
}
/* Check for flash based kernel boot args to use as default */
for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
;
if ((len > 0) && (len <1024))
setenv("bootargs", sp);
return 0;
}
int board_late_init (void)
{
return 0;
}
int board_eth_init(bd_t *bis)
{
return ks8695_eth_initialize();
}
int board_init (void)
{
/* arch number of CM4008 */
gd->bd->bi_arch_number = 624;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
/* power down all but port 0 on the switch */
ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
return 0;
}
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return (0);
}

1
board/cm4008/config.mk
View File

@ -1 +0,0 @@
CONFIG_SYS_TEXT_BASE = 0x00f00000

395
board/cm4008/flash.c
View File

@ -1,395 +0,0 @@
/*
* (C) Copyright 2005
* Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
*
* (C) Copyright 2001
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/byteorder/swab.h>
#include <asm/sections.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
#define mb() __asm__ __volatile__ ("" : : : "memory")
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
static int write_data (flash_info_t * info, ulong dest, unsigned char data);
static void flash_get_offsets (ulong base, flash_info_t * info);
void inline spin_wheel (void);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
int i;
ulong size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
switch (i) {
case 0:
flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
break;
case 1:
/* ignore for now */
flash_info[i].flash_id = FLASH_UNKNOWN;
break;
default:
panic ("configured too many flash banks!\n");
break;
}
size += flash_info[i].size;
}
/* Protect monitor and environment sectors
*/
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
&flash_info[0]);
return size;
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN)
return;
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
info->protect[i] = 0;
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_INTEL:
printf ("INTEL ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F128J3A:
printf ("28F128J3A\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
}
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
{
volatile unsigned char value;
/* Write auto select command: read Manufacturer ID */
addr[0x5555] = 0xAA;
addr[0x2AAA] = 0x55;
addr[0x5555] = 0x90;
mb ();
value = addr[0];
switch (value) {
case (unsigned char)INTEL_MANUFACT:
info->flash_id = FLASH_MAN_INTEL;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
addr[0] = 0xFF; /* restore read mode */
return (0); /* no or unknown flash */
}
mb ();
value = addr[2]; /* device ID */
switch (value) {
case (unsigned char)INTEL_ID_28F640J3A:
info->flash_id += FLASH_28F640J3A;
info->sector_count = 64;
info->size = 0x00800000;
break; /* => 8 MB */
case (unsigned char)INTEL_ID_28F128J3A:
info->flash_id += FLASH_28F128J3A;
info->sector_count = 128;
info->size = 0x01000000;
break; /* => 16 MB */
default:
info->flash_id = FLASH_UNKNOWN;
break;
}
if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
addr[0] = 0xFF; /* restore read mode */
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int prot, sect;
ulong type;
int rcode = 0;
ulong start;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
type = (info->flash_id & FLASH_VENDMASK);
if ((type != FLASH_MAN_INTEL)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot)
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
else
printf ("\n");
/* Disable interrupts which might cause a timeout here */
disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
volatile unsigned char *addr;
unsigned char status;
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
addr = (volatile unsigned char *) (info->start[sect]);
*addr = 0x50; /* clear status register */
*addr = 0x20; /* erase setup */
*addr = 0xD0; /* erase confirm */
while (((status = *addr) & 0x80) != 0x80) {
if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = 0xB0; /* suspend erase */
*addr = 0xFF; /* reset to read mode */
rcode = 1;
break;
}
}
*addr = 0x50; /* clear status register cmd */
*addr = 0xFF; /* resest to read mode */
printf (" done\n");
}
}
return rcode;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
* 4 - Flash not identified
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp;
unsigned char data;
int count, i, l, rc, port_width;
if (info->flash_id == FLASH_UNKNOWN)
return 4;
wp = addr;
port_width = 1;
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i < port_width && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
if ((rc = write_data (info, wp, data)) != 0) {
return (rc);
}
wp += port_width;
}
/*
* handle word aligned part
*/
count = 0;
while (cnt >= port_width) {
data = 0;
for (i = 0; i < port_width; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_data (info, wp, data)) != 0) {
return (rc);
}
wp += port_width;
cnt -= port_width;
if (count++ > 0x800) {
spin_wheel ();
count = 0;
}
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return (write_data (info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word or halfword to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_data (flash_info_t * info, ulong dest, unsigned char data)
{
volatile unsigned char *addr = (volatile unsigned char *) dest;
ulong status;
ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
printf ("not erased at %08lx (%lx)\n", (ulong) addr,
(ulong) * addr);
return (2);
}
/* Disable interrupts which might cause a timeout here */
disable_interrupts();
*addr = 0x40; /* write setup */
*addr = data;
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & 0x80) != 0x80) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = 0xFF; /* restore read mode */
return (1);
}
}
*addr = 0xFF; /* restore read mode */
return (0);
}
void inline spin_wheel (void)
{
static int p = 0;
static char w[] = "\\/-";
printf ("\010%c", w[p]);
(++p == 3) ? (p = 0) : 0;
}

12
board/cm41xx/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_CM41XX
config SYS_BOARD
default "cm41xx"
config SYS_SOC
default "ks8695"
config SYS_CONFIG_NAME
default "cm41xx"
endif

6
board/cm41xx/MAINTAINERS
View File

@ -1,6 +0,0 @@
CM41XX BOARD
#M: -
S: Maintained
F: board/cm41xx/
F: include/configs/cm41xx.h
F: configs/cm41xx_defconfig

8
board/cm41xx/Makefile
View File

@ -1,8 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := cm41xx.o flash.o

88
board/cm41xx/cm41xx.c
View File

@ -1,88 +0,0 @@
/*
* (C) Copyright 2005
* Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
*
* (C) Copyright 2002
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/platform.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
int env_flash_cmdline (void)
{
char *sp = (char *) 0x0201c020;
char *ep;
int len;
/* Check if "erase" push button is depressed */
if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
printf("### Entering network recovery mode...\n");
setenv("bootargs", "console=ttyAM0,115200 mem=32M initrd=0x400000,8M root=/dev/ram0");
setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
setenv("bootdelay", "2");
return 0;
}
/* Check for flash based kernel boot args to use as default */
for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
;
if ((len > 0) && (len <1024))
setenv("bootargs", sp);
return 0;
}
int board_late_init (void)
{
return 0;
}
int board_eth_init(bd_t *bis)
{
return ks8695_eth_initialize();
}
int board_init (void)
{
/* arch number of CM41xx */
gd->bd->bi_arch_number = 672;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
/* power down all but port 0 on the switch */
ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
return 0;
}
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return (0);
}

1
board/cm41xx/config.mk
View File

@ -1 +0,0 @@
CONFIG_SYS_TEXT_BASE = 0x00f00000

395
board/cm41xx/flash.c
View File

@ -1,395 +0,0 @@
/*
* (C) Copyright 2005
* Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
*
* (C) Copyright 2001
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/byteorder/swab.h>
#include <asm/sections.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
#define mb() __asm__ __volatile__ ("" : : : "memory")
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
static int write_data (flash_info_t * info, ulong dest, unsigned char data);
static void flash_get_offsets (ulong base, flash_info_t * info);
void inline spin_wheel (void);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
int i;
ulong size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
switch (i) {
case 0:
flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
break;
case 1:
/* ignore for now */
flash_info[i].flash_id = FLASH_UNKNOWN;
break;
default:
panic ("configured too many flash banks!\n");
break;
}
size += flash_info[i].size;
}
/* Protect monitor and environment sectors
*/
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
&flash_info[0]);
return size;
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN)
return;
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
info->protect[i] = 0;
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_INTEL:
printf ("INTEL ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F128J3A:
printf ("28F128J3A\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
}
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
{
volatile unsigned char value;
/* Write auto select command: read Manufacturer ID */
addr[0x5555] = 0xAA;
addr[0x2AAA] = 0x55;
addr[0x5555] = 0x90;
mb ();
value = addr[0];
switch (value) {
case (unsigned char)INTEL_MANUFACT:
info->flash_id = FLASH_MAN_INTEL;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
addr[0] = 0xFF; /* restore read mode */
return (0); /* no or unknown flash */
}
mb ();
value = addr[2]; /* device ID */
switch (value) {
case (unsigned char)INTEL_ID_28F640J3A:
info->flash_id += FLASH_28F640J3A;
info->sector_count = 64;
info->size = 0x00800000;
break; /* => 8 MB */
case (unsigned char)INTEL_ID_28F128J3A:
info->flash_id += FLASH_28F128J3A;
info->sector_count = 128;
info->size = 0x01000000;
break; /* => 16 MB */
default:
info->flash_id = FLASH_UNKNOWN;
break;
}
if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
addr[0] = 0xFF; /* restore read mode */
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int prot, sect;
ulong type;
int rcode = 0;
ulong start;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
type = (info->flash_id & FLASH_VENDMASK);
if ((type != FLASH_MAN_INTEL)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot)
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
else
printf ("\n");
/* Disable interrupts which might cause a timeout here */
disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
volatile unsigned char *addr;
unsigned char status;
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
addr = (volatile unsigned char *) (info->start[sect]);
*addr = 0x50; /* clear status register */
*addr = 0x20; /* erase setup */
*addr = 0xD0; /* erase confirm */
while (((status = *addr) & 0x80) != 0x80) {
if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = 0xB0; /* suspend erase */
*addr = 0xFF; /* reset to read mode */
rcode = 1;
break;
}
}
*addr = 0x50; /* clear status register cmd */
*addr = 0xFF; /* resest to read mode */
printf (" done\n");
}
}
return rcode;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
* 4 - Flash not identified
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp;
unsigned char data;
int count, i, l, rc, port_width;
if (info->flash_id == FLASH_UNKNOWN)
return 4;
wp = addr;
port_width = 1;
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i < port_width && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
if ((rc = write_data (info, wp, data)) != 0) {
return (rc);
}
wp += port_width;
}
/*
* handle word aligned part
*/
count = 0;
while (cnt >= port_width) {
data = 0;
for (i = 0; i < port_width; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_data (info, wp, data)) != 0) {
return (rc);
}
wp += port_width;
cnt -= port_width;
if (count++ > 0x800) {
spin_wheel ();
count = 0;
}
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return (write_data (info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word or halfword to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_data (flash_info_t * info, ulong dest, unsigned char data)
{
volatile unsigned char *addr = (volatile unsigned char *) dest;
ulong status;
ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
printf ("not erased at %08lx (%lx)\n", (ulong) addr,
(ulong) * addr);
return (2);
}
/* Disable interrupts which might cause a timeout here */
disable_interrupts();
*addr = 0x40; /* write setup */
*addr = data;
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & 0x80) != 0x80) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = 0xFF; /* restore read mode */
return (1);
}
}
*addr = 0xFF; /* restore read mode */
return (0);
}
void inline spin_wheel (void)
{
static int p = 0;
static char w[] = "\\/-";
printf ("\010%c", w[p]);
(++p == 3) ? (p = 0) : 0;
}

2
configs/cm4008_defconfig
View File

@ -1,2 +0,0 @@
CONFIG_ARM=y
CONFIG_TARGET_CM4008=y

2
configs/cm41xx_defconfig
View File

@ -1,2 +0,0 @@
CONFIG_ARM=y
CONFIG_TARGET_CM41XX=y

2
doc/README.scrapyard
View File

@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
cm4008 arm arm920t - - Greg Ungerer <greg.ungerer@opengear.com>
cm41xx arm arm920t - -
dkb arm arm926ejs - - Lei Wen <leiwen@marvell.com>
jadecpu arm arm926ejs - - Matthias Weisser <weisserm@arcor.de>
icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk <wd@denx.de>

1
drivers/net/Makefile
View File

@ -33,7 +33,6 @@ obj-$(CONFIG_FTMAC110) += ftmac110.o
obj-$(CONFIG_FTMAC100) += ftmac100.o
obj-$(CONFIG_GRETH) += greth.o
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_LAN91C96) += lan91c96.o
obj-$(CONFIG_MACB) += macb.o

229
drivers/net/ks8695eth.c
View File

@ -1,229 +0,0 @@
/*
* ks8695eth.c -- KS8695 ethernet driver
*
* (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/****************************************************************************/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <asm/io.h>
#include <asm/arch/platform.h>
/****************************************************************************/
/*
* Hardware register access to the KS8695 LAN ethernet port
* (well, it is the 4 port switch really).
*/
#define ks8695_read(a) *((volatile unsigned long *) (KS8695_IO_BASE + (a)))
#define ks8695_write(a,v) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) = (v)
/****************************************************************************/
/*
* Define the descriptor in-memory data structures.
*/
struct ks8695_txdesc {
uint32_t owner;
uint32_t ctrl;
uint32_t addr;
uint32_t next;
};
struct ks8695_rxdesc {
uint32_t status;
uint32_t ctrl;
uint32_t addr;
uint32_t next;
};
/****************************************************************************/
/*
* Allocate local data structures to use for receiving and sending
* packets. Just to keep it all nice and simple.
*/
#define TXDESCS 4
#define RXDESCS 4
#define BUFSIZE 2048
volatile struct ks8695_txdesc ks8695_tx[TXDESCS] __attribute__((aligned(256)));
volatile struct ks8695_rxdesc ks8695_rx[RXDESCS] __attribute__((aligned(256)));
volatile uint8_t ks8695_bufs[BUFSIZE*(TXDESCS+RXDESCS)] __attribute__((aligned(2048)));;
/****************************************************************************/
/*
* Ideally we want to use the MAC address stored in flash.
* But we do some sanity checks in case they are not present
* first.
*/
unsigned char eth_mac[] = {
0x00, 0x13, 0xc6, 0x00, 0x00, 0x00
};
void ks8695_getmac(void)
{
unsigned char *fp;
int i;
/* Check if flash MAC is valid */
fp = (unsigned char *) 0x0201c000;
for (i = 0; (i < 6); i++) {
if ((fp[i] != 0) && (fp[i] != 0xff))
break;
}
/* If we found a valid looking MAC address then use it */
if (i < 6)
memcpy(&eth_mac[0], fp, 6);
}
/****************************************************************************/
static int ks8695_eth_init(struct eth_device *dev, bd_t *bd)
{
int i;
debug ("%s(%d): eth_reset()\n", __FILE__, __LINE__);
/* Reset the ethernet engines first */
ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
ks8695_getmac();
/* Set MAC address */
ks8695_write(KS8695_LAN_MAC_LOW, (eth_mac[5] | (eth_mac[4] << 8) |
(eth_mac[3] << 16) | (eth_mac[2] << 24)));
ks8695_write(KS8695_LAN_MAC_HIGH, (eth_mac[1] | (eth_mac[0] << 8)));
/* Turn the 4 port switch on */
i = ks8695_read(KS8695_SWITCH_CTRL0);
ks8695_write(KS8695_SWITCH_CTRL0, (i | 0x1));
/* ks8695_write(KS8695_WAN_CONTROL, 0x3f000066); */
/* Initialize descriptor rings */
for (i = 0; (i < TXDESCS); i++) {
ks8695_tx[i].owner = 0;
ks8695_tx[i].ctrl = 0;
ks8695_tx[i].addr = (uint32_t) &ks8695_bufs[i*BUFSIZE];
ks8695_tx[i].next = (uint32_t) &ks8695_tx[i+1];
}
ks8695_tx[TXDESCS-1].ctrl = 0x02000000;
ks8695_tx[TXDESCS-1].next = (uint32_t) &ks8695_tx[0];
for (i = 0; (i < RXDESCS); i++) {
ks8695_rx[i].status = 0x80000000;
ks8695_rx[i].ctrl = BUFSIZE - 4;
ks8695_rx[i].addr = (uint32_t) &ks8695_bufs[(i+TXDESCS)*BUFSIZE];
ks8695_rx[i].next = (uint32_t) &ks8695_rx[i+1];
}
ks8695_rx[RXDESCS-1].ctrl |= 0x00080000;
ks8695_rx[RXDESCS-1].next = (uint32_t) &ks8695_rx[0];
/* The KS8695 is pretty slow reseting the ethernets... */
udelay(2000000);
/* Enable the ethernet engine */
ks8695_write(KS8695_LAN_TX_LIST, (uint32_t) &ks8695_tx[0]);
ks8695_write(KS8695_LAN_RX_LIST, (uint32_t) &ks8695_rx[0]);
ks8695_write(KS8695_LAN_DMA_TX, 0x3);
ks8695_write(KS8695_LAN_DMA_RX, 0x71);
ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
printf("KS8695 ETHERNET: %pM\n", eth_mac);
return 0;
}
/****************************************************************************/
static void ks8695_eth_halt(struct eth_device *dev)
{
debug ("%s(%d): eth_halt()\n", __FILE__, __LINE__);
/* Reset the ethernet engines */
ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
}
/****************************************************************************/
static int ks8695_eth_recv(struct eth_device *dev)
{
volatile struct ks8695_rxdesc *dp;
int i, len = 0;
debug ("%s(%d): eth_rx()\n", __FILE__, __LINE__);
for (i = 0; (i < RXDESCS); i++) {
dp= &ks8695_rx[i];
if ((dp->status & 0x80000000) == 0) {
len = (dp->status & 0x7ff) - 4;
NetReceive((void *) dp->addr, len);
dp->status = 0x80000000;
ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
break;
}
}
return len;
}
/****************************************************************************/
static int ks8695_eth_send(struct eth_device *dev, void *packet, int len)
{
volatile struct ks8695_txdesc *dp;
static int next = 0;
debug ("%s(%d): eth_send(packet=%p,len=%d)\n", __FILE__, __LINE__,
packet, len);
dp = &ks8695_tx[next];
memcpy((void *) dp->addr, (void *) packet, len);
if (len < 64) {
memset((void *) (dp->addr + len), 0, 64-len);
len = 64;
}
dp->ctrl = len | 0xe0000000;
dp->owner = 0x80000000;
ks8695_write(KS8695_LAN_DMA_TX, 0x3);
ks8695_write(KS8695_LAN_DMA_TX_START, 0x1);
if (++next >= TXDESCS)
next = 0;
return 0;
}
/****************************************************************************/
int ks8695_eth_initialize(void)
{
struct eth_device *dev;
dev = malloc(sizeof(*dev));
if (dev == NULL)
return -1;
memset(dev, 0, sizeof(*dev));
dev->iobase = KS8695_IO_BASE + KS8695_LAN_DMA_TX;
dev->init = ks8695_eth_init;
dev->halt = ks8695_eth_halt;
dev->send = ks8695_eth_send;
dev->recv = ks8695_eth_recv;
strcpy(dev->name, "ks8695eth");
eth_register(dev);
return 0;
}

1
drivers/serial/Makefile
View File

@ -27,7 +27,6 @@ obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
obj-$(CONFIG_SYS_NS16550) += ns16550.o
obj-$(CONFIG_S5P) += serial_s5p.o
obj-$(CONFIG_IMX_SERIAL) += serial_imx.o
obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
obj-$(CONFIG_MXC_UART) += serial_mxc.o
obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o

2
drivers/serial/serial.c
View File

@ -127,7 +127,6 @@ serial_initfunc(evb64260_serial_initialize);
serial_initfunc(imx_serial_initialize);
serial_initfunc(iop480_serial_initialize);
serial_initfunc(jz_serial_initialize);
serial_initfunc(ks8695_serial_initialize);
serial_initfunc(leon2_serial_initialize);
serial_initfunc(leon3_serial_initialize);
serial_initfunc(lh7a40x_serial_initialize);
@ -220,7 +219,6 @@ void serial_initialize(void)
imx_serial_initialize();
iop480_serial_initialize();
jz_serial_initialize();
ks8695_serial_initialize();
leon2_serial_initialize();
leon3_serial_initialize();
lh7a40x_serial_initialize();

121
drivers/serial/serial_ks8695.c
View File

@ -1,121 +0,0 @@
/*
* serial.c -- KS8695 serial driver
*
* (C) Copyright 2004, Greg Ungerer <greg.ungerer@opengear.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/platform.h>
#include <serial.h>
#include <linux/compiler.h>
#ifndef CONFIG_SERIAL1
#error "Bad: you didn't configure serial ..."
#endif
DECLARE_GLOBAL_DATA_PTR;
/*
* Define the UART hardware register access structure.
*/
struct ks8695uart {
unsigned int RX; /* 0x00 - Receive data (r) */
unsigned int TX; /* 0x04 - Transmit data (w) */
unsigned int FCR; /* 0x08 - Fifo Control (r/w) */
unsigned int LCR; /* 0x0c - Line Control (r/w) */
unsigned int MCR; /* 0x10 - Modem Control (r/w) */
unsigned int LSR; /* 0x14 - Line Status (r/w) */
unsigned int MSR; /* 0x18 - Modem Status (r/w) */
unsigned int BD; /* 0x1c - Baud Rate (r/w) */
unsigned int SR; /* 0x20 - Status (r/w) */
};
#define KS8695_UART_ADDR ((void *) (KS8695_IO_BASE + KS8695_UART_RX_BUFFER))
#define KS8695_UART_CLK 25000000
/*
* Under some circumstances we want to be "quiet" and not issue any
* serial output - though we want u-boot to otherwise work and behave
* the same. By default be noisy.
*/
int serial_console = 1;
static void ks8695_serial_setbrg(void)
{
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
/* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/
uartp->BD = KS8695_UART_CLK / gd->baudrate;
uartp->LCR = KS8695_UART_LINEC_WLEN8;
}
static int ks8695_serial_init(void)
{
serial_console = 1;
serial_setbrg();
return 0;
}
static void ks8695_serial_raw_putc(const char c)
{
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
int i;
for (i = 0; (i < 0x100000); i++) {
if (uartp->LSR & KS8695_UART_LINES_TXFE)
break;
}
uartp->TX = c;
}
static void ks8695_serial_putc(const char c)
{
if (serial_console) {
ks8695_serial_raw_putc(c);
if (c == '\n')
ks8695_serial_raw_putc('\r');
}
}
static int ks8695_serial_tstc(void)
{
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
if (serial_console)
return ((uartp->LSR & KS8695_UART_LINES_RXFE) ? 1 : 0);
return 0;
}
static int ks8695_serial_getc(void)
{
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
while ((uartp->LSR & KS8695_UART_LINES_RXFE) == 0)
;
return (uartp->RX);
}
static struct serial_device ks8695_serial_drv = {
.name = "ks8695_serial",
.start = ks8695_serial_init,
.stop = NULL,
.setbrg = ks8695_serial_setbrg,
.putc = ks8695_serial_putc,
.puts = default_serial_puts,
.getc = ks8695_serial_getc,
.tstc = ks8695_serial_tstc,
};
void ks8695_serial_initialize(void)
{
serial_register(&ks8695_serial_drv);
}
__weak struct serial_device *default_serial_console(void)
{
return &ks8695_serial_drv;
}

104
include/configs/cm4008.h
View File

@ -1,104 +0,0 @@
/*
* (C) Copyright 2004
* Greg Ungerer <greg.ungerer@opengear.com>.
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_KS8695 1 /* it is a KS8695 CPU */
#define CONFIG_CM4008 1 /* it is an OpenGear CM4008 boad */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/*
* Hardware drivers
*/
/*
* select serial console configuration
*/
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_KS8695_SERIAL
#define CONFIG_SERIAL1
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_SAVEENV
#define CONFIG_BOOTDELAY 0
#define CONFIG_BOOTARGS "mem=16M console=ttyAM0,115200"
#define CONFIG_BOOTCOMMAND "gofsk 0x02200000"
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */
#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
#endif /* __CONFIG_H */

104
include/configs/cm41xx.h
View File

@ -1,104 +0,0 @@
/*
* (C) Copyright 2005
* Greg Ungerer <greg.ungerer@opengear.com>.
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_KS8695 1 /* it is a KS8695 CPU */
#define CONFIG_CM41xx 1 /* it is an OpenGear CM41xx boad */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/*
* Hardware drivers
*/
/*
* select serial console configuration
*/
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_KS8695_SERIAL
#define CONFIG_SERIAL1
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_SAVEENV
#define CONFIG_BOOTDELAY 0
#define CONFIG_BOOTARGS "mem=32M console=ttyAM0,115200"
#define CONFIG_BOOTCOMMAND "gofsk 0x02200000"
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */
#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
#endif /* __CONFIG_H */

1
include/netdev.h
View File

@ -55,7 +55,6 @@ int ftmac100_initialize(bd_t *bits);
int ftmac110_initialize(bd_t *bits);
int greth_initialize(bd_t *bis);
void gt6426x_eth_initialize(bd_t *bis);
int ks8695_eth_initialize(void);
int ks8851_mll_initialize(u8 dev_num, int base_addr);
int lan91c96_initialize(u8 dev_num, int base_addr);
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);

1
include/serial.h
View File

@ -182,7 +182,6 @@ void evb64260_serial_initialize(void);
void imx_serial_initialize(void);
void iop480_serial_initialize(void);
void jz_serial_initialize(void);
void ks8695_serial_initialize(void);
void leon2_serial_initialize(void);
void leon3_serial_initialize(void);
void lh7a40x_serial_initialize(void);