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https://github.com/brain-hackers/u-boot-brain
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zynq: Use system timer implementation instead of our
Don't use error-prone arch timer code and instead use system timer implementation to simplify our code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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@ -12,7 +12,6 @@
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#define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
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#define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
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#define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
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#define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
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#define ZYNQ_SCU_BASEADDR 0xF8F00000
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#define ZYNQ_SCU_BASEADDR 0xF8F00000
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#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600
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#define ZYNQ_GEM_BASEADDR0 0xE000B000
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#define ZYNQ_GEM_BASEADDR0 0xE000B000
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#define ZYNQ_GEM_BASEADDR1 0xE000C000
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#define ZYNQ_GEM_BASEADDR1 0xE000C000
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#define ZYNQ_SDHCI_BASEADDR0 0xE0100000
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#define ZYNQ_SDHCI_BASEADDR0 0xE0100000
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@ -77,92 +77,11 @@ int timer_init(void)
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return 0;
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return 0;
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}
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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ulong get_timer_masked(void)
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{
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ulong now;
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now = readl(&timer_base->counter) /
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(gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
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if (gd->arch.lastinc >= now) {
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/* Normal mode */
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gd->arch.tbl += gd->arch.lastinc - now;
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} else {
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/* We have an overflow ... */
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gd->arch.tbl += gd->arch.lastinc + (TIMER_LOAD_VAL /
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(gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) -
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now + 1;
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}
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gd->arch.lastinc = now;
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return gd->arch.tbl;
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}
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void __udelay(unsigned long usec)
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{
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u32 countticks;
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u32 timeend;
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u32 timediff;
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u32 timenow;
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if (usec == 0)
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return;
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countticks = lldiv(((unsigned long long)gd->arch.timer_rate_hz * usec),
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1000000);
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/* decrementing timer */
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timeend = readl(&timer_base->counter) - countticks;
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#if TIMER_LOAD_VAL != 0xFFFFFFFF
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/* do not manage multiple overflow */
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if (countticks >= TIMER_LOAD_VAL)
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countticks = TIMER_LOAD_VAL - 1;
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#endif
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do {
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timenow = readl(&timer_base->counter);
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if (timenow >= timeend) {
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/* normal case */
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timediff = timenow - timeend;
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} else {
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if ((TIMER_LOAD_VAL - timeend + timenow) <=
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countticks) {
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/* overflow */
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timediff = TIMER_LOAD_VAL - timeend + timenow;
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} else {
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/* missed the exact match */
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break;
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}
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}
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} while (timediff > 0);
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}
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/* Timer without interrupts */
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ulong get_timer(ulong base)
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{
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return get_timer_masked() - base;
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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* On ARM it returns the number of timer ticks per second.
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*/
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*/
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ulong get_tbclk(void)
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ulong get_tbclk(void)
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{
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{
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return CONFIG_SYS_HZ;
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return gd->arch.timer_rate_hz;
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}
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}
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@ -25,6 +25,11 @@
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# define CONFIG_SYS_PL310_BASE 0xf8f02000
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# define CONFIG_SYS_PL310_BASE 0xf8f02000
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#endif
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#endif
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#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600
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#define CONFIG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR
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#define CONFIG_SYS_TIMER_COUNTS_DOWN
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#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
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/* Serial drivers */
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/* Serial drivers */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BAUDRATE 115200
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/* The following table includes the supported baudrates */
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/* The following table includes the supported baudrates */
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