pinctrl: renesas: Synchronize R-Car Gen2/Gen3 tables with Linux 5.12
Synchronize R-Car Gen2/Gen3 pinctrl tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") . This is a rather large
commit, since the macros in sh-pfc.h also got updated, so
all the PFC tables must be updated in lockstep.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This commit is contained in:
Marek Vasut
parent
e3b64beda5
commit
a2a14854f2
File diff suppressed because it is too large
Load Diff
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@ -18,7 +18,7 @@
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* Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
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* which case they support both 3.3V and 1.8V signalling.
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*/
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#define CPU_ALL_PORT(fn, sfx) \
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#define CPU_ALL_GP(fn, sfx) \
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PORT_GP_32(0, fn, sfx), \
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PORT_GP_26(1, fn, sfx), \
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PORT_GP_32(2, fn, sfx), \
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@ -1703,6 +1703,7 @@ static const struct sh_pfc_pin pinmux_pins[] = {
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PINMUX_GPIO_GP_ALL(),
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};
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#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
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/* - ADI -------------------------------------------------------------------- */
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static const unsigned int adi_common_pins[] = {
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/* ADIDATA, ADICS/SAMP, ADICLK */
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@ -1768,6 +1769,7 @@ static const unsigned int adi_chsel2_b_mux[] = {
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/* ADICHS B 2 */
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ADICHS2_B_MARK,
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};
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#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
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/* - Audio Clock ------------------------------------------------------------ */
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static const unsigned int audio_clk_a_pins[] = {
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@ -2556,6 +2558,8 @@ static const unsigned int intc_irq3_pins[] = {
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static const unsigned int intc_irq3_mux[] = {
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IRQ3_MARK,
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};
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#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
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/* - MLB+ ------------------------------------------------------------------- */
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static const unsigned int mlb_3pin_pins[] = {
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RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
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@ -2563,6 +2567,8 @@ static const unsigned int mlb_3pin_pins[] = {
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static const unsigned int mlb_3pin_mux[] = {
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MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
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};
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#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
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/* - MMCIF ------------------------------------------------------------------ */
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static const unsigned int mmc_data1_pins[] = {
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/* D[0] */
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@ -4455,7 +4461,9 @@ static const unsigned int vin2_clk_mux[] = {
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static const struct {
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struct sh_pfc_pin_group common[346];
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#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
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struct sh_pfc_pin_group automotive[9];
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#endif
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} pinmux_groups = {
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.common = {
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SH_PFC_PIN_GROUP(audio_clk_a),
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@ -4805,6 +4813,7 @@ static const struct {
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SH_PFC_PIN_GROUP(vin2_clkenb),
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SH_PFC_PIN_GROUP(vin2_clk),
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},
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#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
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.automotive = {
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SH_PFC_PIN_GROUP(adi_common),
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SH_PFC_PIN_GROUP(adi_chsel0),
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@ -4816,8 +4825,10 @@ static const struct {
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SH_PFC_PIN_GROUP(adi_chsel2_b),
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SH_PFC_PIN_GROUP(mlb_3pin),
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}
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#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
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};
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#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
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static const char * const adi_groups[] = {
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"adi_common",
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"adi_chsel0",
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@ -4828,6 +4839,7 @@ static const char * const adi_groups[] = {
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"adi_chsel1_b",
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"adi_chsel2_b",
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};
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#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
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static const char * const audio_clk_groups[] = {
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"audio_clk_a",
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@ -5005,9 +5017,11 @@ static const char * const intc_groups[] = {
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"intc_irq3",
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};
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#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
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static const char * const mlb_groups[] = {
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"mlb_3pin",
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};
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#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
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static const char * const mmc_groups[] = {
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"mmc_data1",
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@ -5362,7 +5376,9 @@ static const char * const vin2_groups[] = {
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static const struct {
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struct sh_pfc_function common[58];
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#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
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struct sh_pfc_function automotive[2];
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#endif
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} pinmux_functions = {
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.common = {
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SH_PFC_FUNCTION(audio_clk),
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@ -5424,10 +5440,12 @@ static const struct {
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SH_PFC_FUNCTION(vin1),
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SH_PFC_FUNCTION(vin2),
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},
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#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
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.automotive = {
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SH_PFC_FUNCTION(adi),
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SH_PFC_FUNCTION(mlb),
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}
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#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
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};
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static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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@ -14,7 +14,7 @@
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#include "sh_pfc.h"
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#define CPU_ALL_PORT(fn, sfx) \
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#define CPU_ALL_GP(fn, sfx) \
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PORT_GP_29(0, fn, sfx), \
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PORT_GP_23(1, fn, sfx), \
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PORT_GP_32(2, fn, sfx), \
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@ -15,7 +15,7 @@
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#include "sh_pfc.h"
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#define CPU_ALL_PORT(fn, sfx) \
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#define CPU_ALL_GP(fn, sfx) \
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PORT_GP_32(0, fn, sfx), \
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PORT_GP_26(1, fn, sfx), \
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PORT_GP_32(2, fn, sfx), \
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* R8A7795 ES2.0+ processor support - PFC hardware block.
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* R8A77951 processor support - PFC hardware block.
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*
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* Copyright (C) 2015-2019 Renesas Electronics Corporation
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*/
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@ -13,11 +13,9 @@
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#include "sh_pfc.h"
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#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
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SH_PFC_PIN_CFG_PULL_UP | \
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SH_PFC_PIN_CFG_PULL_DOWN)
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#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
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#define CPU_ALL_PORT(fn, sfx) \
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#define CPU_ALL_GP(fn, sfx) \
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PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
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@ -30,6 +28,52 @@
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PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
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#define CPU_ALL_NOGP(fn) \
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PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
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PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
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PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
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/*
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* F_() : just information
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* FM() : macro for FN_xxx / xxx_MARK
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@ -1509,68 +1553,16 @@ static const u16 pinmux_data[] = {
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};
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/*
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* R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
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* Physical layout rows: A - AW, cols: 1 - 39.
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* Pins not associated with a GPIO port.
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*/
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#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
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#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
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#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
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#define PIN_NONE U16_MAX
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enum {
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GP_ASSIGN_LAST(),
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NOGP_ALL(),
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};
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static const struct sh_pfc_pin pinmux_pins[] = {
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PINMUX_GPIO_GP_ALL(),
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/*
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* Pins not associated with a GPIO port.
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*
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* The pin positions are different between different r8a7795
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* packages, all that is needed for the pfc driver is a unique
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* number for each pin. To this end use the pin layout from
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* R-Car H3SiP to calculate a unique number for each pin.
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*/
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SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
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SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
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PINMUX_NOGP_ALL(),
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};
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/* - AUDIO CLOCK ------------------------------------------------------------ */
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@ -1718,7 +1710,7 @@ static const unsigned int avb_phy_int_mux[] = {
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};
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static const unsigned int avb_mdio_pins[] = {
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/* AVB_MDC, AVB_MDIO */
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RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
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RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
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};
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static const unsigned int avb_mdio_mux[] = {
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AVB_MDC_MARK, AVB_MDIO_MARK,
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@ -1731,12 +1723,11 @@ static const unsigned int avb_mii_pins[] = {
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* AVB_RD1, AVB_RD2, AVB_RD3,
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* AVB_TXCREFCLK
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*/
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PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
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PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
|
||||
PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
|
||||
PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
|
||||
PIN_NUMBER('A', 12),
|
||||
|
||||
PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
|
||||
PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
|
||||
PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
|
||||
PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
|
||||
PIN_AVB_TXCREFCLK,
|
||||
};
|
||||
static const unsigned int avb_mii_mux[] = {
|
||||
AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
|
||||
|
|
@ -3261,6 +3252,57 @@ static const unsigned int pwm6_b_mux[] = {
|
|||
PWM6_B_MARK,
|
||||
};
|
||||
|
||||
/* - QSPI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi0_ctrl_pins[] = {
|
||||
/* QSPI0_SPCLK, QSPI0_SSL */
|
||||
PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
|
||||
};
|
||||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
|
||||
};
|
||||
static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data4_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
|
||||
/* QSPI0_IO2, QSPI0_IO3 */
|
||||
PIN_QSPI0_IO2, PIN_QSPI0_IO3,
|
||||
};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
|
||||
};
|
||||
/* - QSPI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi1_ctrl_pins[] = {
|
||||
/* QSPI1_SPCLK, QSPI1_SSL */
|
||||
PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
|
||||
};
|
||||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
|
||||
/* QSPI1_IO2, QSPI1_IO3 */
|
||||
PIN_QSPI1_IO2, PIN_QSPI1_IO3,
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
|
||||
};
|
||||
|
||||
/* - SATA --------------------------------------------------------------------*/
|
||||
static const unsigned int sata0_devslp_a_pins[] = {
|
||||
/* DEVSLP */
|
||||
|
|
@ -4169,7 +4211,7 @@ static const unsigned int vin5_clk_mux[] = {
|
|||
};
|
||||
|
||||
static const struct {
|
||||
struct sh_pfc_pin_group common[320];
|
||||
struct sh_pfc_pin_group common[326];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
||||
struct sh_pfc_pin_group automotive[30];
|
||||
#endif
|
||||
|
|
@ -4374,6 +4416,12 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(pwm5_b),
|
||||
SH_PFC_PIN_GROUP(pwm6_a),
|
||||
SH_PFC_PIN_GROUP(pwm6_b),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
SH_PFC_PIN_GROUP(sata0_devslp_a),
|
||||
SH_PFC_PIN_GROUP(sata0_devslp_b),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
|
|
@ -4868,6 +4916,18 @@ static const char * const pwm6_groups[] = {
|
|||
"pwm6_b",
|
||||
};
|
||||
|
||||
static const char * const qspi0_groups[] = {
|
||||
"qspi0_ctrl",
|
||||
"qspi0_data2",
|
||||
"qspi0_data4",
|
||||
};
|
||||
|
||||
static const char * const qspi1_groups[] = {
|
||||
"qspi1_ctrl",
|
||||
"qspi1_data2",
|
||||
"qspi1_data4",
|
||||
};
|
||||
|
||||
static const char * const sata0_groups[] = {
|
||||
"sata0_devslp_a",
|
||||
"sata0_devslp_b",
|
||||
|
|
@ -5056,7 +5116,7 @@ static const char * const vin5_groups[] = {
|
|||
};
|
||||
|
||||
static const struct {
|
||||
struct sh_pfc_function common[53];
|
||||
struct sh_pfc_function common[55];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
||||
struct sh_pfc_function automotive[4];
|
||||
#endif
|
||||
|
|
@ -5093,6 +5153,8 @@ static const struct {
|
|||
SH_PFC_FUNCTION(pwm4),
|
||||
SH_PFC_FUNCTION(pwm5),
|
||||
SH_PFC_FUNCTION(pwm6),
|
||||
SH_PFC_FUNCTION(qspi0),
|
||||
SH_PFC_FUNCTION(qspi1),
|
||||
SH_PFC_FUNCTION(sata0),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
|
|
@ -5692,44 +5754,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
|
||||
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
|
||||
{ PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
|
||||
{ PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
|
||||
{ PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
|
||||
{ PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
|
||||
{ PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
|
||||
{ PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
|
||||
{ PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
|
||||
{ PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
|
||||
{ PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
|
||||
{ PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
|
||||
{ PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
|
||||
{ PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
|
||||
{ PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
|
||||
{ PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
|
||||
{ PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
|
||||
{ PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
|
||||
{ PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
|
||||
{ PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
|
||||
{ PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
|
||||
{ PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
|
||||
{ PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
|
||||
{ PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
|
||||
{ PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
|
||||
{ PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
|
||||
{ PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
|
||||
{ PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
|
||||
{ PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
|
||||
{ PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
|
||||
{ PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
|
||||
{ PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
|
||||
{ PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
|
||||
{ PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
|
||||
{ PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
|
||||
{ PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
|
||||
{ PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
|
||||
{ PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
|
||||
{ PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
|
||||
{ PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
|
||||
{ PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
|
||||
{ PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
|
||||
{ PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
|
||||
{ PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
|
||||
{ PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
|
||||
{ PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
|
||||
{ PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
|
||||
{ PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
|
||||
{ PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
|
||||
{ PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
|
||||
{ PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
|
||||
{ PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
|
||||
{ PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
|
||||
{ PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
|
||||
{ PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
|
||||
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
|
||||
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
|
||||
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
|
||||
{ PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
|
||||
{ PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
|
||||
{ PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
|
||||
{ PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
|
||||
{ PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
|
||||
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
|
||||
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
|
||||
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
|
||||
{ RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
|
||||
|
|
@ -5783,7 +5845,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
|
||||
{ RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
|
||||
{ PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
|
||||
{ PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
|
||||
{ RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
|
||||
{ RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
|
||||
{ RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
|
||||
|
|
@ -5802,30 +5864,32 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
|
||||
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
|
||||
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
|
||||
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
|
||||
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
|
||||
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
|
||||
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
|
||||
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
|
||||
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
|
||||
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
|
||||
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
|
||||
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
|
||||
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
|
||||
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
|
||||
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
|
||||
{ PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
|
||||
{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
|
||||
{ PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
|
||||
{ PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
|
||||
{ PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
|
||||
{ PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
||||
{ PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
|
||||
#endif
|
||||
{ PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
|
||||
{ PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
|
||||
{ PIN_TMS, 4, 2 }, /* TMS */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
|
||||
{ PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
|
||||
{ PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
|
||||
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
|
||||
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
|
||||
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
|
||||
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
|
||||
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
|
||||
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
|
||||
{ PIN_TDO, 28, 2 }, /* TDO */
|
||||
{ PIN_ASEBRK, 24, 2 }, /* ASEBRK */
|
||||
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
|
||||
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
|
||||
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
|
||||
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
|
||||
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
|
||||
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
|
||||
{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
|
||||
|
|
@ -5894,7 +5958,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
|
||||
{ RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
|
||||
{ RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
|
||||
{ PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
|
||||
{ PIN_MLB_REF, 4, 3 }, /* MLB_REF */
|
||||
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
|
||||
|
|
@ -5933,8 +5997,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
|
||||
{ RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
|
||||
{ RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
|
||||
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
|
||||
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
|
||||
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */
|
||||
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */
|
||||
} },
|
||||
{ },
|
||||
};
|
||||
|
|
@ -5950,7 +6014,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
|
||||
static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc,
|
||||
unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = -EINVAL;
|
||||
|
||||
|
|
@ -5967,35 +6032,35 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
|
|||
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
|
||||
[ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
|
||||
[ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
|
||||
[ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
|
||||
[ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
|
||||
[ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
|
||||
[ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
|
||||
[ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
|
||||
[ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
|
||||
[ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
|
||||
[ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
|
||||
[10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
|
||||
[11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
|
||||
[12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
|
||||
[13] = PIN_NUMBER('V', 6), /* RPC_WP# */
|
||||
[14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
|
||||
[15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
|
||||
[16] = PIN_NUMBER('B', 19), /* AVB_RXC */
|
||||
[17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
|
||||
[18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
|
||||
[19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
|
||||
[20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
|
||||
[21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
|
||||
[22] = PIN_NUMBER('A', 19), /* AVB_TXC */
|
||||
[23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
|
||||
[24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
|
||||
[25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
|
||||
[26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
|
||||
[27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
|
||||
[28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
|
||||
[ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
|
||||
[ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
|
||||
[ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
|
||||
[ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
|
||||
[ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
|
||||
[ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
|
||||
[ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
|
||||
[ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
|
||||
[ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
|
||||
[ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
|
||||
[10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
|
||||
[11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
|
||||
[12] = PIN_RPC_INT_N, /* RPC_INT# */
|
||||
[13] = PIN_RPC_WP_N, /* RPC_WP# */
|
||||
[14] = PIN_RPC_RESET_N, /* RPC_RESET# */
|
||||
[15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
|
||||
[16] = PIN_AVB_RXC, /* AVB_RXC */
|
||||
[17] = PIN_AVB_RD0, /* AVB_RD0 */
|
||||
[18] = PIN_AVB_RD1, /* AVB_RD1 */
|
||||
[19] = PIN_AVB_RD2, /* AVB_RD2 */
|
||||
[20] = PIN_AVB_RD3, /* AVB_RD3 */
|
||||
[21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
|
||||
[22] = PIN_AVB_TXC, /* AVB_TXC */
|
||||
[23] = PIN_AVB_TD0, /* AVB_TD0 */
|
||||
[24] = PIN_AVB_TD1, /* AVB_TD1 */
|
||||
[25] = PIN_AVB_TD2, /* AVB_TD2 */
|
||||
[26] = PIN_AVB_TD3, /* AVB_TD3 */
|
||||
[27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
|
||||
[28] = PIN_AVB_MDIO, /* AVB_MDIO */
|
||||
[29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
|
||||
[30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
|
||||
[31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
|
||||
|
|
@ -6044,7 +6109,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
|
||||
[ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
|
||||
[ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
|
||||
[ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
|
||||
[ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
|
||||
[10] = RCAR_GP_PIN(0, 0), /* D0 */
|
||||
[11] = RCAR_GP_PIN(0, 1), /* D1 */
|
||||
[12] = RCAR_GP_PIN(0, 2), /* D2 */
|
||||
|
|
@ -6065,20 +6130,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
|
||||
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
|
||||
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
|
||||
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
|
||||
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
|
||||
[30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
|
||||
[31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
|
||||
[ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
|
||||
[ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
|
||||
[ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
|
||||
[ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
|
||||
[ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
|
||||
[ 5] = PIN_A_NUMBER('T', 27), /* TCK */
|
||||
[ 6] = PIN_A_NUMBER('R', 30), /* TMS */
|
||||
[ 7] = PIN_A_NUMBER('R', 29), /* TDI */
|
||||
[ 8] = PIN_NONE,
|
||||
[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
|
||||
[ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
|
||||
[ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
|
||||
[ 2] = PIN_FSCLKST_N, /* FSCLKST# */
|
||||
[ 3] = PIN_EXTALR, /* EXTALR*/
|
||||
[ 4] = PIN_TRST_N, /* TRST# */
|
||||
[ 5] = PIN_TCK, /* TCK */
|
||||
[ 6] = PIN_TMS, /* TMS */
|
||||
[ 7] = PIN_TDI, /* TDI */
|
||||
[ 8] = SH_PFC_PIN_NONE,
|
||||
[ 9] = PIN_ASEBRK, /* ASEBRK */
|
||||
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
|
||||
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
|
||||
[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
|
||||
|
|
@ -6143,7 +6208,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
|
||||
[ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
|
||||
[ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
|
||||
[ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
|
||||
[ 6] = PIN_MLB_REF, /* MLB_REF */
|
||||
[ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
|
||||
[ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
|
||||
[ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
|
||||
|
|
@ -6178,31 +6243,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
|
||||
[ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
|
||||
[ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
|
||||
[ 7] = PIN_NONE,
|
||||
[ 8] = PIN_NONE,
|
||||
[ 9] = PIN_NONE,
|
||||
[10] = PIN_NONE,
|
||||
[11] = PIN_NONE,
|
||||
[12] = PIN_NONE,
|
||||
[13] = PIN_NONE,
|
||||
[14] = PIN_NONE,
|
||||
[15] = PIN_NONE,
|
||||
[16] = PIN_NONE,
|
||||
[17] = PIN_NONE,
|
||||
[18] = PIN_NONE,
|
||||
[19] = PIN_NONE,
|
||||
[20] = PIN_NONE,
|
||||
[21] = PIN_NONE,
|
||||
[22] = PIN_NONE,
|
||||
[23] = PIN_NONE,
|
||||
[24] = PIN_NONE,
|
||||
[25] = PIN_NONE,
|
||||
[26] = PIN_NONE,
|
||||
[27] = PIN_NONE,
|
||||
[28] = PIN_NONE,
|
||||
[29] = PIN_NONE,
|
||||
[30] = PIN_NONE,
|
||||
[31] = PIN_NONE,
|
||||
[ 7] = SH_PFC_PIN_NONE,
|
||||
[ 8] = SH_PFC_PIN_NONE,
|
||||
[ 9] = SH_PFC_PIN_NONE,
|
||||
[10] = SH_PFC_PIN_NONE,
|
||||
[11] = SH_PFC_PIN_NONE,
|
||||
[12] = SH_PFC_PIN_NONE,
|
||||
[13] = SH_PFC_PIN_NONE,
|
||||
[14] = SH_PFC_PIN_NONE,
|
||||
[15] = SH_PFC_PIN_NONE,
|
||||
[16] = SH_PFC_PIN_NONE,
|
||||
[17] = SH_PFC_PIN_NONE,
|
||||
[18] = SH_PFC_PIN_NONE,
|
||||
[19] = SH_PFC_PIN_NONE,
|
||||
[20] = SH_PFC_PIN_NONE,
|
||||
[21] = SH_PFC_PIN_NONE,
|
||||
[22] = SH_PFC_PIN_NONE,
|
||||
[23] = SH_PFC_PIN_NONE,
|
||||
[24] = SH_PFC_PIN_NONE,
|
||||
[25] = SH_PFC_PIN_NONE,
|
||||
[26] = SH_PFC_PIN_NONE,
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
|
@ -6248,8 +6313,8 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
|||
sh_pfc_write(pfc, reg->puen, enable);
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
|
||||
.pin_to_pocctrl = r8a7795_pin_to_pocctrl,
|
||||
static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = {
|
||||
.pin_to_pocctrl = r8a77951_pin_to_pocctrl,
|
||||
.get_bias = r8a7795_pinmux_get_bias,
|
||||
.set_bias = r8a7795_pinmux_set_bias,
|
||||
};
|
||||
|
|
@ -6257,7 +6322,7 @@ static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
|
|||
#ifdef CONFIG_PINCTRL_PFC_R8A774E1
|
||||
const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
|
||||
.name = "r8a774e1_pfc",
|
||||
.ops = &r8a7795_pinmux_ops,
|
||||
.ops = &r8a77951_pinmux_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
@ -6282,7 +6347,7 @@ const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
|
|||
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
||||
const struct sh_pfc_soc_info r8a7795_pinmux_info = {
|
||||
.name = "r8a77951_pfc",
|
||||
.ops = &r8a7795_pinmux_ops,
|
||||
.ops = &r8a77951_pinmux_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* R8A7796 processor support - PFC hardware block.
|
||||
* R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
|
||||
*
|
||||
* Copyright (C) 2016-2019 Renesas Electronics Corp.
|
||||
*
|
||||
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
|
||||
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
|
||||
*
|
||||
* R-Car Gen3 processor support - PFC hardware block.
|
||||
*
|
||||
|
|
@ -19,11 +19,9 @@
|
|||
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
|
||||
SH_PFC_PIN_CFG_PULL_UP | \
|
||||
SH_PFC_PIN_CFG_PULL_DOWN)
|
||||
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
||||
#define CPU_ALL_PORT(fn, sfx) \
|
||||
#define CPU_ALL_GP(fn, sfx) \
|
||||
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
|
||||
|
|
@ -36,6 +34,51 @@
|
|||
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
|
||||
|
||||
#define CPU_ALL_NOGP(fn) \
|
||||
PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
|
||||
PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
||||
/*
|
||||
* F_() : just information
|
||||
* FM() : macro for FN_xxx / xxx_MARK
|
||||
|
|
@ -688,7 +731,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
|
||||
PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
|
||||
PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
|
||||
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
|
||||
|
|
@ -1514,67 +1557,16 @@ static const u16 pinmux_data[] = {
|
|||
};
|
||||
|
||||
/*
|
||||
* R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
|
||||
* Physical layout rows: A - AW, cols: 1 - 39.
|
||||
* Pins not associated with a GPIO port.
|
||||
*/
|
||||
#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
|
||||
#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
|
||||
#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
|
||||
#define PIN_NONE U16_MAX
|
||||
enum {
|
||||
GP_ASSIGN_LAST(),
|
||||
NOGP_ALL(),
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
PINMUX_GPIO_GP_ALL(),
|
||||
|
||||
/*
|
||||
* Pins not associated with a GPIO port.
|
||||
*
|
||||
* The pin positions are different between different r8a7796
|
||||
* packages, all that is needed for the pfc driver is a unique
|
||||
* number for each pin. To this end use the pin layout from
|
||||
* R-Car M3SiP to calculate a unique number for each pin.
|
||||
*/
|
||||
SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
|
||||
PINMUX_NOGP_ALL(),
|
||||
};
|
||||
|
||||
/* - AUDIO CLOCK ------------------------------------------------------------ */
|
||||
|
|
@ -1723,7 +1715,7 @@ static const unsigned int avb_phy_int_mux[] = {
|
|||
};
|
||||
static const unsigned int avb_mdio_pins[] = {
|
||||
/* AVB_MDC, AVB_MDIO */
|
||||
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
|
||||
RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
|
||||
};
|
||||
static const unsigned int avb_mdio_mux[] = {
|
||||
AVB_MDC_MARK, AVB_MDIO_MARK,
|
||||
|
|
@ -1736,12 +1728,11 @@ static const unsigned int avb_mii_pins[] = {
|
|||
* AVB_RD1, AVB_RD2, AVB_RD3,
|
||||
* AVB_TXCREFCLK
|
||||
*/
|
||||
PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
|
||||
PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
|
||||
PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
|
||||
PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
|
||||
PIN_NUMBER('A', 12),
|
||||
|
||||
PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
|
||||
PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
|
||||
PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
|
||||
PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
|
||||
PIN_AVB_TXCREFCLK,
|
||||
};
|
||||
static const unsigned int avb_mii_mux[] = {
|
||||
AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
|
||||
|
|
@ -3267,6 +3258,57 @@ static const unsigned int pwm6_b_mux[] = {
|
|||
PWM6_B_MARK,
|
||||
};
|
||||
|
||||
/* - QSPI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi0_ctrl_pins[] = {
|
||||
/* QSPI0_SPCLK, QSPI0_SSL */
|
||||
PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
|
||||
};
|
||||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
|
||||
};
|
||||
static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data4_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
|
||||
/* QSPI0_IO2, QSPI0_IO3 */
|
||||
PIN_QSPI0_IO2, PIN_QSPI0_IO3,
|
||||
};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
|
||||
};
|
||||
/* - QSPI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi1_ctrl_pins[] = {
|
||||
/* QSPI1_SPCLK, QSPI1_SSL */
|
||||
PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
|
||||
};
|
||||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
|
||||
/* QSPI1_IO2, QSPI1_IO3 */
|
||||
PIN_QSPI1_IO2, PIN_QSPI1_IO3,
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
|
||||
};
|
||||
|
||||
/* - SCIF0 ------------------------------------------------------------------ */
|
||||
static const unsigned int scif0_data_pins[] = {
|
||||
/* RX, TX */
|
||||
|
|
@ -3895,6 +3937,36 @@ static const unsigned int tmu_tclk2_b_mux[] = {
|
|||
TCLK2_B_MARK,
|
||||
};
|
||||
|
||||
/* - TPU ------------------------------------------------------------------- */
|
||||
static const unsigned int tpu_to0_pins[] = {
|
||||
/* TPU0TO0 */
|
||||
RCAR_GP_PIN(6, 28),
|
||||
};
|
||||
static const unsigned int tpu_to0_mux[] = {
|
||||
TPU0TO0_MARK,
|
||||
};
|
||||
static const unsigned int tpu_to1_pins[] = {
|
||||
/* TPU0TO1 */
|
||||
RCAR_GP_PIN(6, 29),
|
||||
};
|
||||
static const unsigned int tpu_to1_mux[] = {
|
||||
TPU0TO1_MARK,
|
||||
};
|
||||
static const unsigned int tpu_to2_pins[] = {
|
||||
/* TPU0TO2 */
|
||||
RCAR_GP_PIN(6, 30),
|
||||
};
|
||||
static const unsigned int tpu_to2_mux[] = {
|
||||
TPU0TO2_MARK,
|
||||
};
|
||||
static const unsigned int tpu_to3_pins[] = {
|
||||
/* TPU0TO3 */
|
||||
RCAR_GP_PIN(6, 31),
|
||||
};
|
||||
static const unsigned int tpu_to3_mux[] = {
|
||||
TPU0TO3_MARK,
|
||||
};
|
||||
|
||||
/* - USB0 ------------------------------------------------------------------- */
|
||||
static const unsigned int usb0_pins[] = {
|
||||
/* PWEN, OVC */
|
||||
|
|
@ -4114,7 +4186,7 @@ static const unsigned int vin5_clk_mux[] = {
|
|||
};
|
||||
|
||||
static const struct {
|
||||
struct sh_pfc_pin_group common[312];
|
||||
struct sh_pfc_pin_group common[322];
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A7796)
|
||||
struct sh_pfc_pin_group automotive[30];
|
||||
#endif
|
||||
|
|
@ -4319,6 +4391,12 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(pwm5_b),
|
||||
SH_PFC_PIN_GROUP(pwm6_a),
|
||||
SH_PFC_PIN_GROUP(pwm6_b),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
SH_PFC_PIN_GROUP(scif0_clk),
|
||||
SH_PFC_PIN_GROUP(scif0_ctrl),
|
||||
|
|
@ -4403,6 +4481,10 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(tmu_tclk1_b),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk2_a),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk2_b),
|
||||
SH_PFC_PIN_GROUP(tpu_to0),
|
||||
SH_PFC_PIN_GROUP(tpu_to1),
|
||||
SH_PFC_PIN_GROUP(tpu_to2),
|
||||
SH_PFC_PIN_GROUP(tpu_to3),
|
||||
SH_PFC_PIN_GROUP(usb0),
|
||||
SH_PFC_PIN_GROUP(usb1),
|
||||
SH_PFC_PIN_GROUP(usb30),
|
||||
|
|
@ -4805,6 +4887,18 @@ static const char * const pwm6_groups[] = {
|
|||
"pwm6_b",
|
||||
};
|
||||
|
||||
static const char * const qspi0_groups[] = {
|
||||
"qspi0_ctrl",
|
||||
"qspi0_data2",
|
||||
"qspi0_data4",
|
||||
};
|
||||
|
||||
static const char * const qspi1_groups[] = {
|
||||
"qspi1_ctrl",
|
||||
"qspi1_data2",
|
||||
"qspi1_data4",
|
||||
};
|
||||
|
||||
static const char * const scif0_groups[] = {
|
||||
"scif0_data",
|
||||
"scif0_clk",
|
||||
|
|
@ -4928,6 +5022,13 @@ static const char * const tmu_groups[] = {
|
|||
"tmu_tclk2_b",
|
||||
};
|
||||
|
||||
static const char * const tpu_groups[] = {
|
||||
"tpu_to0",
|
||||
"tpu_to1",
|
||||
"tpu_to2",
|
||||
"tpu_to3",
|
||||
};
|
||||
|
||||
static const char * const usb0_groups[] = {
|
||||
"usb0",
|
||||
};
|
||||
|
|
@ -4973,7 +5074,7 @@ static const char * const vin5_groups[] = {
|
|||
};
|
||||
|
||||
static const struct {
|
||||
struct sh_pfc_function common[49];
|
||||
struct sh_pfc_function common[52];
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A7796)
|
||||
struct sh_pfc_function automotive[4];
|
||||
#endif
|
||||
|
|
@ -5010,6 +5111,8 @@ static const struct {
|
|||
SH_PFC_FUNCTION(pwm4),
|
||||
SH_PFC_FUNCTION(pwm5),
|
||||
SH_PFC_FUNCTION(pwm6),
|
||||
SH_PFC_FUNCTION(qspi0),
|
||||
SH_PFC_FUNCTION(qspi1),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
SH_PFC_FUNCTION(scif2),
|
||||
|
|
@ -5023,6 +5126,7 @@ static const struct {
|
|||
SH_PFC_FUNCTION(sdhi3),
|
||||
SH_PFC_FUNCTION(ssi),
|
||||
SH_PFC_FUNCTION(tmu),
|
||||
SH_PFC_FUNCTION(tpu),
|
||||
SH_PFC_FUNCTION(usb0),
|
||||
SH_PFC_FUNCTION(usb1),
|
||||
SH_PFC_FUNCTION(usb30),
|
||||
|
|
@ -5604,44 +5708,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
|
||||
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
|
||||
{ PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
|
||||
{ PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
|
||||
{ PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
|
||||
{ PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
|
||||
{ PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
|
||||
{ PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
|
||||
{ PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
|
||||
{ PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
|
||||
{ PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
|
||||
{ PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
|
||||
{ PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
|
||||
{ PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
|
||||
{ PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
|
||||
{ PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
|
||||
{ PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
|
||||
{ PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
|
||||
{ PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
|
||||
{ PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
|
||||
{ PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
|
||||
{ PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
|
||||
{ PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
|
||||
{ PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
|
||||
{ PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
|
||||
{ PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
|
||||
{ PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
|
||||
{ PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
|
||||
{ PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
|
||||
{ PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
|
||||
{ PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
|
||||
{ PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
|
||||
{ PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
|
||||
{ PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
|
||||
{ PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
|
||||
{ PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
|
||||
{ PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
|
||||
{ PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
|
||||
{ PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
|
||||
{ PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
|
||||
{ PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
|
||||
{ PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
|
||||
{ PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
|
||||
{ PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
|
||||
{ PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
|
||||
{ PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
|
||||
{ PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
|
||||
{ PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
|
||||
{ PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
|
||||
{ PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
|
||||
{ PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
|
||||
{ PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
|
||||
{ PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
|
||||
{ PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
|
||||
{ PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
|
||||
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
|
||||
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
|
||||
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
|
||||
{ PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
|
||||
{ PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
|
||||
{ PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
|
||||
{ PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
|
||||
{ PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
|
||||
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
|
||||
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
|
||||
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
|
||||
{ RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
|
||||
|
|
@ -5695,7 +5799,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
|
||||
{ RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
|
||||
{ PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
|
||||
{ PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
|
||||
{ RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
|
||||
{ RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
|
||||
{ RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
|
||||
|
|
@ -5714,29 +5818,29 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
|
||||
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
|
||||
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
|
||||
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
|
||||
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
|
||||
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
|
||||
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
|
||||
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
|
||||
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
|
||||
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
|
||||
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
|
||||
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
|
||||
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
|
||||
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
|
||||
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
|
||||
{ PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
|
||||
{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
|
||||
{ PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */
|
||||
{ PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
|
||||
{ PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
|
||||
{ PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
|
||||
{ PIN_FSCLKST, 20, 2 }, /* FSCLKST */
|
||||
{ PIN_TMS, 4, 2 }, /* TMS */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
|
||||
{ PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
|
||||
{ PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
|
||||
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
|
||||
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
|
||||
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
|
||||
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
|
||||
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
|
||||
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
|
||||
{ PIN_TDO, 28, 2 }, /* TDO */
|
||||
{ PIN_ASEBRK, 24, 2 }, /* ASEBRK */
|
||||
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
|
||||
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
|
||||
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
|
||||
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
|
||||
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
|
||||
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
|
||||
{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
|
||||
|
|
@ -5805,7 +5909,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
|
||||
{ RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
|
||||
{ RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
|
||||
{ PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
|
||||
{ PIN_MLB_REF, 4, 3 }, /* MLB_REF */
|
||||
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
|
||||
|
|
@ -5878,35 +5982,35 @@ static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
|
|||
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
|
||||
[ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
|
||||
[ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
|
||||
[ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
|
||||
[ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
|
||||
[ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
|
||||
[ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
|
||||
[ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
|
||||
[ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
|
||||
[ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
|
||||
[ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
|
||||
[10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
|
||||
[11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
|
||||
[12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
|
||||
[13] = PIN_NUMBER('V', 6), /* RPC_WP# */
|
||||
[14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
|
||||
[15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
|
||||
[16] = PIN_NUMBER('B', 19), /* AVB_RXC */
|
||||
[17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
|
||||
[18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
|
||||
[19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
|
||||
[20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
|
||||
[21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
|
||||
[22] = PIN_NUMBER('A', 19), /* AVB_TXC */
|
||||
[23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
|
||||
[24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
|
||||
[25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
|
||||
[26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
|
||||
[27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
|
||||
[28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
|
||||
[ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
|
||||
[ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
|
||||
[ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
|
||||
[ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
|
||||
[ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
|
||||
[ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
|
||||
[ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
|
||||
[ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
|
||||
[ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
|
||||
[ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
|
||||
[10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
|
||||
[11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
|
||||
[12] = PIN_RPC_INT_N, /* RPC_INT# */
|
||||
[13] = PIN_RPC_WP_N, /* RPC_WP# */
|
||||
[14] = PIN_RPC_RESET_N, /* RPC_RESET# */
|
||||
[15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
|
||||
[16] = PIN_AVB_RXC, /* AVB_RXC */
|
||||
[17] = PIN_AVB_RD0, /* AVB_RD0 */
|
||||
[18] = PIN_AVB_RD1, /* AVB_RD1 */
|
||||
[19] = PIN_AVB_RD2, /* AVB_RD2 */
|
||||
[20] = PIN_AVB_RD3, /* AVB_RD3 */
|
||||
[21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
|
||||
[22] = PIN_AVB_TXC, /* AVB_TXC */
|
||||
[23] = PIN_AVB_TD0, /* AVB_TD0 */
|
||||
[24] = PIN_AVB_TD1, /* AVB_TD1 */
|
||||
[25] = PIN_AVB_TD2, /* AVB_TD2 */
|
||||
[26] = PIN_AVB_TD3, /* AVB_TD3 */
|
||||
[27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
|
||||
[28] = PIN_AVB_MDIO, /* AVB_MDIO */
|
||||
[29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
|
||||
[30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
|
||||
[31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
|
||||
|
|
@ -5955,7 +6059,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
|
||||
[ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
|
||||
[ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
|
||||
[ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
|
||||
[ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
|
||||
[10] = RCAR_GP_PIN(0, 0), /* D0 */
|
||||
[11] = RCAR_GP_PIN(0, 1), /* D1 */
|
||||
[12] = RCAR_GP_PIN(0, 2), /* D2 */
|
||||
|
|
@ -5976,20 +6080,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
|
||||
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
|
||||
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
|
||||
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
|
||||
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
|
||||
[30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
|
||||
[31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
|
||||
[ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
|
||||
[ 1] = PIN_NONE,
|
||||
[ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
|
||||
[ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
|
||||
[ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
|
||||
[ 5] = PIN_A_NUMBER('T', 27), /* TCK */
|
||||
[ 6] = PIN_A_NUMBER('R', 30), /* TMS */
|
||||
[ 7] = PIN_A_NUMBER('R', 29), /* TDI */
|
||||
[ 8] = PIN_NONE,
|
||||
[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
|
||||
[ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
|
||||
[ 1] = SH_PFC_PIN_NONE,
|
||||
[ 2] = PIN_FSCLKST, /* FSCLKST */
|
||||
[ 3] = PIN_EXTALR, /* EXTALR*/
|
||||
[ 4] = PIN_TRST_N, /* TRST# */
|
||||
[ 5] = PIN_TCK, /* TCK */
|
||||
[ 6] = PIN_TMS, /* TMS */
|
||||
[ 7] = PIN_TDI, /* TDI */
|
||||
[ 8] = SH_PFC_PIN_NONE,
|
||||
[ 9] = PIN_ASEBRK, /* ASEBRK */
|
||||
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
|
||||
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
|
||||
[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
|
||||
|
|
@ -6054,7 +6158,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
|
||||
[ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
|
||||
[ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
|
||||
[ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
|
||||
[ 6] = PIN_MLB_REF, /* MLB_REF */
|
||||
[ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
|
||||
[ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
|
||||
[ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
|
||||
|
|
@ -6089,31 +6193,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
|
||||
[ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
|
||||
[ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
|
||||
[ 7] = PIN_NONE,
|
||||
[ 8] = PIN_NONE,
|
||||
[ 9] = PIN_NONE,
|
||||
[10] = PIN_NONE,
|
||||
[11] = PIN_NONE,
|
||||
[12] = PIN_NONE,
|
||||
[13] = PIN_NONE,
|
||||
[14] = PIN_NONE,
|
||||
[15] = PIN_NONE,
|
||||
[16] = PIN_NONE,
|
||||
[17] = PIN_NONE,
|
||||
[18] = PIN_NONE,
|
||||
[19] = PIN_NONE,
|
||||
[20] = PIN_NONE,
|
||||
[21] = PIN_NONE,
|
||||
[22] = PIN_NONE,
|
||||
[23] = PIN_NONE,
|
||||
[24] = PIN_NONE,
|
||||
[25] = PIN_NONE,
|
||||
[26] = PIN_NONE,
|
||||
[27] = PIN_NONE,
|
||||
[28] = PIN_NONE,
|
||||
[29] = PIN_NONE,
|
||||
[30] = PIN_NONE,
|
||||
[31] = PIN_NONE,
|
||||
[ 7] = SH_PFC_PIN_NONE,
|
||||
[ 8] = SH_PFC_PIN_NONE,
|
||||
[ 9] = SH_PFC_PIN_NONE,
|
||||
[10] = SH_PFC_PIN_NONE,
|
||||
[11] = SH_PFC_PIN_NONE,
|
||||
[12] = SH_PFC_PIN_NONE,
|
||||
[13] = SH_PFC_PIN_NONE,
|
||||
[14] = SH_PFC_PIN_NONE,
|
||||
[15] = SH_PFC_PIN_NONE,
|
||||
[16] = SH_PFC_PIN_NONE,
|
||||
[17] = SH_PFC_PIN_NONE,
|
||||
[18] = SH_PFC_PIN_NONE,
|
||||
[19] = SH_PFC_PIN_NONE,
|
||||
[20] = SH_PFC_PIN_NONE,
|
||||
[21] = SH_PFC_PIN_NONE,
|
||||
[22] = SH_PFC_PIN_NONE,
|
||||
[23] = SH_PFC_PIN_NONE,
|
||||
[24] = SH_PFC_PIN_NONE,
|
||||
[25] = SH_PFC_PIN_NONE,
|
||||
[26] = SH_PFC_PIN_NONE,
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
|
||||
* Copyright (C) 2016-2019 Renesas Electronics Corp.
|
||||
*
|
||||
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
|
||||
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
|
||||
*
|
||||
* R-Car Gen3 processor support - PFC hardware block.
|
||||
*
|
||||
|
|
@ -20,11 +20,9 @@
|
|||
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
|
||||
SH_PFC_PIN_CFG_PULL_UP | \
|
||||
SH_PFC_PIN_CFG_PULL_DOWN)
|
||||
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
||||
#define CPU_ALL_PORT(fn, sfx) \
|
||||
#define CPU_ALL_GP(fn, sfx) \
|
||||
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
|
||||
|
|
@ -37,6 +35,51 @@
|
|||
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
|
||||
|
||||
#define CPU_ALL_NOGP(fn) \
|
||||
PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
|
||||
PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
||||
/*
|
||||
* F_() : just information
|
||||
* FM() : macro for FN_xxx / xxx_MARK
|
||||
|
|
@ -1519,67 +1562,16 @@ static const u16 pinmux_data[] = {
|
|||
};
|
||||
|
||||
/*
|
||||
* R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
|
||||
* Physical layout rows: A - AW, cols: 1 - 39.
|
||||
* Pins not associated with a GPIO port.
|
||||
*/
|
||||
#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
|
||||
#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
|
||||
#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
|
||||
#define PIN_NONE U16_MAX
|
||||
enum {
|
||||
GP_ASSIGN_LAST(),
|
||||
NOGP_ALL(),
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
PINMUX_GPIO_GP_ALL(),
|
||||
|
||||
/*
|
||||
* Pins not associated with a GPIO port.
|
||||
*
|
||||
* The pin positions are different between different r8a77965
|
||||
* packages, all that is needed for the pfc driver is a unique
|
||||
* number for each pin. To this end use the pin layout from
|
||||
* R-Car M3SiP to calculate a unique number for each pin.
|
||||
*/
|
||||
SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
|
||||
PINMUX_NOGP_ALL(),
|
||||
};
|
||||
|
||||
/* - AUDIO CLOCK ------------------------------------------------------------ */
|
||||
|
|
@ -1728,7 +1720,7 @@ static const unsigned int avb_phy_int_mux[] = {
|
|||
};
|
||||
static const unsigned int avb_mdio_pins[] = {
|
||||
/* AVB_MDC, AVB_MDIO */
|
||||
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
|
||||
RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
|
||||
};
|
||||
static const unsigned int avb_mdio_mux[] = {
|
||||
AVB_MDC_MARK, AVB_MDIO_MARK,
|
||||
|
|
@ -1741,12 +1733,11 @@ static const unsigned int avb_mii_pins[] = {
|
|||
* AVB_RD1, AVB_RD2, AVB_RD3,
|
||||
* AVB_TXCREFCLK
|
||||
*/
|
||||
PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
|
||||
PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
|
||||
PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
|
||||
PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
|
||||
PIN_NUMBER('A', 12),
|
||||
|
||||
PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
|
||||
PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
|
||||
PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
|
||||
PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
|
||||
PIN_AVB_TXCREFCLK,
|
||||
};
|
||||
static const unsigned int avb_mii_mux[] = {
|
||||
AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
|
||||
|
|
@ -3418,6 +3409,57 @@ static const unsigned int pwm6_b_mux[] = {
|
|||
PWM6_B_MARK,
|
||||
};
|
||||
|
||||
/* - QSPI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi0_ctrl_pins[] = {
|
||||
/* QSPI0_SPCLK, QSPI0_SSL */
|
||||
PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
|
||||
};
|
||||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
|
||||
};
|
||||
static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data4_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
|
||||
/* QSPI0_IO2, QSPI0_IO3 */
|
||||
PIN_QSPI0_IO2, PIN_QSPI0_IO3,
|
||||
};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
|
||||
};
|
||||
/* - QSPI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi1_ctrl_pins[] = {
|
||||
/* QSPI1_SPCLK, QSPI1_SSL */
|
||||
PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
|
||||
};
|
||||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
|
||||
/* QSPI1_IO2, QSPI1_IO3 */
|
||||
PIN_QSPI1_IO2, PIN_QSPI1_IO3,
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
|
||||
};
|
||||
|
||||
/* - SATA --------------------------------------------------------------------*/
|
||||
static const unsigned int sata0_devslp_a_pins[] = {
|
||||
/* DEVSLP */
|
||||
|
|
@ -4391,7 +4433,7 @@ static const unsigned int vin5_clk_mux[] = {
|
|||
};
|
||||
|
||||
static const struct {
|
||||
struct sh_pfc_pin_group common[318];
|
||||
struct sh_pfc_pin_group common[324];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77965
|
||||
struct sh_pfc_pin_group automotive[30];
|
||||
#endif
|
||||
|
|
@ -4596,6 +4638,12 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(pwm5_b),
|
||||
SH_PFC_PIN_GROUP(pwm6_a),
|
||||
SH_PFC_PIN_GROUP(pwm6_b),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
SH_PFC_PIN_GROUP(sata0_devslp_a),
|
||||
SH_PFC_PIN_GROUP(sata0_devslp_b),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
|
|
@ -5088,6 +5136,18 @@ static const char * const pwm6_groups[] = {
|
|||
"pwm6_b",
|
||||
};
|
||||
|
||||
static const char * const qspi0_groups[] = {
|
||||
"qspi0_ctrl",
|
||||
"qspi0_data2",
|
||||
"qspi0_data4",
|
||||
};
|
||||
|
||||
static const char * const qspi1_groups[] = {
|
||||
"qspi1_ctrl",
|
||||
"qspi1_data2",
|
||||
"qspi1_data4",
|
||||
};
|
||||
|
||||
static const char * const sata0_groups[] = {
|
||||
"sata0_devslp_a",
|
||||
"sata0_devslp_b",
|
||||
|
|
@ -5267,7 +5327,7 @@ static const char * const vin5_groups[] = {
|
|||
};
|
||||
|
||||
static const struct {
|
||||
struct sh_pfc_function common[51];
|
||||
struct sh_pfc_function common[53];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77965
|
||||
struct sh_pfc_function automotive[4];
|
||||
#endif
|
||||
|
|
@ -5304,6 +5364,8 @@ static const struct {
|
|||
SH_PFC_FUNCTION(pwm4),
|
||||
SH_PFC_FUNCTION(pwm5),
|
||||
SH_PFC_FUNCTION(pwm6),
|
||||
SH_PFC_FUNCTION(qspi0),
|
||||
SH_PFC_FUNCTION(qspi1),
|
||||
SH_PFC_FUNCTION(sata0),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
|
|
@ -5900,44 +5962,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
|
||||
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
|
||||
{ PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
|
||||
{ PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
|
||||
{ PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
|
||||
{ PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
|
||||
{ PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
|
||||
{ PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
|
||||
{ PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
|
||||
{ PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
|
||||
{ PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
|
||||
{ PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
|
||||
{ PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
|
||||
{ PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
|
||||
{ PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
|
||||
{ PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
|
||||
{ PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
|
||||
{ PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
|
||||
{ PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
|
||||
{ PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
|
||||
{ PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
|
||||
{ PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
|
||||
{ PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
|
||||
{ PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
|
||||
{ PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
|
||||
{ PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
|
||||
{ PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
|
||||
{ PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
|
||||
{ PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
|
||||
{ PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
|
||||
{ PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
|
||||
{ PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
|
||||
{ PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
|
||||
{ PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
|
||||
{ PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
|
||||
{ PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
|
||||
{ PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
|
||||
{ PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
|
||||
{ PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
|
||||
{ PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
|
||||
{ PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
|
||||
{ PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
|
||||
{ PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
|
||||
{ PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
|
||||
{ PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
|
||||
{ PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
|
||||
{ PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
|
||||
{ PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
|
||||
{ PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
|
||||
{ PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
|
||||
{ PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
|
||||
{ PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
|
||||
{ PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
|
||||
{ PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
|
||||
{ PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
|
||||
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
|
||||
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
|
||||
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
|
||||
{ PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
|
||||
{ PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
|
||||
{ PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
|
||||
{ PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
|
||||
{ PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
|
||||
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
|
||||
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
|
||||
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
|
||||
{ RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
|
||||
|
|
@ -5991,7 +6053,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
|
||||
{ RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
|
||||
{ PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
|
||||
{ PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
|
||||
{ RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
|
||||
{ RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
|
||||
{ RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
|
||||
|
|
@ -6010,29 +6072,29 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
|
||||
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
|
||||
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
|
||||
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
|
||||
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
|
||||
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
|
||||
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
|
||||
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
|
||||
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
|
||||
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
|
||||
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
|
||||
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
|
||||
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
|
||||
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
|
||||
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
|
||||
{ PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
|
||||
{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
|
||||
{ PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN3 */
|
||||
{ PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
|
||||
{ PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
|
||||
{ PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
|
||||
{ PIN_FSCLKST, 20, 2 }, /* FSCLKST */
|
||||
{ PIN_TMS, 4, 2 }, /* TMS */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
|
||||
{ PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
|
||||
{ PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
|
||||
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
|
||||
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
|
||||
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
|
||||
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
|
||||
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
|
||||
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
|
||||
{ PIN_TDO, 28, 2 }, /* TDO */
|
||||
{ PIN_ASEBRK, 24, 2 }, /* ASEBRK */
|
||||
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
|
||||
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
|
||||
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
|
||||
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
|
||||
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
|
||||
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
|
||||
{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
|
||||
|
|
@ -6101,7 +6163,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
|
||||
{ RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
|
||||
{ RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
|
||||
{ PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
|
||||
{ PIN_MLB_REF, 4, 3 }, /* MLB_REF */
|
||||
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
|
||||
|
|
@ -6174,35 +6236,35 @@ static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po
|
|||
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
|
||||
[ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
|
||||
[ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
|
||||
[ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
|
||||
[ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
|
||||
[ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
|
||||
[ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
|
||||
[ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
|
||||
[ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
|
||||
[ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
|
||||
[ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
|
||||
[10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
|
||||
[11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
|
||||
[12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
|
||||
[13] = PIN_NUMBER('V', 6), /* RPC_WP# */
|
||||
[14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
|
||||
[15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
|
||||
[16] = PIN_NUMBER('B', 19), /* AVB_RXC */
|
||||
[17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
|
||||
[18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
|
||||
[19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
|
||||
[20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
|
||||
[21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
|
||||
[22] = PIN_NUMBER('A', 19), /* AVB_TXC */
|
||||
[23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
|
||||
[24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
|
||||
[25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
|
||||
[26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
|
||||
[27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
|
||||
[28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
|
||||
[ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
|
||||
[ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
|
||||
[ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
|
||||
[ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
|
||||
[ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
|
||||
[ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
|
||||
[ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
|
||||
[ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
|
||||
[ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
|
||||
[ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
|
||||
[10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
|
||||
[11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
|
||||
[12] = PIN_RPC_INT_N, /* RPC_INT# */
|
||||
[13] = PIN_RPC_WP_N, /* RPC_WP# */
|
||||
[14] = PIN_RPC_RESET_N, /* RPC_RESET# */
|
||||
[15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
|
||||
[16] = PIN_AVB_RXC, /* AVB_RXC */
|
||||
[17] = PIN_AVB_RD0, /* AVB_RD0 */
|
||||
[18] = PIN_AVB_RD1, /* AVB_RD1 */
|
||||
[19] = PIN_AVB_RD2, /* AVB_RD2 */
|
||||
[20] = PIN_AVB_RD3, /* AVB_RD3 */
|
||||
[21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
|
||||
[22] = PIN_AVB_TXC, /* AVB_TXC */
|
||||
[23] = PIN_AVB_TD0, /* AVB_TD0 */
|
||||
[24] = PIN_AVB_TD1, /* AVB_TD1 */
|
||||
[25] = PIN_AVB_TD2, /* AVB_TD2 */
|
||||
[26] = PIN_AVB_TD3, /* AVB_TD3 */
|
||||
[27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
|
||||
[28] = PIN_AVB_MDIO, /* AVB_MDIO */
|
||||
[29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
|
||||
[30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
|
||||
[31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
|
||||
|
|
@ -6251,7 +6313,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
|
||||
[ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
|
||||
[ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
|
||||
[ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
|
||||
[ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
|
||||
[10] = RCAR_GP_PIN(0, 0), /* D0 */
|
||||
[11] = RCAR_GP_PIN(0, 1), /* D1 */
|
||||
[12] = RCAR_GP_PIN(0, 2), /* D2 */
|
||||
|
|
@ -6272,20 +6334,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
|
||||
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
|
||||
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
|
||||
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
|
||||
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
|
||||
[30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
|
||||
[31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
|
||||
[ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
|
||||
[ 1] = PIN_NONE,
|
||||
[ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
|
||||
[ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
|
||||
[ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
|
||||
[ 5] = PIN_A_NUMBER('T', 27), /* TCK */
|
||||
[ 6] = PIN_A_NUMBER('R', 30), /* TMS */
|
||||
[ 7] = PIN_A_NUMBER('R', 29), /* TDI */
|
||||
[ 8] = PIN_NONE,
|
||||
[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
|
||||
[ 0] = SH_PFC_PIN_NONE,
|
||||
[ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
|
||||
[ 2] = PIN_FSCLKST, /* FSCLKST */
|
||||
[ 3] = PIN_EXTALR, /* EXTALR*/
|
||||
[ 4] = PIN_TRST_N, /* TRST# */
|
||||
[ 5] = PIN_TCK, /* TCK */
|
||||
[ 6] = PIN_TMS, /* TMS */
|
||||
[ 7] = PIN_TDI, /* TDI */
|
||||
[ 8] = SH_PFC_PIN_NONE,
|
||||
[ 9] = PIN_ASEBRK, /* ASEBRK */
|
||||
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
|
||||
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
|
||||
[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
|
||||
|
|
@ -6350,7 +6412,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
|
||||
[ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
|
||||
[ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
|
||||
[ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
|
||||
[ 6] = PIN_MLB_REF, /* MLB_REF */
|
||||
[ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
|
||||
[ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
|
||||
[ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
|
||||
|
|
@ -6385,31 +6447,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
|
||||
[ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
|
||||
[ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
|
||||
[ 7] = PIN_NONE,
|
||||
[ 8] = PIN_NONE,
|
||||
[ 9] = PIN_NONE,
|
||||
[10] = PIN_NONE,
|
||||
[11] = PIN_NONE,
|
||||
[12] = PIN_NONE,
|
||||
[13] = PIN_NONE,
|
||||
[14] = PIN_NONE,
|
||||
[15] = PIN_NONE,
|
||||
[16] = PIN_NONE,
|
||||
[17] = PIN_NONE,
|
||||
[18] = PIN_NONE,
|
||||
[19] = PIN_NONE,
|
||||
[20] = PIN_NONE,
|
||||
[21] = PIN_NONE,
|
||||
[22] = PIN_NONE,
|
||||
[23] = PIN_NONE,
|
||||
[24] = PIN_NONE,
|
||||
[25] = PIN_NONE,
|
||||
[26] = PIN_NONE,
|
||||
[27] = PIN_NONE,
|
||||
[28] = PIN_NONE,
|
||||
[29] = PIN_NONE,
|
||||
[30] = PIN_NONE,
|
||||
[31] = PIN_NONE,
|
||||
[ 7] = SH_PFC_PIN_NONE,
|
||||
[ 8] = SH_PFC_PIN_NONE,
|
||||
[ 9] = SH_PFC_PIN_NONE,
|
||||
[10] = SH_PFC_PIN_NONE,
|
||||
[11] = SH_PFC_PIN_NONE,
|
||||
[12] = SH_PFC_PIN_NONE,
|
||||
[13] = SH_PFC_PIN_NONE,
|
||||
[14] = SH_PFC_PIN_NONE,
|
||||
[15] = SH_PFC_PIN_NONE,
|
||||
[16] = SH_PFC_PIN_NONE,
|
||||
[17] = SH_PFC_PIN_NONE,
|
||||
[18] = SH_PFC_PIN_NONE,
|
||||
[19] = SH_PFC_PIN_NONE,
|
||||
[20] = SH_PFC_PIN_NONE,
|
||||
[21] = SH_PFC_PIN_NONE,
|
||||
[22] = SH_PFC_PIN_NONE,
|
||||
[23] = SH_PFC_PIN_NONE,
|
||||
[24] = SH_PFC_PIN_NONE,
|
||||
[25] = SH_PFC_PIN_NONE,
|
||||
[26] = SH_PFC_PIN_NONE,
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
|
||||
*
|
||||
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
|
||||
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
|
||||
*
|
||||
* R-Car Gen3 processor support - PFC hardware block.
|
||||
*
|
||||
|
|
@ -20,7 +20,7 @@
|
|||
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CPU_ALL_PORT(fn, sfx) \
|
||||
#define CPU_ALL_GP(fn, sfx) \
|
||||
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_28(1, fn, sfx), \
|
||||
PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
|
|
@ -206,8 +206,8 @@
|
|||
#define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
|
@ -632,14 +632,12 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
|
||||
PINMUX_IPSR_GPSR(IP6_31_28, IRQ4),
|
||||
PINMUX_IPSR_GPSR(IP6_31_28, D14),
|
||||
PINMUX_IPSR_GPSR(IP6_31_28, MMC_WP),
|
||||
|
||||
/* IPSR7 */
|
||||
PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
|
||||
PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
|
||||
PINMUX_IPSR_GPSR(IP7_3_0, IRQ5),
|
||||
PINMUX_IPSR_GPSR(IP7_3_0, D15),
|
||||
PINMUX_IPSR_GPSR(IP7_3_0, MMC_CD),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
|
||||
PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0),
|
||||
|
|
@ -1122,20 +1120,6 @@ static const unsigned int mmc_ctrl_pins[] = {
|
|||
static const unsigned int mmc_ctrl_mux[] = {
|
||||
MMC_CLK_MARK, MMC_CMD_MARK,
|
||||
};
|
||||
static const unsigned int mmc_cd_pins[] = {
|
||||
/* CD */
|
||||
RCAR_GP_PIN(3, 16),
|
||||
};
|
||||
static const unsigned int mmc_cd_mux[] = {
|
||||
MMC_CD_MARK,
|
||||
};
|
||||
static const unsigned int mmc_wp_pins[] = {
|
||||
/* WP */
|
||||
RCAR_GP_PIN(3, 15),
|
||||
};
|
||||
static const unsigned int mmc_wp_mux[] = {
|
||||
MMC_WP_MARK,
|
||||
};
|
||||
|
||||
/* - MSIOF0 ----------------------------------------------------------------- */
|
||||
static const unsigned int msiof0_clk_pins[] = {
|
||||
|
|
@ -1433,6 +1417,64 @@ static const unsigned int qspi1_data4_mux[] = {
|
|||
QSPI1_IO2_MARK, QSPI1_IO3_MARK
|
||||
};
|
||||
|
||||
/* - RPC -------------------------------------------------------------------- */
|
||||
static const unsigned int rpc_clk1_pins[] = {
|
||||
/* Octal-SPI flash: C/SCLK */
|
||||
RCAR_GP_PIN(5, 0),
|
||||
};
|
||||
static const unsigned int rpc_clk1_mux[] = {
|
||||
QSPI0_SPCLK_MARK,
|
||||
};
|
||||
static const unsigned int rpc_clk2_pins[] = {
|
||||
/* HyperFlash: CK, CK# */
|
||||
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
|
||||
};
|
||||
static const unsigned int rpc_clk2_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
|
||||
};
|
||||
static const unsigned int rpc_ctrl_pins[] = {
|
||||
/* Octal-SPI flash: S#/CS, DQS */
|
||||
/* HyperFlash: CS#, RDS */
|
||||
RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
|
||||
};
|
||||
static const unsigned int rpc_ctrl_mux[] = {
|
||||
QSPI0_SSL_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int rpc_data_pins[] = {
|
||||
/* DQ[0:7] */
|
||||
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
|
||||
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
|
||||
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
|
||||
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
|
||||
};
|
||||
static const unsigned int rpc_data_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
|
||||
};
|
||||
static const unsigned int rpc_reset_pins[] = {
|
||||
/* RPC_RESET# */
|
||||
RCAR_GP_PIN(5, 12),
|
||||
};
|
||||
static const unsigned int rpc_reset_mux[] = {
|
||||
RPC_RESET_N_MARK,
|
||||
};
|
||||
static const unsigned int rpc_int_pins[] = {
|
||||
/* RPC_INT# */
|
||||
RCAR_GP_PIN(5, 14),
|
||||
};
|
||||
static const unsigned int rpc_int_mux[] = {
|
||||
RPC_INT_N_MARK,
|
||||
};
|
||||
static const unsigned int rpc_wp_pins[] = {
|
||||
/* RPC_WP# */
|
||||
RCAR_GP_PIN(5, 13),
|
||||
};
|
||||
static const unsigned int rpc_wp_mux[] = {
|
||||
RPC_WP_N_MARK,
|
||||
};
|
||||
|
||||
/* - SCIF Clock ------------------------------------------------------------- */
|
||||
static const unsigned int scif_clk_a_pins[] = {
|
||||
/* SCIF_CLK */
|
||||
|
|
@ -1727,8 +1769,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(mmc_data4),
|
||||
SH_PFC_PIN_GROUP(mmc_data8),
|
||||
SH_PFC_PIN_GROUP(mmc_ctrl),
|
||||
SH_PFC_PIN_GROUP(mmc_cd),
|
||||
SH_PFC_PIN_GROUP(mmc_wp),
|
||||
SH_PFC_PIN_GROUP(msiof0_clk),
|
||||
SH_PFC_PIN_GROUP(msiof0_sync),
|
||||
SH_PFC_PIN_GROUP(msiof0_ss1),
|
||||
|
|
@ -1769,6 +1809,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
SH_PFC_PIN_GROUP(rpc_clk1),
|
||||
SH_PFC_PIN_GROUP(rpc_clk2),
|
||||
SH_PFC_PIN_GROUP(rpc_ctrl),
|
||||
SH_PFC_PIN_GROUP(rpc_data),
|
||||
SH_PFC_PIN_GROUP(rpc_reset),
|
||||
SH_PFC_PIN_GROUP(rpc_int),
|
||||
SH_PFC_PIN_GROUP(rpc_wp),
|
||||
SH_PFC_PIN_GROUP(scif_clk_a),
|
||||
SH_PFC_PIN_GROUP(scif_clk_b),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
|
|
@ -1898,8 +1945,6 @@ static const char * const mmc_groups[] = {
|
|||
"mmc_data4",
|
||||
"mmc_data8",
|
||||
"mmc_ctrl",
|
||||
"mmc_cd",
|
||||
"mmc_wp",
|
||||
};
|
||||
|
||||
static const char * const msiof0_groups[] = {
|
||||
|
|
@ -1975,6 +2020,16 @@ static const char * const qspi1_groups[] = {
|
|||
"qspi1_data4",
|
||||
};
|
||||
|
||||
static const char * const rpc_groups[] = {
|
||||
"rpc_clk1",
|
||||
"rpc_clk2",
|
||||
"rpc_ctrl",
|
||||
"rpc_data",
|
||||
"rpc_reset",
|
||||
"rpc_int",
|
||||
"rpc_wp",
|
||||
};
|
||||
|
||||
static const char * const scif_clk_groups[] = {
|
||||
"scif_clk_a",
|
||||
"scif_clk_b",
|
||||
|
|
@ -2060,6 +2115,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
SH_PFC_FUNCTION(pwm4),
|
||||
SH_PFC_FUNCTION(qspi0),
|
||||
SH_PFC_FUNCTION(qspi1),
|
||||
SH_PFC_FUNCTION(rpc),
|
||||
SH_PFC_FUNCTION(scif_clk),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
* Copyright (C) 2018 Cogent Embedded, Inc.
|
||||
*
|
||||
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
|
||||
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
|
||||
*
|
||||
* R-Car Gen3 processor support - PFC hardware block.
|
||||
*
|
||||
|
|
@ -20,7 +20,7 @@
|
|||
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CPU_ALL_PORT(fn, sfx) \
|
||||
#define CPU_ALL_GP(fn, sfx) \
|
||||
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_28(1, fn, sfx), \
|
||||
PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
|
|
@ -1711,6 +1711,64 @@ static const unsigned int qspi1_data4_mux[] = {
|
|||
QSPI1_IO2_MARK, QSPI1_IO3_MARK
|
||||
};
|
||||
|
||||
/* - RPC -------------------------------------------------------------------- */
|
||||
static const unsigned int rpc_clk1_pins[] = {
|
||||
/* Octal-SPI flash: C/SCLK */
|
||||
RCAR_GP_PIN(5, 0),
|
||||
};
|
||||
static const unsigned int rpc_clk1_mux[] = {
|
||||
QSPI0_SPCLK_MARK,
|
||||
};
|
||||
static const unsigned int rpc_clk2_pins[] = {
|
||||
/* HyperFlash: CK, CK# */
|
||||
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
|
||||
};
|
||||
static const unsigned int rpc_clk2_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
|
||||
};
|
||||
static const unsigned int rpc_ctrl_pins[] = {
|
||||
/* Octal-SPI flash: S#/CS, DQS */
|
||||
/* HyperFlash: CS#, RDS */
|
||||
RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
|
||||
};
|
||||
static const unsigned int rpc_ctrl_mux[] = {
|
||||
QSPI0_SSL_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int rpc_data_pins[] = {
|
||||
/* DQ[0:7] */
|
||||
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
|
||||
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
|
||||
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
|
||||
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
|
||||
};
|
||||
static const unsigned int rpc_data_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
|
||||
};
|
||||
static const unsigned int rpc_reset_pins[] = {
|
||||
/* RPC_RESET# */
|
||||
RCAR_GP_PIN(5, 12),
|
||||
};
|
||||
static const unsigned int rpc_reset_mux[] = {
|
||||
RPC_RESET_N_MARK,
|
||||
};
|
||||
static const unsigned int rpc_int_pins[] = {
|
||||
/* RPC_INT# */
|
||||
RCAR_GP_PIN(5, 14),
|
||||
};
|
||||
static const unsigned int rpc_int_mux[] = {
|
||||
RPC_INT_N_MARK,
|
||||
};
|
||||
static const unsigned int rpc_wp_pins[] = {
|
||||
/* RPC_WP# */
|
||||
RCAR_GP_PIN(5, 13),
|
||||
};
|
||||
static const unsigned int rpc_wp_mux[] = {
|
||||
RPC_WP_N_MARK,
|
||||
};
|
||||
|
||||
/* - SCIF0 ------------------------------------------------------------------ */
|
||||
static const unsigned int scif0_data_pins[] = {
|
||||
/* RX0, TX0 */
|
||||
|
|
@ -2127,6 +2185,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
SH_PFC_PIN_GROUP(rpc_clk1),
|
||||
SH_PFC_PIN_GROUP(rpc_clk2),
|
||||
SH_PFC_PIN_GROUP(rpc_ctrl),
|
||||
SH_PFC_PIN_GROUP(rpc_data),
|
||||
SH_PFC_PIN_GROUP(rpc_reset),
|
||||
SH_PFC_PIN_GROUP(rpc_int),
|
||||
SH_PFC_PIN_GROUP(rpc_wp),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
SH_PFC_PIN_GROUP(scif0_clk),
|
||||
SH_PFC_PIN_GROUP(scif0_ctrl),
|
||||
|
|
@ -2363,6 +2428,16 @@ static const char * const qspi1_groups[] = {
|
|||
"qspi1_data4",
|
||||
};
|
||||
|
||||
static const char * const rpc_groups[] = {
|
||||
"rpc_clk1",
|
||||
"rpc_clk2",
|
||||
"rpc_ctrl",
|
||||
"rpc_data",
|
||||
"rpc_reset",
|
||||
"rpc_int",
|
||||
"rpc_wp",
|
||||
};
|
||||
|
||||
static const char * const scif0_groups[] = {
|
||||
"scif0_data",
|
||||
"scif0_clk",
|
||||
|
|
@ -2461,6 +2536,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
SH_PFC_FUNCTION(pwm4),
|
||||
SH_PFC_FUNCTION(qspi0),
|
||||
SH_PFC_FUNCTION(qspi1),
|
||||
SH_PFC_FUNCTION(rpc),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
SH_PFC_FUNCTION(scif3),
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*
|
||||
* Copyright (C) 2018-2019 Renesas Electronics Corp.
|
||||
*
|
||||
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
|
||||
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
|
||||
*
|
||||
* R8A7796 processor support - PFC hardware block.
|
||||
*
|
||||
|
|
@ -20,10 +20,9 @@
|
|||
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \
|
||||
SH_PFC_PIN_CFG_PULL_DOWN)
|
||||
#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
||||
#define CPU_ALL_PORT(fn, sfx) \
|
||||
#define CPU_ALL_GP(fn, sfx) \
|
||||
PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
|
||||
|
|
@ -44,6 +43,25 @@
|
|||
PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)
|
||||
|
||||
#define CPU_ALL_NOGP(fn) \
|
||||
PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS)
|
||||
|
||||
/*
|
||||
* F_() : just information
|
||||
* FM() : macro for FN_xxx / xxx_MARK
|
||||
|
|
@ -1283,41 +1301,16 @@ static const u16 pinmux_data[] = {
|
|||
};
|
||||
|
||||
/*
|
||||
* R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs.
|
||||
* Physical layout rows: A - AE, cols: 1 - 25.
|
||||
* Pins not associated with a GPIO port.
|
||||
*/
|
||||
#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
|
||||
#define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300)
|
||||
#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
|
||||
#define PIN_NONE U16_MAX
|
||||
enum {
|
||||
GP_ASSIGN_LAST(),
|
||||
NOGP_ALL(),
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
PINMUX_GPIO_GP_ALL(),
|
||||
|
||||
/*
|
||||
* Pins not associated with a GPIO port.
|
||||
*
|
||||
* The pin positions are different between different R8A77990
|
||||
* packages, all that is needed for the pfc driver is a unique
|
||||
* number for each pin. To this end use the pin layout from
|
||||
* R8A77990 to calculate a unique number for each pin.
|
||||
*/
|
||||
SH_PFC_PIN_NAMED_CFG('F', 1, TRST_N, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('F', 3, TMS, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('F', 4, TCK, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('G', 2, TDI, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('G', 3, FSCLKST_N, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('H', 1, ASEBRK, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('N', 1, AVB_TXC, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('N', 2, AVB_TD0, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('N', 3, AVB_TD1, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('N', 5, AVB_TD2, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('N', 6, AVB_TD3, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('P', 3, AVB_TX_CTL, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('P', 4, AVB_MDIO, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('P', 5, AVB_MDC, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF, CFG_FLAGS),
|
||||
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
|
||||
PINMUX_NOGP_ALL(),
|
||||
};
|
||||
|
||||
/* - AUDIO CLOCK ------------------------------------------------------------ */
|
||||
|
|
@ -5115,15 +5108,15 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[0] = RCAR_GP_PIN(2, 23), /* RD# */
|
||||
[1] = RCAR_GP_PIN(2, 22), /* BS# */
|
||||
[2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */
|
||||
[3] = PIN_NUMBER('P', 5), /* AVB_MDC */
|
||||
[4] = PIN_NUMBER('P', 4), /* AVB_MDIO */
|
||||
[3] = PIN_AVB_MDC, /* AVB_MDC */
|
||||
[4] = PIN_AVB_MDIO, /* AVB_MDIO */
|
||||
[5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */
|
||||
[6] = PIN_NUMBER('N', 6), /* AVB_TD3 */
|
||||
[7] = PIN_NUMBER('N', 5), /* AVB_TD2 */
|
||||
[8] = PIN_NUMBER('N', 3), /* AVB_TD1 */
|
||||
[9] = PIN_NUMBER('N', 2), /* AVB_TD0 */
|
||||
[10] = PIN_NUMBER('N', 1), /* AVB_TXC */
|
||||
[11] = PIN_NUMBER('P', 3), /* AVB_TX_CTL */
|
||||
[6] = PIN_AVB_TD3, /* AVB_TD3 */
|
||||
[7] = PIN_AVB_TD2, /* AVB_TD2 */
|
||||
[8] = PIN_AVB_TD1, /* AVB_TD1 */
|
||||
[9] = PIN_AVB_TD0, /* AVB_TD0 */
|
||||
[10] = PIN_AVB_TXC, /* AVB_TXC */
|
||||
[11] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
|
||||
[12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */
|
||||
[13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */
|
||||
[14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */
|
||||
|
|
@ -5174,33 +5167,33 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[25] = RCAR_GP_PIN(1, 2), /* A2 */
|
||||
[26] = RCAR_GP_PIN(1, 1), /* A1 */
|
||||
[27] = RCAR_GP_PIN(1, 0), /* A0 */
|
||||
[28] = PIN_NONE,
|
||||
[29] = PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */
|
||||
[31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
|
||||
[0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
|
||||
[1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
|
||||
[2] = PIN_NUMBER('H', 1), /* ASEBRK */
|
||||
[3] = PIN_NONE,
|
||||
[4] = PIN_NUMBER('G', 2), /* TDI */
|
||||
[5] = PIN_NUMBER('F', 3), /* TMS */
|
||||
[6] = PIN_NUMBER('F', 4), /* TCK */
|
||||
[7] = PIN_NUMBER('F', 1), /* TRST# */
|
||||
[8] = PIN_NONE,
|
||||
[9] = PIN_NONE,
|
||||
[10] = PIN_NONE,
|
||||
[11] = PIN_NONE,
|
||||
[12] = PIN_NONE,
|
||||
[13] = PIN_NONE,
|
||||
[14] = PIN_NONE,
|
||||
[15] = PIN_NUMBER('G', 3), /* FSCLKST# */
|
||||
[2] = PIN_ASEBRK, /* ASEBRK */
|
||||
[3] = SH_PFC_PIN_NONE,
|
||||
[4] = PIN_TDI, /* TDI */
|
||||
[5] = PIN_TMS, /* TMS */
|
||||
[6] = PIN_TCK, /* TCK */
|
||||
[7] = PIN_TRST_N, /* TRST# */
|
||||
[8] = SH_PFC_PIN_NONE,
|
||||
[9] = SH_PFC_PIN_NONE,
|
||||
[10] = SH_PFC_PIN_NONE,
|
||||
[11] = SH_PFC_PIN_NONE,
|
||||
[12] = SH_PFC_PIN_NONE,
|
||||
[13] = SH_PFC_PIN_NONE,
|
||||
[14] = SH_PFC_PIN_NONE,
|
||||
[15] = PIN_FSCLKST_N, /* FSCLKST# */
|
||||
[16] = RCAR_GP_PIN(0, 17), /* SDA4 */
|
||||
[17] = RCAR_GP_PIN(0, 16), /* SCL4 */
|
||||
[18] = PIN_NONE,
|
||||
[19] = PIN_NONE,
|
||||
[20] = PIN_A_NUMBER('D', 3), /* PRESETOUT# */
|
||||
[18] = SH_PFC_PIN_NONE,
|
||||
[19] = SH_PFC_PIN_NONE,
|
||||
[20] = PIN_PRESETOUT_N, /* PRESETOUT# */
|
||||
[21] = RCAR_GP_PIN(0, 15), /* D15 */
|
||||
[22] = RCAR_GP_PIN(0, 14), /* D14 */
|
||||
[23] = RCAR_GP_PIN(0, 13), /* D13 */
|
||||
|
|
@ -5219,8 +5212,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */
|
||||
[3] = RCAR_GP_PIN(5, 2), /* TX0_A */
|
||||
[4] = RCAR_GP_PIN(5, 1), /* RX0_A */
|
||||
[5] = PIN_NONE,
|
||||
[6] = PIN_NONE,
|
||||
[5] = SH_PFC_PIN_NONE,
|
||||
[6] = SH_PFC_PIN_NONE,
|
||||
[7] = RCAR_GP_PIN(3, 15), /* SD1_WP */
|
||||
[8] = RCAR_GP_PIN(3, 14), /* SD1_CD */
|
||||
[9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
|
||||
|
|
@ -5264,7 +5257,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
|
||||
[14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
|
||||
[15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
|
||||
[16] = PIN_NUMBER('T', 21), /* MLB_REF */
|
||||
[16] = PIN_MLB_REF, /* MLB_REF */
|
||||
[17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */
|
||||
[18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */
|
||||
[19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */
|
||||
|
|
@ -5282,36 +5275,36 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[31] = RCAR_GP_PIN(5, 5), /* RX1 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
|
||||
[0] = PIN_NONE,
|
||||
[1] = PIN_NONE,
|
||||
[2] = PIN_NONE,
|
||||
[3] = PIN_NONE,
|
||||
[4] = PIN_NONE,
|
||||
[5] = PIN_NONE,
|
||||
[6] = PIN_NONE,
|
||||
[7] = PIN_NONE,
|
||||
[8] = PIN_NONE,
|
||||
[9] = PIN_NONE,
|
||||
[10] = PIN_NONE,
|
||||
[11] = PIN_NONE,
|
||||
[12] = PIN_NONE,
|
||||
[13] = PIN_NONE,
|
||||
[14] = PIN_NONE,
|
||||
[15] = PIN_NONE,
|
||||
[16] = PIN_NONE,
|
||||
[17] = PIN_NONE,
|
||||
[18] = PIN_NONE,
|
||||
[19] = PIN_NONE,
|
||||
[20] = PIN_NONE,
|
||||
[21] = PIN_NONE,
|
||||
[22] = PIN_NONE,
|
||||
[23] = PIN_NONE,
|
||||
[24] = PIN_NONE,
|
||||
[25] = PIN_NONE,
|
||||
[26] = PIN_NONE,
|
||||
[27] = PIN_NONE,
|
||||
[28] = PIN_NONE,
|
||||
[29] = PIN_NONE,
|
||||
[0] = SH_PFC_PIN_NONE,
|
||||
[1] = SH_PFC_PIN_NONE,
|
||||
[2] = SH_PFC_PIN_NONE,
|
||||
[3] = SH_PFC_PIN_NONE,
|
||||
[4] = SH_PFC_PIN_NONE,
|
||||
[5] = SH_PFC_PIN_NONE,
|
||||
[6] = SH_PFC_PIN_NONE,
|
||||
[7] = SH_PFC_PIN_NONE,
|
||||
[8] = SH_PFC_PIN_NONE,
|
||||
[9] = SH_PFC_PIN_NONE,
|
||||
[10] = SH_PFC_PIN_NONE,
|
||||
[11] = SH_PFC_PIN_NONE,
|
||||
[12] = SH_PFC_PIN_NONE,
|
||||
[13] = SH_PFC_PIN_NONE,
|
||||
[14] = SH_PFC_PIN_NONE,
|
||||
[15] = SH_PFC_PIN_NONE,
|
||||
[16] = SH_PFC_PIN_NONE,
|
||||
[17] = SH_PFC_PIN_NONE,
|
||||
[18] = SH_PFC_PIN_NONE,
|
||||
[19] = SH_PFC_PIN_NONE,
|
||||
[20] = SH_PFC_PIN_NONE,
|
||||
[21] = SH_PFC_PIN_NONE,
|
||||
[22] = SH_PFC_PIN_NONE,
|
||||
[23] = SH_PFC_PIN_NONE,
|
||||
[24] = SH_PFC_PIN_NONE,
|
||||
[25] = SH_PFC_PIN_NONE,
|
||||
[26] = SH_PFC_PIN_NONE,
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */
|
||||
[31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */
|
||||
} },
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*
|
||||
* Copyright (C) 2017 Renesas Electronics Corp.
|
||||
*
|
||||
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
|
||||
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
|
||||
*
|
||||
* R-Car Gen3 processor support - PFC hardware block.
|
||||
*
|
||||
|
|
@ -19,7 +19,7 @@
|
|||
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CPU_ALL_PORT(fn, sfx) \
|
||||
#define CPU_ALL_GP(fn, sfx) \
|
||||
PORT_GP_9(0, fn, sfx), \
|
||||
PORT_GP_32(1, fn, sfx), \
|
||||
PORT_GP_32(2, fn, sfx), \
|
||||
|
|
|
|||
|
|
@ -1,11 +1,8 @@
|
|||
/*
|
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* SuperH Pin Function Controller Support
|
||||
*
|
||||
* Copyright (c) 2008 Magnus Damm
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#ifndef __SH_PFC_H
|
||||
|
|
@ -21,19 +18,32 @@ enum {
|
|||
PINMUX_TYPE_INPUT,
|
||||
};
|
||||
|
||||
#define SH_PFC_PIN_NONE U16_MAX
|
||||
|
||||
#define SH_PFC_PIN_CFG_INPUT (1 << 0)
|
||||
#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
|
||||
#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
|
||||
#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
|
||||
#define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \
|
||||
SH_PFC_PIN_CFG_PULL_DOWN)
|
||||
#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
|
||||
#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
|
||||
|
||||
#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6)
|
||||
#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
|
||||
|
||||
#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
|
||||
SH_PFC_PIN_VOLTAGE_18_33)
|
||||
#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
|
||||
SH_PFC_PIN_VOLTAGE_25_33)
|
||||
|
||||
#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
|
||||
|
||||
struct sh_pfc_pin {
|
||||
u16 pin;
|
||||
u16 enum_id;
|
||||
const char *name;
|
||||
unsigned int configs;
|
||||
u16 pin;
|
||||
u16 enum_id;
|
||||
};
|
||||
|
||||
#define SH_PFC_PIN_GROUP_ALIAS(alias, n) \
|
||||
|
|
@ -393,12 +403,12 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
|||
/*
|
||||
* Describe a pinmux configuration in which a pin is physically multiplexed
|
||||
* with other pins.
|
||||
* - ipsr: IPSR field (unused, for documentation purposes only)
|
||||
* - ipsr: IPSR field
|
||||
* - fn: Function name
|
||||
* - psel: Physical multiplexing selector
|
||||
*/
|
||||
#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##psel)
|
||||
PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr)
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration for a single-function pin with GPIO
|
||||
|
|
@ -416,9 +426,13 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
|||
fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
|
||||
#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
|
||||
#define PORT_GP_CFG_2(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
|
||||
#define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_2(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
|
||||
#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
|
||||
|
|
@ -517,9 +531,13 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
|||
PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
|
||||
#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
|
||||
#define PORT_GP_CFG_27(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_26(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 26, fn, sfx, cfg)
|
||||
#define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_27(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
|
||||
#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
|
||||
|
||||
|
|
@ -533,9 +551,13 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
|||
PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
|
||||
#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
|
||||
#define PORT_GP_CFG_31(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_30(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 30, fn, sfx, cfg)
|
||||
#define PORT_GP_31(bank, fn, sfx) PORT_GP_CFG_31(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_31(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
|
||||
#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
|
||||
|
||||
|
|
@ -559,7 +581,7 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
|||
|
||||
/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
|
||||
#define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
|
||||
#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
|
||||
#define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str)
|
||||
|
||||
/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
|
||||
#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
|
||||
|
|
@ -569,11 +591,29 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
|||
.enum_id = _name##_DATA, \
|
||||
.configs = cfg, \
|
||||
}
|
||||
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
|
||||
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
|
||||
|
||||
/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
|
||||
#define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
|
||||
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
|
||||
#define PINMUX_DATA_GP_ALL() CPU_ALL_GP(_GP_DATA, unused)
|
||||
|
||||
/*
|
||||
* GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin
|
||||
*
|
||||
* The largest GP pin index is obtained by taking the size of a union,
|
||||
* containing one array per GP pin, sized by the corresponding pin index.
|
||||
* As the fields in the CPU_ALL_GP() macro definition are separated by commas,
|
||||
* while the members of a union must be terminated by semicolons, the commas
|
||||
* are absorbed by wrapping them inside dummy attributes.
|
||||
*/
|
||||
#define _GP_ENTRY(bank, pin, name, sfx, cfg) \
|
||||
deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated
|
||||
#define GP_ASSIGN_LAST() \
|
||||
GP_LAST = sizeof(union { \
|
||||
char dummy[0] __attribute__((deprecated, \
|
||||
CPU_ALL_GP(_GP_ENTRY, unused), \
|
||||
deprecated)); \
|
||||
})
|
||||
|
||||
/*
|
||||
* PORT style (linear pin space)
|
||||
|
|
@ -616,22 +656,6 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
|||
.configs = cfgs, \
|
||||
}
|
||||
|
||||
/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
|
||||
#define SH_PFC_PIN_NAMED(row, col, _name) \
|
||||
{ \
|
||||
.pin = PIN_NUMBER(row, col), \
|
||||
.name = __stringify(PIN_##_name), \
|
||||
.configs = SH_PFC_PIN_CFG_NO_GPIO, \
|
||||
}
|
||||
|
||||
/* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
|
||||
#define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
|
||||
{ \
|
||||
.pin = PIN_NUMBER(row, col), \
|
||||
.name = __stringify(PIN_##_name), \
|
||||
.configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \
|
||||
}
|
||||
|
||||
/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
|
||||
* PORT_name_OUT, PORT_name_IN marks
|
||||
*/
|
||||
|
|
@ -640,6 +664,24 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
|||
PORT##pfx##_OUT, PORT##pfx##_IN)
|
||||
#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
|
||||
|
||||
/*
|
||||
* PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin
|
||||
*
|
||||
* The largest PORT pin index is obtained by taking the size of a union,
|
||||
* containing one array per PORT pin, sized by the corresponding pin index.
|
||||
* As the fields in the CPU_ALL_PORT() macro definition are separated by
|
||||
* commas, while the members of a union must be terminated by semicolons, the
|
||||
* commas are absorbed by wrapping them inside dummy attributes.
|
||||
*/
|
||||
#define _PORT_ENTRY(pn, pfx, sfx) \
|
||||
deprecated)); char pfx[pn] __attribute__((deprecated
|
||||
#define PORT_ASSIGN_LAST() \
|
||||
PORT_LAST = sizeof(union { \
|
||||
char dummy[0] __attribute__((deprecated, \
|
||||
CPU_ALL_PORT(_PORT_ENTRY, PORT, unused), \
|
||||
deprecated)); \
|
||||
})
|
||||
|
||||
/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
|
||||
#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
|
||||
[gpio - (base)] = { \
|
||||
|
|
@ -649,6 +691,26 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
|||
#define GPIO_FN(str) \
|
||||
PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
|
||||
|
||||
/*
|
||||
* Pins not associated with a GPIO port
|
||||
*/
|
||||
|
||||
#define PIN_NOGP_CFG(pin, name, fn, cfg) fn(pin, name, cfg)
|
||||
#define PIN_NOGP(pin, name, fn) fn(pin, name, 0)
|
||||
|
||||
/* NOGP_ALL - Expand to a list of PIN_id */
|
||||
#define _NOGP_ALL(pin, name, cfg) PIN_##pin
|
||||
#define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL)
|
||||
|
||||
/* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */
|
||||
#define _NOGP_PINMUX(_pin, _name, cfg) \
|
||||
{ \
|
||||
.pin = PIN_##_pin, \
|
||||
.name = "PIN_" _name, \
|
||||
.configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \
|
||||
}
|
||||
#define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX)
|
||||
|
||||
/*
|
||||
* PORTnCR helper macro for SH-Mobile/R-Mobile
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue