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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq 

- fsl-qoriq: Bug fixes related pfe, eth, thermal node, vid.c, cpu release,
  mmc, usb, env, etc for Layerscape boards
- powerpc: Update Maintainers for some boards.
This commit is contained in:
Tom Rini 2021-06-17 08:44:56 -04:00
parent 7e585b5a61 b7efcaff8b
commit a298d4fbcd
76 changed files with 1218 additions and 260 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
arch/arm/Kconfig
View File

@ -1491,6 +1491,24 @@ config TARGET_PG_WCOM_SELI8
SELI8 is a QorIQ LS1021a based service unit card used
in XMC20 and FOX615 product families.
config TARGET_PG_WCOM_EXPU1
bool "Support Hitachi-Powergrids EXPU1 service unit card"
select ARCH_LS1021A
select ARCH_SUPPORT_PSCI
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SYS_FSL_DDR
select FSL_DDR_INTERACTIVE
select VENDOR_KM
imply SCSI
help
Support for Hitachi-Powergrids EXPU1 service unit card.
EXPU1 is a QorIQ LS1021a based service unit card used
in XMC20 and FOX615 product families.
config TARGET_LS1021ATSN
bool "Support ls1021atsn"
select ARCH_LS1021A

12
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -223,7 +223,9 @@ config ARCH_LX2162A
select SYS_FSL_DDR_VER_50
select SYS_FSL_EC1
select SYS_FSL_EC2
select SYS_FSL_ERRATUM_A050106
select SYS_FSL_ERRATUM_A050204
select SYS_FSL_ERRATUM_A011334
select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
select SYS_FSL_HAS_RGMII
select SYS_FSL_HAS_SEC
select SYS_FSL_HAS_CCN508
@ -253,7 +255,9 @@ config ARCH_LX2160A
select SYS_FSL_DDR_VER_50
select SYS_FSL_EC1
select SYS_FSL_EC2
select SYS_FSL_ERRATUM_A050106
select SYS_FSL_ERRATUM_A050204
select SYS_FSL_ERRATUM_A011334
select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
select SYS_FSL_HAS_RGMII
select SYS_FSL_HAS_SEC
select SYS_FSL_HAS_CCN508
@ -371,8 +375,8 @@ config SYS_FSL_ERRATUM_A009008
config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
config SYS_FSL_ERRATUM_A050106
bool "Workaround for USB PHY erratum A050106"
config SYS_FSL_ERRATUM_A050204
bool "Workaround for USB PHY erratum A050204"
help
USB3.0 Receiver needs to enable fixed equalization
for each of PHY instances in an SOC. This is similar

2
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -1063,7 +1063,7 @@ int cpu_eth_init(struct bd_info *bis)
return error;
}
static inline int check_psci(void)
int check_psci(void)
{
unsigned int psci_ver;

1
arch/arm/cpu/armv8/fsl-layerscape/cpu.h
View File

@ -6,3 +6,4 @@
int fsl_qoriq_core_to_cluster(unsigned int core);
u32 initiator_type(u32 cluster, int init_id);
u32 cpu_mask(void);
int check_psci(void);

150
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
*/
#include <common.h>
@ -478,6 +478,151 @@ static bool crypto_is_disabled(unsigned int svr)
return false;
}
#ifdef CONFIG_FSL_PFE
void pfe_set_firmware_in_fdt(void *blob, int pfenode, void *pfw, char *pename,
unsigned int len)
{
int rc, fwnode;
unsigned int phandle;
char subnode_str[32], prop_str[32], phandle_str[32], s[64];
sprintf(subnode_str, "pfe-%s-firmware", pename);
sprintf(prop_str, "fsl,pfe-%s-firmware", pename);
sprintf(phandle_str, "fsl,%s-firmware", pename);
/*Add PE FW to fdt.*/
/* Increase the size of the fdt to make room for the node. */
rc = fdt_increase_size(blob, len);
if (rc < 0) {
printf("Unable to make room for %s firmware: %s\n", pename,
fdt_strerror(rc));
return;
}
/* Create the firmware node. */
fwnode = fdt_add_subnode(blob, pfenode, subnode_str);
if (fwnode < 0) {
fdt_get_path(blob, pfenode, s, sizeof(s));
printf("Could not add firmware node to %s: %s\n", s,
fdt_strerror(fwnode));
return;
}
rc = fdt_setprop_string(blob, fwnode, "compatible", prop_str);
if (rc < 0) {
fdt_get_path(blob, fwnode, s, sizeof(s));
printf("Could not add compatible property to node %s: %s\n", s,
fdt_strerror(rc));
return;
}
rc = fdt_setprop_u32(blob, fwnode, "length", len);
if (rc < 0) {
fdt_get_path(blob, fwnode, s, sizeof(s));
printf("Could not add compatible property to node %s: %s\n", s,
fdt_strerror(rc));
return;
}
/*create phandle and set the property*/
phandle = fdt_create_phandle(blob, fwnode);
if (!phandle) {
fdt_get_path(blob, fwnode, s, sizeof(s));
printf("Could not add phandle property to node %s: %s\n", s,
fdt_strerror(rc));
return;
}
rc = fdt_setprop(blob, fwnode, phandle_str, pfw, len);
if (rc < 0) {
fdt_get_path(blob, fwnode, s, sizeof(s));
printf("Could not add firmware property to node %s: %s\n", s,
fdt_strerror(rc));
return;
}
}
void fdt_fixup_pfe_firmware(void *blob)
{
int pfenode;
unsigned int len_class = 0, len_tmu = 0, len_util = 0;
const char *p;
void *pclassfw, *ptmufw, *putilfw;
/* The first PFE we find, will contain the actual firmware. */
pfenode = fdt_node_offset_by_compatible(blob, -1, "fsl,pfe");
if (pfenode < 0)
/* Exit silently if there are no PFE devices */
return;
/* If we already have a firmware node, then also exit silently. */
if (fdt_node_offset_by_compatible(blob, -1,
"fsl,pfe-class-firmware") > 0)
return;
/* If the environment variable is not set, then exit silently */
p = env_get("class_elf_firmware");
if (!p)
return;
pclassfw = (void *)simple_strtoul(p, NULL, 16);
if (!pclassfw)
return;
p = env_get("class_elf_size");
if (!p)
return;
len_class = simple_strtoul(p, NULL, 16);
/* If the environment variable is not set, then exit silently */
p = env_get("tmu_elf_firmware");
if (!p)
return;
ptmufw = (void *)simple_strtoul(p, NULL, 16);
if (!ptmufw)
return;
p = env_get("tmu_elf_size");
if (!p)
return;
len_tmu = simple_strtoul(p, NULL, 16);
if (len_class == 0 || len_tmu == 0) {
printf("PFE FW corrupted. CLASS FW size %d, TMU FW size %d\n",
len_class, len_tmu);
return;
}
/*Add CLASS FW to fdt.*/
pfe_set_firmware_in_fdt(blob, pfenode, pclassfw, "class", len_class);
/*Add TMU FW to fdt.*/
pfe_set_firmware_in_fdt(blob, pfenode, ptmufw, "tmu", len_tmu);
/* Util PE firmware is handled separately as it is not a usual case*/
p = env_get("util_elf_firmware");
if (!p)
return;
putilfw = (void *)simple_strtoul(p, NULL, 16);
if (!putilfw)
return;
p = env_get("util_elf_size");
if (!p)
return;
len_util = simple_strtoul(p, NULL, 16);
if (len_util) {
printf("PFE Util PE firmware is not added to FDT.\n");
return;
}
pfe_set_firmware_in_fdt(blob, pfenode, putilfw, "util", len_util);
}
#endif
void ft_cpu_setup(void *blob, struct bd_info *bd)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@ -534,6 +679,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_firmware(blob);
#endif
#ifdef CONFIG_FSL_PFE
fdt_fixup_pfe_firmware(blob);
#endif
#ifndef CONFIG_ARCH_LS1012A
fsl_fdt_disable_usb(blob);
#endif

51
arch/arm/cpu/armv8/fsl-layerscape/mp.c
View File

@ -10,10 +10,12 @@
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/arch/mp.h>
#include <asm/arch/soc.h>
#include <linux/delay.h>
#include <linux/psci.h>
#include "cpu.h"
#include <asm/arch-fsl-layerscape/soc.h>
#include <efi_loader.h>
@ -301,24 +303,41 @@ int cpu_release(u32 nr, int argc, char *const argv[])
u64 *table = get_spin_tbl_addr();
int pos;
pos = core_to_pos(nr);
if (pos <= 0)
return -1;
table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
boot_addr = simple_strtoull(argv[0], NULL, 16);
table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
flush_dcache_range((unsigned long)table,
(unsigned long)table + SPIN_TABLE_ELEM_SIZE);
asm volatile("dsb st");
/*
* The secondary CPUs polling the spin-table above for a non-zero
* value. To save power "wfe" is called. Thus call "sev" here to
* wake the CPUs and let them check the spin-table again (see
* slave_cpu loop in lowlevel.S)
*/
asm volatile("sev");
if (check_psci()) {
/* SPIN Table is used */
pos = core_to_pos(nr);
if (pos <= 0)
return -1;
table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
flush_dcache_range((unsigned long)table,
(unsigned long)table + SPIN_TABLE_ELEM_SIZE);
asm volatile("dsb st");
/*
* The secondary CPUs polling the spin-table above for a non-zero
* value. To save power "wfe" is called. Thus call "sev" here to
* wake the CPUs and let them check the spin-table again (see
* slave_cpu loop in lowlevel.S)
*/
asm volatile("sev");
} else {
/* Use PSCI to kick the core */
struct pt_regs regs;
printf("begin to kick cpu core #%d to address %llx\n",
nr, boot_addr);
regs.regs[0] = PSCI_0_2_FN64_CPU_ON;
regs.regs[1] = nr;
regs.regs[2] = boot_addr;
regs.regs[3] = 0;
smc_call(&regs);
if (regs.regs[0])
return -1;
}
return 0;
}

6
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014-2015 Freescale Semiconductor
* Copyright 2019-2020 NXP
* Copyright 2019-2021 NXP
*/
#include <common.h>
@ -218,7 +218,7 @@ static void erratum_a009007(void)
}
#if defined(CONFIG_FSL_LSCH3)
static void erratum_a050106(void)
static void erratum_a050204(void)
{
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
void __iomem *dcsr = (void __iomem *)DCSR_BASE;
@ -378,7 +378,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009798();
erratum_a008997();
erratum_a009007();
erratum_a050106();
erratum_a050204();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.

1
arch/arm/dts/Makefile
View File

@ -411,6 +411,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
ls1021a-iot-duart.dtb ls1021a-tsn.dtb
dtb-$(CONFIG_TARGET_PG_WCOM_SELI8) += ls1021a-pg-wcom-seli8.dtb
dtb-$(CONFIG_TARGET_PG_WCOM_EXPU1) += ls1021a-pg-wcom-expu1.dtb
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-qds-42-x.dtb \

3
arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts
View File

@ -41,8 +41,9 @@
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
vddio-supply = <&vddh>;
vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-name = "VDDIO";

3
arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
View File

@ -32,8 +32,9 @@
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
vddio-supply = <&vddh>;
vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-name = "VDDIO";

8
arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
View File

@ -5,7 +5,7 @@
* Some assumptions are made:
* * mezzanine card M8 is connected to IO SLOT1 (25g-aui for DPMAC 3,4,5,6)
*
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
*
*/
@ -56,3 +56,9 @@
reg = <0x3>;
};
};
&esdhc1 {
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
};

8
arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
View File

@ -6,7 +6,7 @@
* * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4)
* * mezzanine card M13/M8 is connected to IO SLOT6 (25g-aui for DPMAC 5,6)
*
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
*
*/
@ -59,3 +59,9 @@
reg = <0x1>;
};
};
&esdhc1 {
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
};

8
arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
View File

@ -6,7 +6,7 @@
* * Mezzanine card M8 is connected to IO SLOT1
* (xlaui4 for DPMAC 1)
*
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
*
*/
@ -24,3 +24,9 @@
reg = <0x0>;
};
};
&esdhc1 {
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
};

8
arch/arm/dts/fsl-lx2162a-qds.dts
View File

@ -2,7 +2,7 @@
/*
* NXP LX2162AQDS device tree source
*
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
*
*/
@ -135,3 +135,9 @@
reg = <2>;
};
};
&esdhc1 {
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
};

130
arch/arm/dts/ls1021a-pg-wcom-expu1.dts Normal file
View File

@ -0,0 +1,130 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Hitachi ABB Power Grids EXPU1 board device tree source
*
* Copyright 2020 Hitachi ABB Power Grids
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*/
/dts-v1/;
#include "ls1021a.dtsi"
/ {
model = "EXPU1 Service Unit for XMC and FOX";
aliases {
enet2-rgmii-debug-phy = &debug_phy;
};
chosen {
stdout-path = &uart0;
};
};
&enet0 {
status = "okay";
tbi-handle = <&tbi0>;
phy-connection-type = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&enet1 {
status = "okay";
tbi-handle = <&tbi1>;
phy-connection-type = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&enet2 {
phy-handle = <&debug_phy>;
phy-connection-type = "rgmii-id";
max-speed = <100>;
status = "okay";
};
&i2c0 {
status = "okay";
};
&dspi1 {
bus-num = <0>;
status = "okay";
zl30343@0 {
compatible = "gen,spidev", "zarlink,zl30343";
reg = <0>;
spi-max-frequency = <8000000>;
};
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
/* NOR Flash on board */
ranges = <0x0 0x0 0x60000000 0x04000000>;
status = "okay";
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x4000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
label = "rcw";
reg = <0x0 0x20000>;
read-only;
};
partition@20000 {
label = "qe";
reg = <0x20000 0x20000>;
};
/* ZL30343 init data to be added here */
partition@40000 {
label = "envred";
reg = <0x40000 0x20000>;
};
partition@60000 {
label = "env";
reg = <0x60000 0x20000>;
};
partition@100000 {
label = "u-boot";
reg = <0x100000 0x100000>;
};
partition@200000 {
label = "ubi0";
reg = <0x200000 0x3E00000>;
};
};
};
&mdio0 {
debug_phy: ethernet-phy@11 {
reg = <0x11>;
};
tbi0: tbi-phy@0xb {
reg = <0xb>;
device_type = "tbi-phy";
};
};
&mdio1 {
tbi1: tbi-phy@0xd {
reg = <0xd>;
device_type = "tbi-phy";
};
};
&uart0 {
status = "okay";
};

8
arch/arm/dts/ls1021a.dtsi
View File

@ -100,7 +100,7 @@
gpio0: gpio@2300000 {
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
reg = <0x2300000 0x10000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@ -110,7 +110,7 @@
gpio1: gpio@2310000 {
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
reg = <0x2310000 0x10000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@ -120,7 +120,7 @@
gpio2: gpio@2320000 {
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
reg = <0x2320000 0x10000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
@ -130,7 +130,7 @@
gpio3: gpio@2330000 {
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
reg = <0x2330000 0x10000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;

7
arch/powerpc/dts/t2080rdb.dts
View File

@ -77,10 +77,17 @@
reg = <0x0>;
};
#ifdef CONFIG_T2080RDB_REV_D
xg_aq1202_phy4: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x8>;
};
#else
xg_aq1202_phy4: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
#endif
};
};
};

11
board/freescale/common/vid.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
* Copyright 2020-21 NXP
* Copyright 2020 Stephen Carlson <stcarlso@linux.microsoft.com>
*/
@ -793,13 +793,16 @@ static int do_vdd_override(struct cmd_tbl *cmdtp,
char *const argv[])
{
ulong override;
int ret = 0;
if (argc < 2)
return CMD_RET_USAGE;
if (!strict_strtoul(argv[1], 10, &override))
adjust_vdd(override); /* the value is checked by callee */
else
if (!strict_strtoul(argv[1], 10, &override)) {
ret = adjust_vdd(override);
if (ret < 0)
return CMD_RET_FAILURE;
} else
return CMD_RET_USAGE;
return 0;
}

8
board/freescale/ls1012afrdm/ls1012afrdm.c
View File

@ -23,6 +23,7 @@
#include <fsl_mmdc.h>
#include <netdev.h>
#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
@ -185,6 +186,13 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_FSL_PFE
void board_quiesce_devices(void)
{
pfe_command_stop(0, NULL);
}
#endif
int ft_board_setup(void *blob, struct bd_info *bd)
{
arch_fixup_fdt(blob);

8
board/freescale/ls1012aqds/ls1012aqds.c
View File

@ -32,6 +32,7 @@
#include "../common/qixis.h"
#include "ls1012aqds_qixis.h"
#include "ls1012aqds_pfe.h"
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
@ -163,6 +164,13 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_FSL_PFE
void board_quiesce_devices(void)
{
pfe_command_stop(0, NULL);
}
#endif
int esdhc_status_fixup(void *blob, const char *compat)
{
char esdhc0_path[] = "/soc/esdhc@1560000";

8
board/freescale/ls1012ardb/ls1012ardb.c
View File

@ -28,6 +28,7 @@
#include <fsl_mmdc.h>
#include <netdev.h>
#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
@ -186,6 +187,13 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_FSL_PFE
void board_quiesce_devices(void)
{
pfe_command_stop(0, NULL);
}
#endif
#ifdef CONFIG_TARGET_LS1012ARDB
int esdhc_status_fixup(void *blob, const char *compat)
{

2
board/freescale/p1_p2_rdb_pc/MAINTAINERS
View File

@ -1,5 +1,5 @@
P1_P2_RDB_PC BOARD
#M: -
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/p1_p2_rdb_pc/
F: include/configs/p1_p2_rdb_pc.h

2
board/freescale/p2041rdb/MAINTAINERS
View File

@ -1,5 +1,5 @@
P2041RDB BOARD
#M: -
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/p2041rdb/
F: include/configs/P2041RDB.h

4
board/freescale/t102xrdb/MAINTAINERS
View File

@ -1,6 +1,6 @@
T102XRDB BOARD
#M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
S: Orphan (since 2018-05)
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/t102xrdb/
F: include/configs/T102xRDB.h
F: configs/T1024RDB_defconfig

4
board/freescale/t208xrdb/Kconfig
View File

@ -9,6 +9,10 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "T208xRDB"
config T2080RDB_REV_D
bool "Support for T2080RDB revisions D and up"
default n
source "board/freescale/common/Kconfig"
endif

4
board/freescale/t208xrdb/MAINTAINERS
View File

@ -8,6 +8,10 @@ F: configs/T2080RDB_NAND_defconfig
F: configs/T2080RDB_SDCARD_defconfig
F: configs/T2080RDB_SPIFLASH_defconfig
F: configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
F: configs/T2080RDB_revD_defconfig
F: configs/T2080RDB_revD_NAND_defconfig
F: configs/T2080RDB_revD_SDCARD_defconfig
F: configs/T2080RDB_revD_SPIFLASH_defconfig
T2080RDB_SECURE_BOOT BOARD
M: Ruchika Gupta <ruchika.gupta@nxp.com>

112
board/freescale/t208xrdb/eth_t208xrdb.c
View File

@ -26,84 +26,7 @@
#include <fsl_dtsec.h>
#include <asm/fsl_serdes.h>
int board_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_FMAN_ENET)
int i, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Set the two on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
switch (srds_s1) {
case 0x66:
case 0x6b:
fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR);
break;
default:
printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n",
srds_s1);
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}
extern u8 get_hw_revision(void);
/* Disable the MAC5 and MAC6 "fsl,fman-memac" nodes and the two
* "fsl,dpa-ethernet" nodes that reference them.
@ -139,6 +62,39 @@ void fdt_fixup_board_fman_ethernet(void *fdt)
}
}
/* Update the address of the second Aquantia PHY on boards revision D and up.
* Also rename the PHY node to align with the address change.
*/
void fdt_fixup_board_phy(void *fdt)
{
const char phy_path[] =
"/soc@ffe000000/fman@400000/mdio@fd000/ethernet-phy@1";
int ret, offset, new_addr = AQR113C_PHY_ADDR2;
char new_name[] = "ethernet-phy@00";
if (get_hw_revision() == 'C')
return;
offset = fdt_path_offset(fdt, phy_path);
if (offset < 0) {
printf("ethernet-phy@1 node not found in the dts\n");
return;
}
ret = fdt_setprop(fdt, offset, "reg", &new_addr, sizeof(new_addr));
if (ret < 0) {
printf("Unable to set 'reg' for node ethernet-phy@1: %s\n",
fdt_strerror(ret));
return;
}
sprintf(new_name, "ethernet-phy@%x", new_addr);
ret = fdt_set_name(fdt, offset, new_name);
if (ret < 0)
printf("Unable to rename node ethernet-phy@1: %s\n",
fdt_strerror(ret));
}
void fdt_fixup_board_enet(void *fdt)
{
return;

24
board/freescale/t208xrdb/t208xrdb.c
View File

@ -27,14 +27,29 @@
DECLARE_GLOBAL_DATA_PTR;
u8 get_hw_revision(void)
{
u8 ver = CPLD_READ(hw_ver);
switch (ver) {
default:
case 0x1:
return 'C';
case 0x0:
return 'D';
case 0x2:
return 'E';
}
}
int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
printf("Board: %sRDB, ", cpu->name);
printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
CPLD_READ(hw_ver), CPLD_READ(sw_ver));
printf("Board rev: %c CPLD ver: 0x%02x, boot from ",
get_hw_revision(), CPLD_READ(sw_ver));
#ifdef CONFIG_SDCARD
puts("SD/MMC\n");
@ -136,12 +151,9 @@ int ft_board_setup(void *blob, struct bd_info *bd)
fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#else
fdt_fixup_board_fman_ethernet(blob);
#endif
fdt_fixup_board_enet(blob);
fdt_fixup_board_phy(blob);
#endif
return 0;

1
board/freescale/t208xrdb/t208xrdb.h
View File

@ -10,5 +10,6 @@
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, struct bd_info *bd);
void fdt_fixup_board_fman_ethernet(void *blob);
void fdt_fixup_board_phy(void *blob);
#endif

4
board/freescale/t4rdb/MAINTAINERS
View File

@ -1,6 +1,6 @@
T4RDB BOARD
#M: Chunhe Lan <Chunhe.Lan@freescale.com>
S: Orphan (since 2018-05)
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/t4rdb/
F: include/configs/T4240RDB.h
F: configs/T4160RDB_defconfig

7
board/keymile/Kconfig
View File

@ -64,6 +64,13 @@ config SYS_PAX_BASE
help
IFC Base Address for PAXx FPGA.
config SYS_CLIPS_BASE
hex "CLIPS IFC Base Address"
default 0x78000000
depends on ARCH_LS1021A
help
IFC Base Address for CLIPS FPGA.
config KM_CONSOLE_TTY
string "KM Console"
default "ttyS0"

11
board/keymile/common/common.c
View File

@ -46,12 +46,14 @@ int set_km_env(void)
unsigned int pram;
unsigned int varaddr;
unsigned int kernelmem;
char *p;
unsigned long rootfssize = 0;
char envval[16];
char *p;
pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM;
env_set_hex("pnvramaddr", pnvramaddr);
sprintf(envval, "0x%x", pnvramaddr);
env_set("pnvramaddr", envval);
/* try to read rootfssize (ram image) from environment */
p = env_get("rootfssize");
@ -64,9 +66,12 @@ int set_km_env(void)
varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
env_set_hex("varaddr", varaddr);
sprintf(envval, "0x%x", varaddr);
env_set("varaddr", envval);
kernelmem = gd->ram_size - 0x400 * pram;
env_set_hex("kernelmem", kernelmem);
sprintf(envval, "0x%x", kernelmem);
env_set("kernelmem", envval);
return 0;
}

20
board/keymile/pg-wcom-ls102xa/Kconfig
View File

@ -17,3 +17,23 @@ config BOARD_SPECIFIC_OPTIONS
imply FS_CRAMFS
endif
if TARGET_PG_WCOM_EXPU1
config SYS_BOARD
default "pg-wcom-ls102xa"
config SYS_VENDOR
default "keymile"
config SYS_SOC
default "ls102xa"
config SYS_CONFIG_NAME
default "pg-wcom-expu1"
config BOARD_SPECIFIC_OPTIONS
def_bool y
imply FS_CRAMFS
endif

3
board/keymile/pg-wcom-ls102xa/MAINTAINERS
View File

@ -6,5 +6,8 @@ S: Maintained
F: board/keymile/pg-wcom-ls102xa/
F: include/configs/km/pg-wcom-ls102xa.h
F: include/configs/pg-wcom-seli8.h
F: include/configs/pg-wcom-expu1.h
F: configs/pg_wcom_seli8_defconfig
F: configs/pg_wcom_expu1_defconfig
F: arch/arm/dts/ls1021a-pg-wcom-seli8.dts
F: arch/arm/dts/ls1021a-pg-wcom-expu1.dts

69
board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
View File

@ -70,19 +70,38 @@ int board_early_init_f(void)
/* QRIO Configuration */
qrio_uprstreq(UPREQ_CORE_RST);
if (IS_ENABLED(CONFIG_TARGET_PG_WCOM_SELI8)) {
qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_LIU_RST, true);
#if CONFIG_IS_ENABLED(TARGET_PG_WCOM_SELI8)
qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_LIU_RST, true);
qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_PAXK_RST, true);
qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_PAXK_RST, true);
#endif
qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
qrio_prst(KM_DBG_ETH_RST, false, false);
}
#if CONFIG_IS_ENABLED(TARGET_PG_WCOM_EXPU1)
qrio_prstcfg(WCOM_TMG_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(WCOM_TMG_RST, true);
qrio_prstcfg(WCOM_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_prst(WCOM_PHY_RST, false, false);
qrio_prstcfg(WCOM_QSFP_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(WCOM_QSFP_RST, true);
qrio_prstcfg(WCOM_CLIPS_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_prst(WCOM_CLIPS_RST, false, false);
#endif
qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
qrio_prst(KM_DBG_ETH_RST, false, false);
i2c_deblock_gpio_cfg();
/* enable the Unit LED (red) & Boot LED (on) */
qrio_set_leds();
/* enable Application Buffer */
qrio_enable_app_buffer();
arch_soc_init();
return 0;
@ -128,6 +147,40 @@ int ft_board_setup(void *blob, struct bd_info *bd)
return 0;
}
#if defined(CONFIG_POST)
int post_hotkeys_pressed(void)
{
/* DIC26_SELFTEST: GPRTA0, GPA0 */
qrio_gpio_direction_input(QRIO_GPIO_A, 0);
return qrio_get_gpio(QRIO_GPIO_A, 0);
}
ulong post_word_load(void)
{
/* POST word is located at the beginning of reserved physical RAM */
void *addr = (void *)(CONFIG_SYS_SDRAM_BASE +
gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8);
return in_le32(addr);
}
void post_word_store(ulong value)
{
/* POST word is located at the beginning of reserved physical RAM */
void *addr = (void *)(CONFIG_SYS_SDRAM_BASE +
gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8);
out_le32(addr, value);
}
int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
/* Define only 1MiB range for mem_regions at the middle of the RAM */
/* For 1GiB range mem_regions takes approx. 4min */
*vstart = CONFIG_SYS_SDRAM_BASE + (gd->ram_size >> 1);
*size = 1 << 20;
return 0;
}
#endif
u8 flash_read8(void *addr)
{
return __raw_readb(addr + 1);

2
board/keymile/scripts/ramfs-common.txt
View File

@ -3,7 +3,7 @@ boot_bank=-1
altbootcmd=run ${subbootcmds}
bootcmd=run ${subbootcmds}
subbootcmds=save_and_reset_once tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs add_default addpanic addramfs boot
save_and_reset_once=setenv save_and_reset_once true && save && reset
save_and_reset_once=setenv save_and_reset_once true && saveenv && reset
nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}
configure=run set_uimage; run set_tftppath; km_setboardid && run try_import_rootfssize && saveenv && reset
setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value}

93
configs/T2080RDB_revD_NAND_defconfig Normal file
View File

@ -0,0 +1,93 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x00201000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_T2080RDB_REV_D=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
# CONFIG_CMD_IRQ is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_NAND=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1307=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64

90
configs/T2080RDB_revD_SDCARD_defconfig Normal file
View File

@ -0,0 +1,90 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x00201000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_T2080RDB_REV_D=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
# CONFIG_CMD_IRQ is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_MMC=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1307=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64

92
configs/T2080RDB_revD_SPIFLASH_defconfig Normal file
View File

@ -0,0 +1,92 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x00201000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_T2080RDB_REV_D=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
# CONFIG_CMD_IRQ is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1307=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64

77
configs/T2080RDB_revD_defconfig Normal file
View File

@ -0,0 +1,77 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_T2080RDB_REV_D=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
# CONFIG_CMD_IRQ is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1307=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64

1
configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
View File

@ -60,3 +60,4 @@ CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_RSA=y
CONFIG_NXP_ESBC=y

1
configs/ls1088aqds_tfa_defconfig
View File

@ -48,6 +48,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x20500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y

1
configs/ls1088ardb_tfa_defconfig
View File

@ -45,6 +45,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x20500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y

2
configs/ls2088aqds_tfa_defconfig
View File

@ -42,7 +42,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x20500000
CONFIG_ENV_ADDR=0x580500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y

70
configs/pg_wcom_expu1_defconfig Normal file
View File

@ -0,0 +1,70 @@
CONFIG_ARM=y
CONFIG_TARGET_PG_WCOM_EXPU1=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_KM_COMMON_ETH_INIT=y
CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-expu1"
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_SILENT_CONSOLE=y
CONFIG_MISC_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),-(ubi0);68000000.flash:-(ubi1)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0x60060000
CONFIG_ENV_ADDR_REDUND=0x60040000
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_FSL_DDR3=y
# CONFIG_MMC is not set
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y

2
configs/pg_wcom_seli8_defconfig
View File

@ -7,7 +7,7 @@ CONFIG_KM_COMMON_ETH_INIT=y
CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y

7
drivers/mmc/Kconfig
View File

@ -798,6 +798,13 @@ config FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
This option assumes no hotplug, and u-boot has to make all the way to
to linux to use 1.8v UHS-I speed mode if has card.
config FSL_ESDHC_VS33_NOT_SUPPORT
bool "3.3V power supply not supported"
depends on FSL_ESDHC
help
For eSDHC, power supply is through peripheral circuit. 3.3V support is
common. Select this if 3.3V power supply not supported.
config FSL_ESDHC_IMX
bool "Freescale/NXP i.MX eSDHC controller support"
help

17
drivers/mmc/fsl_esdhc.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
* Copyright 2019-2020 NXP
* Copyright 2019-2021 NXP
* Andy Fleming
*
* Based vaguely on the pxa mmc code:
@ -795,10 +795,21 @@ static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
u32 caps;
caps = esdhc_read32(&regs->hostcapblt);
/*
* For eSDHC, power supply is through peripheral circuit. Some eSDHC
* versions have value 0 of the bit but that does not reflect the
* truth. 3.3V is common for SD/MMC, and is supported for all boards
* with eSDHC in current u-boot. So, make 3.3V is supported in
* default in code. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT can be enabled
* if future board does not support 3.3V.
*/
caps |= HOSTCAPBLT_VS33;
if (IS_ENABLED(CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT))
caps &= ~HOSTCAPBLT_VS33;
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135))
caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
if (IS_ENABLED(CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33))
caps |= HOSTCAPBLT_VS33;
if (caps & HOSTCAPBLT_VS18)
cfg->voltages |= MMC_VDD_165_195;
if (caps & HOSTCAPBLT_VS30)

7
drivers/mmc/fsl_esdhc_imx.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
* Copyright 2019 NXP Semiconductors
* Copyright 2019, 2021 NXP
* Andy Fleming
* Yangbo Lu <yangbo.lu@nxp.com>
*
@ -1234,11 +1234,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
#endif
/* T4240 host controller capabilities register should have VS33 bit */
#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
caps = caps | ESDHC_HOSTCAPBLT_VS33;
#endif
if (caps & ESDHC_HOSTCAPBLT_VS18)
voltage_caps |= MMC_VDD_165_195;
if (caps & ESDHC_HOSTCAPBLT_VS30)

2
drivers/net/pfe_eth/pfe_cmd.c
View File

@ -418,7 +418,7 @@ static void send_dummy_pkt_to_hif(void)
writel(buf, TMU_PHY_INQ_PKTINFO);
}
static void pfe_command_stop(int argc, char *const argv[])
void pfe_command_stop(int argc, char *const argv[])
{
int pfe_pe_id, hif_stop_loop = 10;
u32 rx_status;

60
drivers/net/pfe_eth/pfe_firmware.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017,2021 NXP
*/
/*
@ -262,7 +262,8 @@ int pfe_firmware_init(void)
uintptr_t pfe_img_addr = 0;
#endif
int ret = 0;
int fw_count;
int fw_count, max_fw_count;
const char *p;
ret = pfe_spi_flash_init();
if (ret)
@ -293,6 +294,61 @@ int pfe_firmware_init(void)
}
#endif
p = env_get("load_util");
if (!p) {
max_fw_count = 2;
} else {
max_fw_count = simple_strtoul(p, NULL, 10);
if (max_fw_count)
max_fw_count = 3;
else
max_fw_count = 2;
}
for (fw_count = 0; fw_count < max_fw_count; fw_count++) {
switch (fw_count) {
case 0:
pfe_firmware_name = "class_slowpath";
break;
case 1:
pfe_firmware_name = "tmu_slowpath";
break;
case 2:
pfe_firmware_name = "util_slowpath";
break;
}
if (pfe_get_fw(&raw_image_addr, &raw_image_size,
pfe_firmware_name)) {
printf("%s firmware couldn't be found in FIT image\n",
pfe_firmware_name);
break;
}
pfe_firmware = malloc(raw_image_size);
if (!pfe_firmware)
return -ENOMEM;
memcpy((void *)pfe_firmware, (void *)raw_image_addr,
raw_image_size);
switch (fw_count) {
case 0:
env_set_addr("class_elf_firmware", pfe_firmware);
env_set_addr("class_elf_size", (void *)raw_image_size);
break;
case 1:
env_set_addr("tmu_elf_firmware", pfe_firmware);
env_set_addr("tmu_elf_size", (void *)raw_image_size);
break;
case 2:
env_set_addr("util_elf_firmware", pfe_firmware);
env_set_addr("util_elf_size", (void *)raw_image_size);
break;
}
}
raw_image_addr = NULL;
pfe_firmware = NULL;
raw_image_size = 0;
for (fw_count = 0; fw_count < 2; fw_count++) {
if (fw_count == 0)
pfe_firmware_name = "class";

7
drivers/net/tsec.c
View File

@ -828,6 +828,7 @@ int tsec_probe(struct udevice *dev)
const char *phy_mode;
ofnode parent, child;
fdt_addr_t reg;
u32 max_speed;
int ret;
data = (struct tsec_data *)dev_get_driver_data(dev);
@ -893,8 +894,12 @@ int tsec_probe(struct udevice *dev)
}
priv->interface = pdata->phy_interface;
/* Check for speed limit, default is 1000Mbps */
max_speed = dev_read_u32_default(dev, "max-speed", 1000);
/* Initialize flags */
priv->flags = TSEC_GIGABIT;
if (max_speed == 1000)
priv->flags = TSEC_GIGABIT;
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
priv->flags |= TSEC_SGMII;

4
drivers/pci/pcie_layerscape_ep.c
View File

@ -269,6 +269,10 @@ static int ls_pcie_ep_probe(struct udevice *dev)
pcie->idx = ((unsigned long)pcie->dbi - PCIE_SYS_BASE_ADDR) /
PCIE_CCSR_SIZE;
/* This controller is disabled by RCW */
if (!is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx)))
return 0;
pcie->big_endian = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"big-endian");

2
include/configs/P2041RDB.h
View File

@ -92,7 +92,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/*
* DDR Setup

3
include/configs/T208xQDS.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2011-2013 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
*/
/*
@ -618,7 +618,6 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
/*

9
include/configs/T208xRDB.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
*/
/*
@ -537,8 +537,12 @@ unsigned long get_board_ddr_clk(void);
#define RGMII_PHY2_ADDR 0x02
#define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
#define CORTINA_PHY_ADDR2 0x0d
#define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
/* Aquantia AQ1202 10G Base-T used by board revisions up to C */
#define FM1_10GEC3_PHY_ADDR 0x00
#define FM1_10GEC4_PHY_ADDR 0x01
/* Aquantia AQR113C 10G Base-T used by board revisions D and up */
#define AQR113C_PHY_ADDR1 0x00
#define AQR113C_PHY_ADDR2 0x08
#endif
#ifdef CONFIG_FMAN_ENET
@ -574,7 +578,6 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
/*

3
include/configs/T4240RDB.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
*/
/*
@ -585,7 +585,6 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif

17
include/configs/km/pg-wcom-ls102xa.h
View File

@ -21,6 +21,10 @@
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \
CONFIG_KM_PHRAM + \
CONFIG_KM_RESERVED_PRAM) >> 10)
#define CONFIG_SYS_CLK_FREQ 66666666
/*
* Take into account default implementation where DDR_FDBK_MULTI is consider as
@ -43,6 +47,10 @@
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x54
/* POST memory regions test */
#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS)
#define CONFIG_POST_EXTERNAL_WORD_FUNCS
/*
* IFC Definitions
*/
@ -206,7 +214,7 @@
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
#define COUNTER_FREQUENCY 12500000
#define COUNTER_FREQUENCY 8333333
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 256
@ -280,10 +288,17 @@
"protect on " __stringify(ENV_DEL_ADDR) \
" +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
#define CONFIG_HW_ENV_SETTINGS \
"hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi," \
"can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6," \
"asrc,spdif,lpuart1,ftm1\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_NEW_ENV \
CONFIG_KM_DEF_ENV \
CONFIG_HW_ENV_SETTINGS \
"EEprom_ivm=pca9547:70:9\0" \
"ethrotate=no\0" \
""
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */

5
include/configs/kontron_sl28.h
View File

@ -56,11 +56,6 @@
#define CONFIG_DDR_CLK_FREQ 100000000
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
/* ethernet */
#define CONFIG_SYS_RX_ETH_BUFFER 8

13
include/configs/ls1012a2g5rdb.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017 NXP
* Copyright 2017, 2021 NXP
*/
#ifndef __LS1012A2G5RDB_H__
@ -13,11 +13,6 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
/* SATA */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
@ -72,7 +67,7 @@
"installer=load mmc 0:2 $load_addr " \
"/flex_installer_arm64.itb; " \
"bootm $load_addr#$board\0" \
"qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \
"qspi_bootcmd=echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
"$kernel_addr $kernel_size; env exists secureboot " \
"&& sf read $kernelheader_addr_r $kernelheader_addr " \
@ -82,11 +77,11 @@
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#undef QSPI_NOR_BOOTCOMMAND
#define QSPI_NOR_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;"
#else
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;"
#endif
#endif

4
include/configs/ls1012a_common.h
View File

@ -102,11 +102,11 @@
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#define QSPI_NOR_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\
#define QSPI_NOR_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
"$kernel_start $kernel_size && "\
"bootm $kernel_load"
#else
#define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\
#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
"$kernel_start $kernel_size && "\
"bootm $kernel_load"
#endif

6
include/configs/ls1012afrdm.h
View File

@ -50,16 +50,16 @@
"installer=load usb 0:2 $load_addr " \
"/flex_installer_arm64.itb; " \
"bootm $load_addr#$board\0" \
"qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \
"qspi_bootcmd=echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
"$kernel_addr $kernel_size && bootm $load_addr#$board\0"
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#undef QSPI_NOR_BOOTCOMMAND
#define QSPI_NOR_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd"
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd"
#else
#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd"
#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd"
#endif
#endif /* __LS1012ARDB_H__ */

13
include/configs/ls1012afrwy.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
* Copyright 2018, 2021 NXP
*/
#ifndef __LS1012AFRWY_H__
@ -33,11 +33,6 @@
func(DHCP, dhcp, na)
#endif
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCI_SCAN_SHOW
@ -89,7 +84,7 @@
"env exists secureboot " \
"&& esbc_validate ${scripthdraddr};" \
"source ${scriptaddr}\0" \
"sd_bootcmd=pfe stop; echo Trying load from sd card..;" \
"sd_bootcmd=echo Trying load from sd card..;" \
"mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd ;" \
"env exists secureboot && mmc read $kernelheader_addr_r "\
@ -100,10 +95,10 @@
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#undef QSPI_NOR_BOOTCOMMAND
#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run sd_bootcmd; "\
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "\
"env exists secureboot && esbc_halt;"
#else
#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run sd_bootcmd; "\
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "\
"env exists secureboot && esbc_halt;"
#endif

12
include/configs/ls1012aqds.h
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#ifndef __LS1012AQDS_H__
@ -93,11 +94,6 @@
DSPI_CTAR_DT(0))
#define CONFIG_SPI_FLASH_EON /* cs3 */
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCI_SCAN_SHOW
@ -140,7 +136,7 @@
"env exists secureboot " \
"&& esbc_validate ${scripthdraddr};" \
"source ${scriptaddr}\0" \
"qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \
"qspi_bootcmd=echo Trying load from qspi..;" \
"sf probe 0:0 && sf read $load_addr " \
"$kernel_addr $kernel_size; env exists secureboot " \
"&& sf read $kernelheader_addr_r $kernelheader_addr " \
@ -150,10 +146,10 @@
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#undef QSPI_NOR_BOOTCOMMAND
#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\
"env exists secureboot && esbc_halt;"
#else
#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\
"env exists secureboot && esbc_halt;"
#endif

14
include/configs/ls1012ardb.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
* Copyright 2016 Freescale Semiconductor, Inc.
*/
@ -38,12 +38,6 @@
#define __PHY_ETH2_MASK 0xFB
#define __PHY_ETH1_MASK 0xFD
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCI_SCAN_SHOW
@ -91,7 +85,7 @@
"installer=load mmc 0:2 $load_addr " \
"/flex_installer_arm64.itb; " \
"bootm $load_addr#$board\0" \
"qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \
"qspi_bootcmd=echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
"$kernel_addr $kernel_size; env exists secureboot " \
"&& sf read $kernelheader_addr_r $kernelheader_addr " \
@ -101,10 +95,10 @@
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#undef QSPI_NOR_BOOTCOMMAND
#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\
"env exists secureboot && esbc_halt;"
#else
#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\
"env exists secureboot && esbc_halt;"
#endif

7
include/configs/ls1028a_common.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019-2020 NXP
* Copyright 2019-2021 NXP
*/
#ifndef __L1028A_COMMON_H
@ -93,11 +93,6 @@
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#define OCRAM_NONSECURE_SIZE 0x00010000
#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000

9
include/configs/ls1043a_common.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015 Freescale Semiconductor
* Copyright 2019-2020 NXP
* Copyright 2019-2021 NXP
*/
#ifndef __LS1043A_COMMON_H
@ -171,13 +171,6 @@
#endif
#endif
/* MMC */
#ifndef SPL_NO_MMC
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#endif
/* DSPI */
#ifndef SPL_NO_DSPI
#ifdef CONFIG_FSL_DSPI

9
include/configs/ls1046a_common.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 Freescale Semiconductor
* Copyright 2019-2020 NXP
* Copyright 2019-2021 NXP
*/
#ifndef __LS1046A_COMMON_H
@ -165,13 +165,6 @@
CONFIG_SYS_SCSI_MAX_LUN)
#endif
/* MMC */
#ifndef SPL_NO_MMC
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#endif
/* FMan ucode */
#ifndef SPL_NO_FMAN
#define CONFIG_SYS_DPAA_FMAN

3
include/configs/ls1088aqds.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017, 2020 NXP
* Copyright 2017, 2020-2021 NXP
*/
#ifndef __LS1088A_QDS_H
@ -361,7 +361,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_FSL_MEMAC
/* MMC */
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)

7
include/configs/ls1088ardb.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017, 2020 NXP
* Copyright 2017, 2020-2021 NXP
*/
#ifndef __LS1088A_RDB_H
@ -507,11 +507,6 @@
#endif
#endif
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#ifndef SPL_NO_ENV
#define BOOT_TARGET_DEVICES(func) \

7
include/configs/ls2080aqds.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017, 2019-2020 NXP
* Copyright 2017, 2019-2021 NXP
* Copyright 2015 Freescale Semiconductor
*/
@ -318,11 +318,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PCI_SCAN_SHOW
#endif
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
#ifdef CONFIG_NXP_ESBC

7
include/configs/ls2080ardb.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017, 2019-2020 NXP
* Copyright 2017, 2019-2021 NXP
* Copyright 2015 Freescale Semiconductor
*/
@ -300,11 +300,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_PCI_SCAN_SHOW
#endif
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0) \
func(MMC, mmc, 0) \

7
include/configs/lx2160a_common.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018-2020 NXP
* Copyright 2018-2021 NXP
*/
#ifndef __LX2_COMMON_H
@ -129,11 +129,6 @@
#define CONFIG_PCI_SCAN_SHOW
#endif
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
/* SATA */
#ifdef CONFIG_SCSI

53
include/configs/pg-wcom-expu1.h Normal file
View File

@ -0,0 +1,53 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 Hitachi ABB Power Grids
*/
#ifndef __CONFIG_PG_WCOM_EXPU1_H
#define __CONFIG_PG_WCOM_EXPU1_H
#define WCOM_EXPU1
#define CONFIG_HOSTNAME "EXPU1"
#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
/* CLIPS FPGA Definitions */
#define CONFIG_SYS_CSPR3_EXT (0x00)
#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
CSOR_GPCM_TRHZ_40)
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
FTIM0_GPCM_TEADC(0x7) | \
FTIM0_GPCM_TEAHC(0x2))
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
FTIM1_GPCM_TRAD(0x12))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x12))
#define CONFIG_SYS_CS3_FTIM3 0x04000000
/* PRST */
#define WCOM_CLIPS_RST 0
#define WCOM_QSFP_RST 1
#define WCOM_PHY_RST 2
#define WCOM_TMG_RST 3
#define KM_DBG_ETH_RST 15
/* QRIO GPIOs used for deblocking */
#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
#define KM_I2C_DEBLOCK_SCL 20
#define KM_I2C_DEBLOCK_SDA 21
/* ZL30343 on SPI */
#define WCOM_ZL30343_CFG_ADDR 0xe8070000
#define WCOM_ZL30343_SPI_BUS 0
#define WCOM_ZL30343_CS 0
#include "km/pg-wcom-ls102xa.h"
#endif /* __CONFIG_PG_WCOM_EXPU1_H */

6
include/net/pfe_eth/pfe/pfe_hw.h
View File

@ -160,4 +160,10 @@ void hif_rx_enable(void);
void hif_rx_disable(void);
void hif_rx_desc_disable(void);
#ifdef PFE_RESET_WA
void pfe_command_stop(int argc, char *const argv[]);
#else
static void pfe_command_stop(int argc, char *const argv[]) {}
#endif
#endif /* _PFE_H_ */

1
scripts/config_whitelist.txt
View File

@ -2307,7 +2307,6 @@ CONFIG_SYS_FSL_MAX_NUM_OF_SEC
CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR
CONFIG_SYS_FSL_MC_BASE
CONFIG_SYS_FSL_MC_SIZE
CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
CONFIG_SYS_FSL_NI_BASE
CONFIG_SYS_FSL_NI_SIZE
CONFIG_SYS_FSL_NO_SERDES