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[FIX] Coding style cleanup

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This commit is contained in:
Michal Simek 2007-08-05 22:33:05 +02:00
parent 45b3fd2815
commit a274ca4f6d
3 changed files with 45 additions and 46 deletions
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71
drivers/net/xilinx_emac.h
View File

@ -1,7 +1,7 @@
/* /*
* (C) Copyright 2007 Michal Simek * (C) Copyright 2007 Michal Simek
* *
* Michal SIMEK <monstr@monstr.eu> * Michal SIMEK <monstr@monstr.eu>
* *
* See file CREDITS for list of people who contributed to this * See file CREDITS for list of people who contributed to this
* project. * project.
@ -13,7 +13,7 @@
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
@ -35,34 +35,33 @@ typedef struct {
u32 IsStarted; /* Device is currently started 0-no, 1-yes */ u32 IsStarted; /* Device is currently started 0-no, 1-yes */
XPacketFifoV100b RecvFifo; /* FIFO used to receive frames */ XPacketFifoV100b RecvFifo; /* FIFO used to receive frames */
XPacketFifoV100b SendFifo; /* FIFO used to send frames */ XPacketFifoV100b SendFifo; /* FIFO used to send frames */
} XEmac; } XEmac;
#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */ #define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */
#define XIIF_V123B_RESET_MASK 0xAUL #define XIIF_V123B_RESET_MASK 0xAUL
#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */ #define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */
/* This constant is used with the Reset Register */ /* This constant is used with the Reset Register */
#define XPF_RESET_FIFO_MASK 0x0000000A #define XPF_RESET_FIFO_MASK 0x0000000A
#define XPF_COUNT_STATUS_REG_OFFSET 4UL #define XPF_COUNT_STATUS_REG_OFFSET 4UL
/* * These constants are used with the Occupancy/Vacancy Count Register. This /* These constants are used with the Occupancy/Vacancy Count Register. This
* register also contains FIFO status */ * register also contains FIFO status */
#define XPF_COUNT_MASK 0x0000FFFF #define XPF_COUNT_MASK 0x0000FFFF
#define XPF_DEADLOCK_MASK 0x20000000 #define XPF_DEADLOCK_MASK 0x20000000
/* Offset of the MAC registers from the IPIF base address */ /* Offset of the MAC registers from the IPIF base address */
#define XEM_REG_OFFSET 0x1100UL #define XEM_REG_OFFSET 0x1100UL
/* /*
* Register offsets for the Ethernet MAC. Each register is 32 bits. * Register offsets for the Ethernet MAC. Each register is 32 bits.
*/ */
#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */ #define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */
#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */ #define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */
#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */ #define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */
#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */ #define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */
#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */ #define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */
#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */ #define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */
@ -78,31 +77,31 @@ typedef struct {
* part of the IPIF IP Interrupt registers * part of the IPIF IP Interrupt registers
*/ */
/* A mask for all transmit interrupts, used in polled mode */ /* A mask for all transmit interrupts, used in polled mode */
#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK | \ #define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK |\
XEM_EIR_XMIT_ERROR_MASK | \ XEM_EIR_XMIT_ERROR_MASK | \
XEM_EIR_XMIT_SFIFO_EMPTY_MASK | \ XEM_EIR_XMIT_SFIFO_EMPTY_MASK |\
XEM_EIR_XMIT_LFIFO_FULL_MASK) XEM_EIR_XMIT_LFIFO_FULL_MASK)
#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL /* Xmit complete */ #define XEM_EIR_XMIT_DONE_MASK 0x00000001UL /* Xmit complete */
#define XEM_EIR_RECV_DONE_MASK 0x00000002UL /* Recv complete */ #define XEM_EIR_RECV_DONE_MASK 0x00000002UL /* Recv complete */
#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL /* Xmit error */ #define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL /* Xmit error */
#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL /* Recv error */ #define XEM_EIR_RECV_ERROR_MASK 0x00000008UL /* Recv error */
#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL /* Xmit status fifo empty */ #define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL /* Xmit status fifo empty */
#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL /* Recv length fifo empty */ #define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL /* Recv length fifo empty */
#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL /* Xmit length fifo full */ #define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL /* Xmit length fifo full */
#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL /* Recv length fifo #define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL /* Recv length fifo
* overrun */ * overrun */
#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL /* Recv length fifo #define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL /* Recv length fifo
* underrun */ * underrun */
#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL /* Xmit status fifo #define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL /* Xmit status fifo
* overrun */ * overrun */
#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL /* Transmit status fifo #define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL /* Transmit status fifo
* underrun */ * underrun */
#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL /* Transmit length fifo #define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL /* Transmit length fifo
* overrun */ * overrun */
#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL /* Transmit length fifo #define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL /* Transmit length fifo
* underrun */ * underrun */
#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL /* Transmit pause pkt #define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL /* Transmit pause pkt
* received */ * received */
/* /*
@ -124,5 +123,5 @@ typedef struct {
* addr */ * addr */
/* Transmit Status Register (TSR) */ /* Transmit Status Register (TSR) */
#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL /* Transmit excess deferral */ #define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL /* Transmit excess deferral */
#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL /* Transmit late collision */ #define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL /* Transmit late collision */

10
drivers/net/xilinx_emaclite.c
View File

@ -29,7 +29,7 @@
#ifdef XILINX_EMACLITE_BASEADDR #ifdef XILINX_EMACLITE_BASEADDR
//#define DEBUG #undef DEBUG
#define ENET_MAX_MTU PKTSIZE #define ENET_MAX_MTU PKTSIZE
#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
@ -310,7 +310,7 @@ int eth_rx (void)
BaseAddress = EmacLite.BaseAddress + EmacLite.NextRxBufferToUse; BaseAddress = EmacLite.BaseAddress + EmacLite.NextRxBufferToUse;
Register = in_be32 (BaseAddress + XEL_RSR_OFFSET); Register = in_be32 (BaseAddress + XEL_RSR_OFFSET);
#ifdef DEBUG #ifdef DEBUG
// printf ("Testing data at address 0x%x\n", BaseAddress); printf ("Testing data at address 0x%x\n", BaseAddress);
#endif #endif
if ((Register & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { if ((Register & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
#ifdef XILINX_EMACLITE_RX_PING_PONG #ifdef XILINX_EMACLITE_RX_PING_PONG
@ -319,7 +319,7 @@ int eth_rx (void)
} else { } else {
#ifndef XILINX_EMACLITE_RX_PING_PONG #ifndef XILINX_EMACLITE_RX_PING_PONG
#ifdef DEBUG #ifdef DEBUG
// printf ("No data was available - address 0x%x\n", BaseAddress); printf ("No data was available - address 0x%x\n", BaseAddress);
#endif #endif
return 0; return 0;
#else #else
@ -328,8 +328,8 @@ int eth_rx (void)
if ((Register & XEL_RSR_RECV_DONE_MASK) != if ((Register & XEL_RSR_RECV_DONE_MASK) !=
XEL_RSR_RECV_DONE_MASK) { XEL_RSR_RECV_DONE_MASK) {
#ifdef DEBUG #ifdef DEBUG
// printf ("No data was available - address 0x%x\n", printf ("No data was available - address 0x%x\n",
// BaseAddress); BaseAddress);
#endif #endif
return 0; return 0;
} }

10
include/configs/ml401.h
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@ -87,7 +87,7 @@
* 0x11FB_F000 CFG_MONITOR_BASE * 0x11FB_F000 CFG_MONITOR_BASE
* MONITOR_CODE 256kB Env * MONITOR_CODE 256kB Env
* 0x13FF_F000 CFG_GBL_DATA_OFFSET * 0x13FF_F000 CFG_GBL_DATA_OFFSET
* GLOBAL_DATA 4kB bd, gd * GLOBAL_DATA 4kB bd, gd
* 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE * 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
*/ */
@ -100,7 +100,7 @@
/* global pointer */ /* global pointer */
#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */ #define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
/* start of global data */ /* start of global data */
#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) #define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
/* monitor code */ /* monitor code */
#define SIZE 0x40000 #define SIZE 0x40000
@ -243,10 +243,10 @@
#define CONFIG_BOOTDELAY 30 #define CONFIG_BOOTDELAY 30
#define CONFIG_BOOTARGS "root=romfs" #define CONFIG_BOOTARGS "root=romfs"
#define CONFIG_HOSTNAME "ml401" #define CONFIG_HOSTNAME "ml401"
#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
#define CONFIG_IPADDR 192.168.0.3 #define CONFIG_IPADDR 192.168.0.3
#define CONFIG_SERVERIP 192.168.0.5 #define CONFIG_SERVERIP 192.168.0.5
#define CONFIG_GATEWAYIP 192.168.0.1 #define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
/* architecture dependent code */ /* architecture dependent code */