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net: zynq: Don't overwrite gem_rclk_ctrl with default value
The gem[0-1]_rclk_ctrl registers control the source of the rx clock, control and data signals and configure via ps7_init function. Don't overwrite the register with the default value. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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@ -140,13 +140,6 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
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if (ret)
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goto out;
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if (gem_id) {
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/* Configure GEM_RCLK_CTRL */
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writel(1, &slcr_base->gem1_rclk_ctrl);
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} else {
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/* Configure GEM_RCLK_CTRL */
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writel(1, &slcr_base->gem0_rclk_ctrl);
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}
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udelay(100000);
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out:
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zynq_slcr_lock();
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@ -175,7 +175,6 @@ struct zynq_gem_priv {
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u32 rxbd_current;
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u32 rx_first_buf;
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int phyaddr;
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u32 emio;
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int init;
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struct zynq_gem_regs *iobase;
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phy_interface_t interface;
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@ -457,8 +456,6 @@ static int zynq_gem_init(struct udevice *dev)
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break;
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}
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/* Change the rclk and clk only not using EMIO interface */
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if (!priv->emio)
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#ifndef CONFIG_CLK_ZYNQMP
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zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
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ZYNQ_GEM_BASEADDR0, clk_rate);
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@ -690,7 +687,6 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
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pdata->iobase = (phys_addr_t)dev_get_addr(dev);
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priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
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/* Hardcode for now */
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priv->emio = 0;
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priv->phyaddr = -1;
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priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
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@ -708,8 +704,6 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
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}
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priv->interface = pdata->phy_interface;
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priv->emio = fdtdec_get_bool(gd->fdt_blob, node, "xlnx,emio");
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printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
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priv->phyaddr, phy_string_for_interface(priv->interface));
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