From 16841a6a500766662f6e5d3c07ad1595c7deaceb Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Mar 2021 15:56:53 +0800 Subject: [PATCH 001/117] tools: imx image: fix write warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix the warning by set the variable zero to uint64_t "warning: ‘write’ reading 5 bytes from a region of size 4" Signed-off-by: Peng Fan --- tools/imx8image.c | 2 +- tools/imx8mimage.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/imx8image.c b/tools/imx8image.c index 133780f5ea..fa8f227487 100644 --- a/tools/imx8image.c +++ b/tools/imx8image.c @@ -365,7 +365,7 @@ static void copy_file (int ifd, const char *datafile, int pad, int offset) struct stat sbuf; unsigned char *ptr; int tail; - int zero = 0; + uint64_t zero = 0; uint8_t zeros[4096]; int size, ret; diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c index 9985b95a98..11e40ccd94 100644 --- a/tools/imx8mimage.c +++ b/tools/imx8mimage.c @@ -248,7 +248,7 @@ static void copy_file(int ifd, const char *datafile, int pad, int offset, struct stat sbuf; unsigned char *ptr; int tail; - int zero = 0; + uint64_t zero = 0; uint8_t zeros[4096]; int size, ret; From cf16dc3329bd396e624cddaf35ef5c1bf77da66c Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 19 Mar 2021 15:56:54 +0800 Subject: [PATCH 002/117] imx8mm_evk: Update to latest LPDDR4 script Update LPDDR4 script to sync with v2020.04 u-boot Signed-off-by: Ye Li --- board/freescale/imx8mm_evk/lpddr4_timing.c | 692 +++++++++------------ 1 file changed, 280 insertions(+), 412 deletions(-) diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c b/board/freescale/imx8mm_evk/lpddr4_timing.c index 8e48b9d81b..4373ca624e 100644 --- a/board/freescale/imx8mm_evk/lpddr4_timing.c +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c @@ -1,129 +1,162 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2018-2019 NXP + * + * Generated code from MX8M_DDR_tool */ #include -#include #include -#include -struct dram_cfg_param lpddr4_ddrc_cfg[] = { - /* Start to config, default 3200mbps */ - { DDRC_DBG1(0), 0x00000001 }, - { DDRC_PWRCTL(0), 0x00000001 }, - { DDRC_MSTR(0), 0xa1080020 }, - { DDRC_RFSHTMG(0), 0x005b00d2 }, - { DDRC_INIT0(0), 0xC003061B }, - { DDRC_INIT1(0), 0x009D0000 }, - { DDRC_INIT3(0), 0x00D4002D }, - { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, - { DDRC_INIT6(0), 0x0066004a }, - { DDRC_INIT7(0), 0x0006004a }, - - { DDRC_DRAMTMG0(0), 0x1A201B22 }, - { DDRC_DRAMTMG1(0), 0x00060633 }, - { DDRC_DRAMTMG3(0), 0x00C0C000 }, - { DDRC_DRAMTMG4(0), 0x0F04080F }, - { DDRC_DRAMTMG5(0), 0x02040C0C }, - { DDRC_DRAMTMG6(0), 0x01010007 }, - { DDRC_DRAMTMG7(0), 0x00000401 }, - { DDRC_DRAMTMG12(0), 0x00020600 }, - { DDRC_DRAMTMG13(0), 0x0C100002 }, - { DDRC_DRAMTMG14(0), 0x000000E6 }, - { DDRC_DRAMTMG17(0), 0x00A00050 }, - - { DDRC_ZQCTL0(0), 0x03200018 }, - { DDRC_ZQCTL1(0), 0x028061A8 }, - { DDRC_ZQCTL2(0), 0x00000000 }, - - { DDRC_DFITMG0(0), 0x0497820A }, - { DDRC_DFITMG2(0), 0x0000170A }, - { DDRC_DRAMTMG2(0), 0x070E171a }, - { DDRC_DBICTL(0), 0x00000001 }, - - { DDRC_DFITMG1(0), 0x00080303 }, - { DDRC_DFIUPD0(0), 0xE0400018 }, - { DDRC_DFIUPD1(0), 0x00DF00E4 }, - { DDRC_DFIUPD2(0), 0x80000000 }, - { DDRC_DFIMISC(0), 0x00000011 }, - - { DDRC_DFIPHYMSTR(0), 0x00000000 }, - { DDRC_RANKCTL(0), 0x00000c99 }, - - /* address mapping */ - { DDRC_ADDRMAP0(0), 0x0000001f }, - { DDRC_ADDRMAP1(0), 0x00080808 }, - { DDRC_ADDRMAP2(0), 0x00000000 }, - { DDRC_ADDRMAP3(0), 0x00000000 }, - { DDRC_ADDRMAP4(0), 0x00001f1f }, - { DDRC_ADDRMAP5(0), 0x07070707 }, - { DDRC_ADDRMAP6(0), 0x07070707 }, - { DDRC_ADDRMAP7(0), 0x00000f0f }, +struct dram_cfg_param ddr_ddrc_cfg[] = { + /* Initialize DDRC registers */ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x223 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x66004d }, + { 0x3d4000ec, 0x16004d }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, /* performance setting */ - { DDRC_SCHED(0), 0x29001701 }, - { DDRC_SCHED1(0), 0x0000002c }, - { DDRC_PERFHPR1(0), 0x04000030 }, - { DDRC_PERFLPR1(0), 0x900093e7 }, - { DDRC_PERFWR1(0), 0x20005574 }, - { DDRC_PCCFG(0), 0x00000111 }, - { DDRC_PCFGW_0(0), 0x000072ff }, - { DDRC_PCFGQOS0_0(0), 0x02100e07 }, - { DDRC_PCFGQOS1_0(0), 0x00620096 }, - { DDRC_PCFGWQOS0_0(0), 0x01100e07 }, - { DDRC_PCFGWQOS1_0(0), 0x00c8012c }, + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, - /* frequency P1&P2 */ - /* Frequency 1: 400mbps */ - { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, - { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 }, - { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c }, - { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 }, - { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 }, - { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 }, - { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 }, - { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e }, - { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 }, - { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, - { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b }, - { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 }, - { DDRC_FREQ1_DFITMG0(0), 0x03818200 }, - { DDRC_FREQ1_DFITMG2(0), 0x00000000 }, - { DDRC_FREQ1_RFSHTMG(0), 0x000C001c }, - { DDRC_FREQ1_INIT3(0), 0x00840000 }, - { DDRC_FREQ1_INIT4(0), 0x00310000 }, - { DDRC_FREQ1_INIT6(0), 0x0066004a }, - { DDRC_FREQ1_INIT7(0), 0x0006004a }, + /* P1: 400mts */ + { 0x3d402020, 0x21 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, + { 0x3d4020ec, 0x16004d }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, - /* Frequency 2: 100mbps */ - { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c }, - { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 }, - { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c }, - { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 }, - { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 }, - { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 }, - { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 }, - { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e }, - { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 }, - { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b }, - { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 }, - { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, - { DDRC_FREQ2_DFITMG2(0), 0x00000000 }, - { DDRC_FREQ2_RFSHTMG(0), 0x0003800c }, - { DDRC_FREQ2_RFSHTMG(0), 0x00030007 }, - { DDRC_FREQ2_INIT3(0), 0x00840000 }, - { DDRC_FREQ2_INIT4(0), 0x00310008 }, - { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, - { DDRC_FREQ2_INIT6(0), 0x0066004a }, - { DDRC_FREQ2_INIT7(0), 0x0006004a }, + /* p2: 100mts */ + { 0x3d403020, 0x21 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, + { 0x3d4030ec, 0x16004d }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, - /* boot start point */ - { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2 + /* default boot point */ + { 0x3d400028, 0x0 }, }; /* PHY Initialize Configuration */ -struct dram_cfg_param lpddr4_ddrphy_cfg[] = { +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, { 0x1005f, 0x1ff }, { 0x1015f, 0x1ff }, { 0x1105f, 0x1ff }, @@ -132,7 +165,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x1215f, 0x1ff }, { 0x1305f, 0x1ff }, { 0x1315f, 0x1ff }, - { 0x11005f, 0x1ff }, { 0x11015f, 0x1ff }, { 0x11105f, 0x1ff }, @@ -141,7 +173,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x11215f, 0x1ff }, { 0x11305f, 0x1ff }, { 0x11315f, 0x1ff }, - { 0x21005f, 0x1ff }, { 0x21015f, 0x1ff }, { 0x21105f, 0x1ff }, @@ -150,7 +181,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x21215f, 0x1ff }, { 0x21305f, 0x1ff }, { 0x21315f, 0x1ff }, - { 0x55, 0x1ff }, { 0x1055, 0x1ff }, { 0x2055, 0x1ff }, @@ -161,32 +191,24 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x7055, 0x1ff }, { 0x8055, 0x1ff }, { 0x9055, 0x1ff }, - { 0x200c5, 0x19 }, { 0x1200c5, 0x7 }, { 0x2200c5, 0x7 }, - { 0x2002e, 0x2 }, { 0x12002e, 0x2 }, { 0x22002e, 0x2 }, - { 0x90204, 0x0 }, { 0x190204, 0x0 }, { 0x290204, 0x0 }, - - { 0x20024, 0xab }, + { 0x20024, 0x1ab }, { 0x2003a, 0x0 }, - - { 0x120024, 0xab }, + { 0x120024, 0x1ab }, { 0x2003a, 0x0 }, - - { 0x220024, 0xab }, + { 0x220024, 0x1ab }, { 0x2003a, 0x0 }, - { 0x20056, 0x3 }, { 0x120056, 0xa }, { 0x220056, 0xa }, - { 0x1004d, 0xe00 }, { 0x1014d, 0xe00 }, { 0x1104d, 0xe00 }, @@ -195,7 +217,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x1214d, 0xe00 }, { 0x1304d, 0xe00 }, { 0x1314d, 0xe00 }, - { 0x11004d, 0xe00 }, { 0x11014d, 0xe00 }, { 0x11104d, 0xe00 }, @@ -204,7 +225,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x11214d, 0xe00 }, { 0x11304d, 0xe00 }, { 0x11314d, 0xe00 }, - { 0x21004d, 0xe00 }, { 0x21014d, 0xe00 }, { 0x21104d, 0xe00 }, @@ -213,34 +233,30 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x21214d, 0xe00 }, { 0x21304d, 0xe00 }, { 0x21314d, 0xe00 }, - - { 0x10049, 0xfbe }, - { 0x10149, 0xfbe }, - { 0x11049, 0xfbe }, - { 0x11149, 0xfbe }, - { 0x12049, 0xfbe }, - { 0x12149, 0xfbe }, - { 0x13049, 0xfbe }, - { 0x13149, 0xfbe }, - - { 0x110049, 0xfbe }, - { 0x110149, 0xfbe }, - { 0x111049, 0xfbe }, - { 0x111149, 0xfbe }, - { 0x112049, 0xfbe }, - { 0x112149, 0xfbe }, - { 0x113049, 0xfbe }, - { 0x113149, 0xfbe }, - - { 0x210049, 0xfbe }, - { 0x210149, 0xfbe }, - { 0x211049, 0xfbe }, - { 0x211149, 0xfbe }, - { 0x212049, 0xfbe }, - { 0x212149, 0xfbe }, - { 0x213049, 0xfbe }, - { 0x213149, 0xfbe }, - + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, { 0x43, 0x63 }, { 0x1043, 0x63 }, { 0x2043, 0x63 }, @@ -251,7 +267,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x7043, 0x63 }, { 0x8043, 0x63 }, { 0x9043, 0x63 }, - { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, @@ -259,8 +274,7 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x120008, 0x64 }, { 0x220008, 0x19 }, { 0x20088, 0x9 }, - - { 0x200b2, 0x1d4 }, + { 0x200b2, 0xdc }, { 0x10043, 0x5a1 }, { 0x10143, 0x5a1 }, { 0x11043, 0x5a1 }, @@ -269,7 +283,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x12143, 0x5a1 }, { 0x13043, 0x5a1 }, { 0x13143, 0x5a1 }, - { 0x1200b2, 0xdc }, { 0x110043, 0x5a1 }, { 0x110143, 0x5a1 }, @@ -279,7 +292,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x112143, 0x5a1 }, { 0x113043, 0x5a1 }, { 0x113143, 0x5a1 }, - { 0x2200b2, 0xdc }, { 0x210043, 0x5a1 }, { 0x210143, 0x5a1 }, @@ -289,15 +301,12 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x212143, 0x5a1 }, { 0x213043, 0x5a1 }, { 0x213143, 0x5a1 }, - { 0x200fa, 0x1 }, { 0x1200fa, 0x1 }, { 0x2200fa, 0x1 }, - { 0x20019, 0x1 }, { 0x120019, 0x1 }, { 0x220019, 0x1 }, - { 0x200f0, 0x660 }, { 0x200f1, 0x0 }, { 0x200f2, 0x4444 }, @@ -306,21 +315,20 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x200f5, 0x0 }, { 0x200f6, 0x0 }, { 0x200f7, 0xf000 }, - { 0x20025, 0x0 }, - { 0x2002d, LPDDR4_PHY_DMIPinPresent }, - { 0x12002d, LPDDR4_PHY_DMIPinPresent }, - { 0x22002d, LPDDR4_PHY_DMIPinPresent }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, { 0x200c7, 0x21 }, - { 0x200ca, 0x24 }, { 0x1200c7, 0x21 }, - { 0x1200ca, 0x24 }, { 0x2200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200ca, 0x24 }, { 0x2200ca, 0x24 }, }; /* ddr phy trained csr */ -struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = { +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { { 0x200b2, 0x0 }, { 0x1200b2, 0x0 }, { 0x2200b2, 0x0 }, @@ -1041,309 +1049,164 @@ struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = { { 0x13730, 0x0 }, { 0x13830, 0x0 }, }; - /* P0 message block paremeter for training firmware */ -struct dram_cfg_param lpddr4_fsp0_cfg[] = { +struct dram_cfg_param ddr_fsp0_cfg[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x0 }, { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, { 0x54008, 0x131f }, { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, 0x0 }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, - { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, + { 0x54012, 0x110 }, { 0x54019, 0x2dd4 }, - { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401a, 0x31 }, { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d08 }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x2dd4 }, - { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54020, 0x31 }, { 0x54021, 0x4d66 }, - { 0x54022, 0x4d08 }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, - { 0x5402c, LPDDR4_CS }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, + { 0x5402c, 0x1 }, { 0x54032, 0xd400 }, - { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54033, 0x312d }, { 0x54034, 0x6600 }, - { 0x54035, 0x84d }, + { 0x54035, 0x4d }, { 0x54036, 0x4d }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54037, 0x1600 }, { 0x54038, 0xd400 }, - { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54039, 0x312d }, { 0x5403a, 0x6600 }, - { 0x5403b, 0x84d }, + { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; /* P1 message block paremeter for training firmware */ -struct dram_cfg_param lpddr4_fsp1_cfg[] = { +struct dram_cfg_param ddr_fsp1_cfg[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, { 0x54002, 0x101 }, { 0x54003, 0x190 }, { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },/* PHY Ron/Rtt */ - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, { 0x54008, 0x121f }, { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, 0x0 }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, - { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, + { 0x54012, 0x110 }, { 0x54019, 0x84 }, - { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401a, 0x31 }, { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d08 }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54020, 0x31 }, { 0x54021, 0x4d66 }, - { 0x54022, 0x4d08 }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, - { 0x5402c, LPDDR4_CS }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, + { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, - { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54033, 0x3100 }, { 0x54034, 0x6600 }, - { 0x54035, 0x84d }, + { 0x54035, 0x4d }, { 0x54036, 0x4d }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54039, 0x3100 }, { 0x5403a, 0x6600 }, - { 0x5403b, 0x84d }, + { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; -/* P1 message block paremeter for training firmware */ -struct dram_cfg_param lpddr4_fsp2_cfg[] = { +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, { 0x54002, 0x102 }, { 0x54003, 0x64 }, { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, { 0x54008, 0x121f }, { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, 0x0 }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, - { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, + { 0x54012, 0x110 }, { 0x54019, 0x84 }, - { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401a, 0x31 }, { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d08 }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54020, 0x31 }, { 0x54021, 0x4d66 }, - { 0x54022, 0x4d08 }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, - { 0x5402c, LPDDR4_CS }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, + { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, - { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54033, 0x3100 }, { 0x54034, 0x6600 }, - { 0x54035, 0x84d }, + { 0x54035, 0x4d }, { 0x54036, 0x4d }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54039, 0x3100 }, { 0x5403a, 0x6600 }, - { 0x5403b, 0x84d }, + { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; /* P0 2D message block paremeter for training firmware */ -struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x0 }, { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, { 0x54008, 0x61 }, { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, 0x0 }, - { 0x5400e, 0x0 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, - { 0x54011, 0x0 }, - { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, + { 0x54012, 0x110 }, { 0x54019, 0x2dd4 }, - { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401a, 0x31 }, { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d08 }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x2dd4 }, - { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54020, 0x31 }, { 0x54021, 0x4d66 }, - { 0x54022, 0x4d08 }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, - { 0x5402c, LPDDR4_CS }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, + { 0x5402c, 0x1 }, { 0x54032, 0xd400 }, - { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54033, 0x312d }, { 0x54034, 0x6600 }, - { 0x54035, 0x84d }, + { 0x54035, 0x4d }, { 0x54036, 0x4d }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54037, 0x1600 }, { 0x54038, 0xd400 }, - { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54039, 0x312d }, { 0x5403a, 0x6600 }, - { 0x5403b, 0x84d }, + { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; /* DRAM PHY init engine image */ -struct dram_cfg_param lpddr4_phy_pie[] = { +struct dram_cfg_param ddr_phy_pie[] = { { 0xd0000, 0x0 }, { 0x90000, 0x10 }, { 0x90001, 0x400 }, @@ -1854,6 +1717,10 @@ struct dram_cfg_param lpddr4_phy_pie[] = { { 0x90013, 0x6152 }, { 0x20010, 0x5a }, { 0x20011, 0x3 }, + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, { 0x40080, 0xe0 }, { 0x40081, 0x12 }, { 0x40082, 0xe0 }, @@ -1931,50 +1798,51 @@ struct dram_cfg_param lpddr4_phy_pie[] = { { 0x138b4, 0x1 }, { 0x2003a, 0x2 }, { 0xc0080, 0x2 }, - { 0xd0000, 0x1 }, + { 0xd0000, 0x1 } }; -struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { +struct dram_fsp_msg ddr_dram_fsp_msg[] = { { /* P0 3000mts 1D */ .drate = 3000, .fw_type = FW_1D_IMAGE, - .fsp_cfg = lpddr4_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), - }, - { - /* P0 3000mts 2D */ - .drate = 3000, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = lpddr4_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), }, { /* P1 400mts 1D */ .drate = 400, .fw_type = FW_1D_IMAGE, - .fsp_cfg = lpddr4_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), }, { - /* P1 100mts 1D */ + /* P2 100mts 1D */ .drate = 100, .fw_type = FW_1D_IMAGE, - .fsp_cfg = lpddr4_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), }, }; -/* lpddr4 timing config params on EVK board */ +/* ddr timing config params */ struct dram_timing_info dram_timing = { - .ddrc_cfg = lpddr4_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), - .ddrphy_cfg = lpddr4_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), - .fsp_msg = lpddr4_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), - .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr), - .ddrphy_pie = lpddr4_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, }; From 48ddafd9a42284457ac22d42572b88dbdb136fdd Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 19 Mar 2021 15:56:55 +0800 Subject: [PATCH 003/117] imx8mm_evk: Switch to new imx8mm evk board Update PMIC to use PCA9540, the legacy board not supported by NXP Signed-off-by: Ye Li --- arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 +- arch/arm/dts/imx8mm-evk.dtsi | 127 +++++++++++++++------------- board/freescale/imx8mm_evk/spl.c | 33 ++++---- configs/imx8mm_evk_defconfig | 2 +- 4 files changed, 86 insertions(+), 80 deletions(-) diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index e843a5648e..7f48912b49 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -114,11 +114,11 @@ u-boot,dm-spl; }; -&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} { u-boot,dm-spl; }; -&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi index 6518f088b2..60179e006d 100644 --- a/arch/arm/dts/imx8mm-evk.dtsi +++ b/arch/arm/dts/imx8mm-evk.dtsi @@ -126,115 +126,120 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450a"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; - regulator-ramp-delay = <1250>; + regulator-ramp-delay = <3125>; }; - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; + regulator-ramp-delay = <3125>; }; - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; }; - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - ldo1_reg: LDO1 { - regulator-name = "ldo1"; + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo2_reg: LDO2 { - regulator-name = "ldo2"; + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; + regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; }; + }; }; }; diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index 64bc60651d..4ef7f6f180 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -26,7 +26,7 @@ #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -94,7 +94,7 @@ static int power_init_board(void) struct udevice *dev; int ret; - ret = pmic_get("pmic@4b", &dev); + ret = pmic_get("pca9450@25", &dev); if (ret == -ENODEV) { puts("No pmic\n"); return 0; @@ -102,25 +102,26 @@ static int power_init_board(void) if (ret != 0) return ret; - /* decrease RESET key long push time from the default 10s to 10ms */ - pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0); + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); - /* unlock the PMIC regs */ - pmic_reg_write(dev, BD718XX_REGLOCK, 0x1); + /* Buck 1 DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); - /* increase VDD_SOC to typical value 0.85v before first DRAM access */ - pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f); + /* Set DVS1 to 0.8v for suspend */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10); - /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ - pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83); + /* increase VDD_DRAM to 0.95v for 3Ghz DDR */ + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C); -#ifndef CONFIG_IMX8M_LPDDR4 - /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ - pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28); -#endif + /* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */ + pmic_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a); - /* lock the PMIC regs */ - pmic_reg_write(dev, BD718XX_REGLOCK, 0x11); + /* set VDD_SNVS_0V8 from default 0.85V */ + pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); + + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); return 0; } diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index e22b7de56f..ae9e0626dd 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -83,7 +83,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y CONFIG_DM_PMIC=y -CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y From 15734d473fe0b3deb3f19fe2c4f2f21832b0c932 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Mar 2021 15:56:56 +0800 Subject: [PATCH 004/117] imx8mm/p: remove boot.cmd These files should not be in U-Boot repo Signed-off-by: Peng Fan --- board/freescale/imx8mm_evk/boot.cmd | 35 ----------------------------- board/freescale/imx8mp_evk/boot.cmd | 25 --------------------- 2 files changed, 60 deletions(-) delete mode 100644 board/freescale/imx8mm_evk/boot.cmd delete mode 100644 board/freescale/imx8mp_evk/boot.cmd diff --git a/board/freescale/imx8mm_evk/boot.cmd b/board/freescale/imx8mm_evk/boot.cmd deleted file mode 100644 index fdfceec263..0000000000 --- a/board/freescale/imx8mm_evk/boot.cmd +++ /dev/null @@ -1,35 +0,0 @@ -setenv bootargs console=${console} root=${mmcroot}; - -for boot_target in ${boot_targets}; -do - if test "${boot_target}" = "mmc1" ; then - if fatload mmc 1:${mmcpart} ${kernel_addr_r} ${image}; then - if fatload mmc 1:${mmcpart} ${fdt_addr} ${fdt_file}; then - echo Load image and .dtb from SD card(mmc1); - booti ${kernel_addr_r} - ${fdt_addr}; - exit; - fi - fi - fi - - if test "${boot_target}" = "mmc2" ; then - if fatload mmc 2:${mmcpart} ${kernel_addr_r} ${image}; then - if fatload mmc 2:${mmcpart} ${fdt_addr} ${fdt_file}; then - echo Load image and .dtb from eMMC(mmc2); - booti ${kernel_addr_r} - ${fdt_addr}; - exit; - fi - fi - fi - - if test "${boot_target}" = "dhcp" ; then - if dhcp ${kernel_addr_r} ${serverip}:${image}; then - if dhcp ${fdt_addr} ${serverip}:${fdt_file}; then - echo Load image and .dtb from net(dhcp); - booti ${kernel_addr_r} - ${fdt_addr}; - exit; - fi - fi - fi - -done diff --git a/board/freescale/imx8mp_evk/boot.cmd b/board/freescale/imx8mp_evk/boot.cmd deleted file mode 100644 index 10bcced774..0000000000 --- a/board/freescale/imx8mp_evk/boot.cmd +++ /dev/null @@ -1,25 +0,0 @@ -setenv bootargs console=${console} root=${mmcroot}; - -for boot_target in ${boot_targets}; -do - if test "${boot_target}" = "mmc1" ; then - if fatload mmc 1:${mmcpart} ${kernel_addr_r} ${image}; then - if fatload mmc 1:${mmcpart} ${fdt_addr} ${fdt_file}; then - echo Load image and .dtb from SD card(mmc1); - booti ${kernel_addr_r} - ${fdt_addr}; - exit; - fi - fi - fi - - if test "${boot_target}" = "mmc2" ; then - if fatload mmc 2:${mmcpart} ${kernel_addr_r} ${image}; then - if fatload mmc 2:${mmcpart} ${fdt_addr} ${fdt_file}; then - echo Load image and .dtb from eMMC(mmc2); - booti ${kernel_addr_r} - ${fdt_addr}; - exit; - fi - fi - fi - -done From f53e1c25d4ae7d1a0cddbecb36165dcc7413f180 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Mar 2021 15:56:57 +0800 Subject: [PATCH 005/117] imx8mm_evk: add/cleanup variable for distro Add fdt_addr_r fdtfile which used by distro boot Clean up environment Signed-off-by: Peng Fan --- include/configs/imx8mm_evk.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index fd9a6cbb8c..8f3dd8fb61 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -44,13 +44,13 @@ /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ - "scriptaddr=0x43500000\0" \ - "kernel_addr_r=0x40880000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "image=Image\0" \ "console=ttymxc1,115200\0" \ - "fdt_addr=0x43000000\0" \ + "fdt_addr_r=0x43000000\0" \ "boot_fit=no\0" \ - "fdt_file=imx8mm-evk.dtb\0" \ + "fdtfile=imx8mm-evk.dtb\0" \ "initrd_addr=0x43800000\0" \ "bootm_size=0x10000000\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ From a02735938e20d45e7bce934de927f153bde5bf95 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Mar 2021 15:56:58 +0800 Subject: [PATCH 006/117] imx8mp_evk: add/cleanup variable for distro Add fdt_addr_r fdtfile which used by distro boot Clean up environment Signed-off-by: Peng Fan --- include/configs/imx8mp_evk.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 61a5c6fb79..d1bc09e825 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -68,13 +68,13 @@ /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ - "scriptaddr=0x43500000\0" \ - "kernel_addr_r=0x40880000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "image=Image\0" \ "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ - "fdt_addr=0x43000000\0" \ + "fdt_addr_r=0x43000000\0" \ "boot_fdt=try\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "initrd_addr=0x43800000\0" \ "bootm_size=0x10000000\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ From 31c878f76ec60abd0f7a27be44dc21c83a45429d Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Fri, 19 Mar 2021 15:56:59 +0800 Subject: [PATCH 007/117] imx8mp: ddr: Add inline ECC feature support Add inline ECC support for lpddr4 on imx8mp-evk. And add a config which can enable/disable inline ECC feature for lpddr4 on imx8mp-evk board. Signed-off-by: Sherry Sun Signed-off-by: Peng Fan --- board/freescale/imx8mp_evk/lpddr4_timing.c | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c index 7658262b37..cc9c6926be 100644 --- a/board/freescale/imx8mp_evk/lpddr4_timing.c +++ b/board/freescale/imx8mp_evk/lpddr4_timing.c @@ -14,6 +14,9 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400020, 0x1323 }, { 0x3d400024, 0x1e84800 }, { 0x3d400064, 0x7a0118 }, +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC + { 0x3d400070, 0x01027f44 }, +#endif { 0x3d4000d0, 0xc00307a3 }, { 0x3d4000d4, 0xc50000 }, { 0x3d4000dc, 0xf4003f }, @@ -45,12 +48,21 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d4001c4, 0x1 }, { 0x3d4000f4, 0xc99 }, { 0x3d400108, 0x9121c1c }, +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC + { 0x3d400200, 0x13 }, + { 0x3d40020c, 0x13131300 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x50505 }, + { 0x3d400214, 0x4040404 }, + { 0x3d400218, 0x68040404 }, +#else { 0x3d400200, 0x16 }, { 0x3d40020c, 0x0 }, { 0x3d400210, 0x1f1f }, { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x68070707 }, +#endif { 0x3d40021c, 0xf08 }, { 0x3d400250, 0x00001705 }, { 0x3d400254, 0x2c }, @@ -1846,3 +1858,18 @@ struct dram_timing_info dram_timing = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 4000, 400, 100, }, }; + +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC +void board_dram_ecc_scrub(void) +{ + /* add inline scrb function MPlus spcific */ + /* scrub 0-1.75G */ + ddrc_inline_ecc_scrub(0x0, 0x1bffffff); + /* scrub 2-3.75G */ + ddrc_inline_ecc_scrub(0x20000000, 0x3bffffff); + /* scrub 4-5.75G */ + ddrc_inline_ecc_scrub(0x40000000, 0x5bffffff); + /* set scruber read range 0-6G */ + ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff); +} +#endif From c0c78d24bd15fdb53abc5457432345a877988a8e Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 19 Mar 2021 15:57:00 +0800 Subject: [PATCH 008/117] imx8mp_evk: Update LPDDR4 timing for new FW 202006 After switching to new LPDDR4 firmware 202006 version, have to update the LPDDR4 timing accordingly from RPA tool. Signed-off-by: Ye Li Tested-by: Sherry Sun Tested-by: Jacky Bai Reviewed-by: Jacky Bai Signed-off-by: Peng Fan --- board/freescale/imx8mp_evk/lpddr4_timing.c | 189 +++++++++++---------- 1 file changed, 99 insertions(+), 90 deletions(-) diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c index cc9c6926be..eff0a93860 100644 --- a/board/freescale/imx8mp_evk/lpddr4_timing.c +++ b/board/freescale/imx8mp_evk/lpddr4_timing.c @@ -15,14 +15,17 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400024, 0x1e84800 }, { 0x3d400064, 0x7a0118 }, #ifdef CONFIG_IMX8M_DRAM_INLINE_ECC - { 0x3d400070, 0x01027f44 }, + { 0x3d400070, 0x1027f54 }, +#else + { 0x3d400070, 0x1027f10 }, #endif + { 0x3d400074, 0x7b0 }, { 0x3d4000d0, 0xc00307a3 }, { 0x3d4000d4, 0xc50000 }, { 0x3d4000dc, 0xf4003f }, { 0x3d4000e0, 0x330000 }, - { 0x3d4000e8, 0x460048 }, - { 0x3d4000ec, 0x150048 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, { 0x3d400100, 0x2028222a }, { 0x3d400104, 0x807bf }, { 0x3d40010c, 0xe0e000 }, @@ -64,26 +67,26 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400218, 0x68070707 }, #endif { 0x3d40021c, 0xf08 }, - { 0x3d400250, 0x00001705 }, + { 0x3d400250, 0x1705 }, { 0x3d400254, 0x2c }, { 0x3d40025c, 0x4000030 }, { 0x3d400264, 0x900093e7 }, { 0x3d40026c, 0x2005574 }, { 0x3d400400, 0x111 }, - { 0x3d400404, 0x72ff }, + { 0x3d400404, 0x72ff }, { 0x3d400408, 0x72ff }, { 0x3d400494, 0x2100e07 }, { 0x3d400498, 0x620096 }, { 0x3d40049c, 0x1100e07 }, { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x21 }, - { 0x3d402024, 0x7d00 }, - { 0x3d402050, 0x20d040 }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, { 0x3d402064, 0xc001c }, { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x310000 }, - { 0x3d4020e8, 0x66004d }, - { 0x3d4020ec, 0x16004d }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, { 0x3d402100, 0xa040305 }, { 0x3d402104, 0x30407 }, { 0x3d402108, 0x203060b }, @@ -101,14 +104,14 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, { 0x3d4020f4, 0xc99 }, - { 0x3d403020, 0x21 }, - { 0x3d403024, 0x30d400 }, - { 0x3d403050, 0x20d040 }, + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, { 0x3d403064, 0x30007 }, { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x310000 }, - { 0x3d4030e8, 0x66004d }, - { 0x3d4030ec, 0x16004d }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, { 0x3d403100, 0xa010102 }, { 0x3d403104, 0x30404 }, { 0x3d403108, 0x203060b }, @@ -125,6 +128,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d403190, 0x3818200 }, { 0x3d403194, 0x80303 }, { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, { 0x3d400028, 0x0 }, }; @@ -1114,28 +1118,28 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x54012, 0x310 }, { 0x54019, 0x84 }, { 0x5401a, 0x33 }, - { 0x5401b, 0x4846 }, + { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, - { 0x5401e, 0x15 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, { 0x54020, 0x33 }, - { 0x54021, 0x4846 }, + { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, - { 0x54024, 0x15 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, { 0x54032, 0x8400 }, { 0x54033, 0x3300 }, - { 0x54034, 0x4600 }, + { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, - { 0x54037, 0x1500 }, + { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, { 0x54039, 0x3300 }, - { 0x5403a, 0x4600 }, + { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, - { 0x5403d, 0x1500 }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; @@ -1154,28 +1158,28 @@ struct dram_cfg_param ddr_fsp2_cfg[] = { { 0x54012, 0x310 }, { 0x54019, 0x84 }, { 0x5401a, 0x33 }, - { 0x5401b, 0x4846 }, + { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, - { 0x5401e, 0x15 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, { 0x54020, 0x33 }, - { 0x54021, 0x4846 }, + { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, - { 0x54024, 0x15 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, { 0x54032, 0x8400 }, { 0x54033, 0x3300 }, - { 0x54034, 0x4600 }, + { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, - { 0x54037, 0x1500 }, + { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, { 0x54039, 0x3300 }, - { 0x5403a, 0x4600 }, + { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, - { 0x5403d, 0x1500 }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; @@ -1640,67 +1644,58 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0x90155, 0x20 }, { 0x90156, 0x2aa }, { 0x90157, 0x9 }, - { 0x90158, 0x0 }, - { 0x90159, 0x400 }, - { 0x9015a, 0x10e }, - { 0x9015b, 0x8 }, - { 0x9015c, 0xe8 }, - { 0x9015d, 0x109 }, - { 0x9015e, 0x0 }, - { 0x9015f, 0x8140 }, - { 0x90160, 0x10c }, - { 0x90161, 0x10 }, - { 0x90162, 0x8138 }, - { 0x90163, 0x10c }, - { 0x90164, 0x8 }, - { 0x90165, 0x7c8 }, - { 0x90166, 0x101 }, - { 0x90167, 0x8 }, - { 0x90168, 0x448 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, { 0x90169, 0x109 }, - { 0x9016a, 0xf }, - { 0x9016b, 0x7c0 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, { 0x9016c, 0x109 }, - { 0x9016d, 0x0 }, - { 0x9016e, 0xe8 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, { 0x9016f, 0x109 }, - { 0x90170, 0x47 }, - { 0x90171, 0x630 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, { 0x90172, 0x109 }, - { 0x90173, 0x8 }, - { 0x90174, 0x618 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, { 0x90175, 0x109 }, { 0x90176, 0x8 }, - { 0x90177, 0xe0 }, - { 0x90178, 0x109 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, { 0x90179, 0x0 }, - { 0x9017a, 0x7c8 }, + { 0x9017a, 0x478 }, { 0x9017b, 0x109 }, - { 0x9017c, 0x8 }, - { 0x9017d, 0x8140 }, - { 0x9017e, 0x10c }, - { 0x9017f, 0x0 }, - { 0x90180, 0x478 }, - { 0x90181, 0x109 }, - { 0x90182, 0x0 }, - { 0x90183, 0x1 }, - { 0x90184, 0x8 }, - { 0x90185, 0x8 }, - { 0x90186, 0x4 }, - { 0x90187, 0x8 }, - { 0x90188, 0x8 }, - { 0x90189, 0x7c8 }, - { 0x9018a, 0x101 }, - { 0x90006, 0x0 }, - { 0x90007, 0x0 }, - { 0x90008, 0x8 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, { 0x90009, 0x0 }, - { 0x9000a, 0x0 }, - { 0x9000b, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, { 0x9001f, 0x29 }, - { 0x90026, 0x6a }, + { 0x90026, 0x68 }, { 0x400d0, 0x0 }, { 0x400d1, 0x101 }, { 0x400d2, 0x105 }, @@ -1710,6 +1705,7 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0x400d6, 0x20a }, { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, { 0x2000b, 0x7d }, { 0x2000c, 0xfa }, { 0x2000d, 0x9c4 }, @@ -1862,14 +1858,27 @@ struct dram_timing_info dram_timing = { #ifdef CONFIG_IMX8M_DRAM_INLINE_ECC void board_dram_ecc_scrub(void) { - /* add inline scrb function MPlus spcific */ - /* scrub 0-1.75G */ - ddrc_inline_ecc_scrub(0x0, 0x1bffffff); - /* scrub 2-3.75G */ - ddrc_inline_ecc_scrub(0x20000000, 0x3bffffff); - /* scrub 4-5.75G */ - ddrc_inline_ecc_scrub(0x40000000, 0x5bffffff); - /* set scruber read range 0-6G */ + ddrc_inline_ecc_scrub(0x0, 0x3ffffff); + ddrc_inline_ecc_scrub(0x20000000, 0x23ffffff); + ddrc_inline_ecc_scrub(0x40000000, 0x43ffffff); + ddrc_inline_ecc_scrub(0x4000000, 0x7ffffff); + ddrc_inline_ecc_scrub(0x24000000, 0x27ffffff); + ddrc_inline_ecc_scrub(0x44000000, 0x47ffffff); + ddrc_inline_ecc_scrub(0x8000000, 0xbffffff); + ddrc_inline_ecc_scrub(0x28000000, 0x2bffffff); + ddrc_inline_ecc_scrub(0x48000000, 0x4bffffff); + ddrc_inline_ecc_scrub(0xc000000, 0xfffffff); + ddrc_inline_ecc_scrub(0x2c000000, 0x2fffffff); + ddrc_inline_ecc_scrub(0x4c000000, 0x4fffffff); + ddrc_inline_ecc_scrub(0x10000000, 0x13ffffff); + ddrc_inline_ecc_scrub(0x30000000, 0x33ffffff); + ddrc_inline_ecc_scrub(0x50000000, 0x53ffffff); + ddrc_inline_ecc_scrub(0x14000000, 0x17ffffff); + ddrc_inline_ecc_scrub(0x34000000, 0x37ffffff); + ddrc_inline_ecc_scrub(0x54000000, 0x57ffffff); + ddrc_inline_ecc_scrub(0x18000000, 0x1bffffff); + ddrc_inline_ecc_scrub(0x38000000, 0x3bffffff); + ddrc_inline_ecc_scrub(0x58000000, 0x5bffffff); ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff); } #endif From d437230954ddd3a18a21eb0dfe5e5d302b526513 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 19 Mar 2021 15:57:01 +0800 Subject: [PATCH 009/117] imx8mp_evk: Update LPDDR4 refresh time Use more safer refresh time value for 6GB LPDDR4 on this EVK board. Update the parameters for every frequency point. Signed-off-by: Ye Li Reviewed-by: Jacky Bai Signed-off-by: Peng Fan --- board/freescale/imx8mp_evk/lpddr4_timing.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c index eff0a93860..0759502ba3 100644 --- a/board/freescale/imx8mp_evk/lpddr4_timing.c +++ b/board/freescale/imx8mp_evk/lpddr4_timing.c @@ -13,7 +13,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400000, 0xa3080020 }, { 0x3d400020, 0x1323 }, { 0x3d400024, 0x1e84800 }, - { 0x3d400064, 0x7a0118 }, + { 0x3d400064, 0x7a017c }, #ifdef CONFIG_IMX8M_DRAM_INLINE_ECC { 0x3d400070, 0x1027f54 }, #else @@ -35,7 +35,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d40011c, 0x501 }, { 0x3d400130, 0x20800 }, { 0x3d400134, 0xe100002 }, - { 0x3d400138, 0x120 }, + { 0x3d400138, 0x184 }, { 0x3d400144, 0xc80064 }, { 0x3d400180, 0x3e8001e }, { 0x3d400184, 0x3207a12 }, @@ -82,7 +82,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402020, 0x1021 }, { 0x3d402024, 0x30d400 }, { 0x3d402050, 0x20d000 }, - { 0x3d402064, 0xc001c }, + { 0x3d402064, 0xc0026 }, { 0x3d4020dc, 0x840000 }, { 0x3d4020e0, 0x330000 }, { 0x3d4020e8, 0x660048 }, @@ -97,7 +97,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d40211c, 0x301 }, { 0x3d402130, 0x20300 }, { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0x1d }, + { 0x3d402138, 0x27 }, { 0x3d402144, 0x14000a }, { 0x3d402180, 0x640004 }, { 0x3d402190, 0x3818200 }, @@ -107,7 +107,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d403020, 0x1021 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, - { 0x3d403064, 0x30007 }, + { 0x3d403064, 0x3000a }, { 0x3d4030dc, 0x840000 }, { 0x3d4030e0, 0x330000 }, { 0x3d4030e8, 0x660048 }, @@ -122,7 +122,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d40311c, 0x301 }, { 0x3d403130, 0x20300 }, { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0x8 }, + { 0x3d403138, 0xa }, { 0x3d403144, 0x50003 }, { 0x3d403180, 0x190004 }, { 0x3d403190, 0x3818200 }, From c994d3d203b8cb6259fae689df41c4386835a9a9 Mon Sep 17 00:00:00 2001 From: "haidong.zheng" Date: Fri, 19 Mar 2021 15:57:02 +0800 Subject: [PATCH 010/117] imx8mp: refine power on imx8mp board VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng Signed-off-by: Peng Fan --- board/freescale/imx8mp_evk/lpddr4_timing.c | 166 +++++++++++++++++++++ board/freescale/imx8mp_evk/spl.c | 5 + drivers/ddr/imx/imx8m/Kconfig | 8 + 3 files changed, 179 insertions(+) mode change 100644 => 100755 board/freescale/imx8mp_evk/lpddr4_timing.c diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c old mode 100644 new mode 100755 index 0759502ba3..9d069fc27a --- a/board/freescale/imx8mp_evk/lpddr4_timing.c +++ b/board/freescale/imx8mp_evk/lpddr4_timing.c @@ -11,6 +11,16 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x1 }, { 0x3d400000, 0xa3080020 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x3d400020, 0x223 }, + { 0x3d400024, 0x124f800 }, + { 0x3d400064, 0x4900a8 }, + { 0x3d400070, 0x1027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc0030495 }, + { 0x3d4000d4, 0x770000 }, + { 0x3d4000dc, 0xc40024 }, +#else { 0x3d400020, 0x1323 }, { 0x3d400024, 0x1e84800 }, { 0x3d400064, 0x7a017c }, @@ -23,9 +33,29 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d4000d0, 0xc00307a3 }, { 0x3d4000d4, 0xc50000 }, { 0x3d4000dc, 0xf4003f }, +#endif { 0x3d4000e0, 0x330000 }, { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x3d400100, 0x1618141a }, + { 0x3d400104, 0x504a6 }, + { 0x3d40010c, 0x909000 }, + { 0x3d400110, 0xb04060b }, + { 0x3d400114, 0x2030909 }, + { 0x3d400118, 0x1010006 }, + { 0x3d40011c, 0x301 }, + { 0x3d400130, 0x20500 }, + { 0x3d400134, 0xb100002 }, + { 0x3d400138, 0xad }, + { 0x3d400144, 0x78003c }, + { 0x3d400180, 0x2580012 }, + { 0x3d400184, 0x1e0493e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x4938208 }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1308 }, +#else { 0x3d400100, 0x2028222a }, { 0x3d400104, 0x807bf }, { 0x3d40010c, 0xe0e000 }, @@ -43,6 +73,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400190, 0x49f820e }, { 0x3d400194, 0x80303 }, { 0x3d4001b4, 0x1f0e }, +#endif { 0x3d4001a0, 0xe0400018 }, { 0x3d4001a4, 0xdf00e4 }, { 0x3d4001a8, 0x80000000 }, @@ -50,6 +81,30 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d4001c0, 0x1 }, { 0x3d4001c4, 0x1 }, { 0x3d4000f4, 0xc99 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x3d400108, 0x60c1514 }, + { 0x3d400200, 0x16 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x68070707 }, + { 0x3d40021c, 0xf08 }, + { 0x3d400250, 0x1f05 }, + { 0x3d400254, 0x1f }, + { 0x3d400264, 0x90003ff }, + { 0x3d40026c, 0x20003ff }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x1000e00 }, + { 0x3d400498, 0x3ff0000 }, + { 0x3d40049c, 0x1000e00 }, + { 0x3d4004a0, 0x3ff0000 }, + { 0x3d402020, 0x21 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, +#else { 0x3d400108, 0x9121c1c }, #ifdef CONFIG_IMX8M_DRAM_INLINE_ECC { 0x3d400200, 0x13 }, @@ -83,6 +138,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402024, 0x30d400 }, { 0x3d402050, 0x20d000 }, { 0x3d402064, 0xc0026 }, +#endif { 0x3d4020dc, 0x840000 }, { 0x3d4020e0, 0x330000 }, { 0x3d4020e8, 0x660048 }, @@ -104,10 +160,17 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, { 0x3d4020f4, 0xc99 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x3d403020, 0x21 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, +#else { 0x3d403020, 0x1021 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, { 0x3d403064, 0x3000a }, +#endif { 0x3d4030dc, 0x840000 }, { 0x3d4030e0, 0x330000 }, { 0x3d4030e8, 0x660048 }, @@ -200,7 +263,11 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x7055, 0x1ff }, { 0x8055, 0x1ff }, { 0x9055, 0x1ff }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x200c5, 0xa }, +#else { 0x200c5, 0x18 }, +#endif { 0x1200c5, 0x7 }, { 0x2200c5, 0x7 }, { 0x2002e, 0x2 }, @@ -279,7 +346,11 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x20008, 0x258 }, +#else { 0x20008, 0x3e8 }, +#endif { 0x120008, 0x64 }, { 0x220008, 0x19 }, { 0x20088, 0x9 }, @@ -1066,6 +1137,38 @@ struct dram_cfg_param ddr_ddrphy_trained_csr[] = { /* P0 message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_cfg[] = { +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x24c4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x24c4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xc400 }, + { 0x54033, 0x3324 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xc400 }, + { 0x54039, 0x3324 }, +#else { 0xd0000, 0x0 }, { 0x54003, 0xfa0 }, { 0x54004, 0x2 }, @@ -1096,6 +1199,7 @@ struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x54037, 0x1600 }, { 0x54038, 0xf400 }, { 0x54039, 0x333f }, +#endif { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1186,6 +1290,39 @@ struct dram_cfg_param ddr_fsp2_cfg[] = { /* P0 2D message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x24c4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x24c4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xc400 }, + { 0x54033, 0x3324 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xc400 }, + { 0x54039, 0x3324 }, +#else { 0x54003, 0xfa0 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, @@ -1217,6 +1354,7 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0x54037, 0x1600 }, { 0x54038, 0xf400 }, { 0x54039, 0x333f }, +#endif { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1705,10 +1843,16 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0x400d6, 0x20a }, { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x2000b, 0x4b }, + { 0x2000c, 0x96 }, + { 0x2000d, 0x5dc }, +#else { 0x200be, 0x3 }, { 0x2000b, 0x7d }, { 0x2000c, 0xfa }, { 0x2000d, 0x9c4 }, +#endif { 0x2000e, 0x2c }, { 0x12000b, 0xc }, { 0x12000c, 0x19 }, @@ -1728,6 +1872,12 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0x90013, 0x6152 }, { 0x20010, 0x5a }, { 0x20011, 0x3 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, +#endif { 0x40080, 0xe0 }, { 0x40081, 0x12 }, { 0x40082, 0xe0 }, @@ -1811,8 +1961,13 @@ struct dram_cfg_param ddr_phy_pie[] = { struct dram_fsp_msg ddr_dram_fsp_msg[] = { { +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + /* P0 2400mts 1D */ + .drate = 2400, +#else /* P0 4000mts 1D */ .drate = 4000, +#endif .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), @@ -1832,8 +1987,13 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), }, { +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + /* P0 2400mts 2D */ + .drate = 2400, +#else /* P0 4000mts 2D */ .drate = 4000, +#endif .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), @@ -1852,9 +2012,14 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + .fsp_table = { 2400, 400, 100, }, +#else .fsp_table = { 4000, 400, 100, }, +#endif }; +#ifndef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS #ifdef CONFIG_IMX8M_DRAM_INLINE_ECC void board_dram_ecc_scrub(void) { @@ -1882,3 +2047,4 @@ void board_dram_ecc_scrub(void) ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff); } #endif +#endif diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index ebfd94dc1f..3f043c2b2e 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -84,7 +84,12 @@ int power_init_board(void) * Enable DVS control through PMIC_STBY_REQ and * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ +#ifdef CONFIG_IMX8M_VDD_SOC_850MV + /* set DVS0 to 0.85v for special case*/ + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14); +#else pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); +#endif pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig index a5f5524fbe..a90b7db494 100644 --- a/drivers/ddr/imx/imx8m/Kconfig +++ b/drivers/ddr/imx/imx8m/Kconfig @@ -36,4 +36,12 @@ config IMX8M_DRAM_INLINE_ECC help Select this config if you want to use inline ecc feature for imx8mp-evk board. + +config IMX8M_VDD_SOC_850MV + bool "imx8mp change the vdd_soc voltage to 850mv" + depends on IMX8MP + +config IMX8M_LPDDR4_FREQ0_2400MTS + bool "imx8m PDDR4 freq0 change from 4000MTS to 2400MTS" + endmenu From 2212542f9b640f049539e08024a0073711d2a8ff Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Mar 2021 15:57:03 +0800 Subject: [PATCH 011/117] imx8mp_evk: spl: clean up including headers Clean up the including headers Signed-off-by: Peng Fan --- board/freescale/imx8mp_evk/spl.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index 3f043c2b2e..ef14cfc227 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -5,30 +5,21 @@ */ #include -#include -#include #include -#include #include #include #include #include -#include -#include -#include -#include +#include #include #include #include -#include - -#include -#include #include +#include #include -#include -#include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; From 41037bc47c293dc6cdf6c7f03ffefc35b4217bba Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Mar 2021 15:57:04 +0800 Subject: [PATCH 012/117] imx8mp_evk: Increase VDD_ARM to 0.95v Overdrive voltage There is a frequency/timing limitation for SOC and ARM, if SOC is OD voltage/OD freq, then ARM can't run at ND voltage/1.2Ghz, it may have timing risk from SOC to ARM. Current VDD_SOC is set to 0.95v OD voltage in SPL, and kernel will increase bus clocks to OD frequency before it increases ARM voltage. So to conform to the limitation, we'd better increases VDD_ARM to OD voltage in SPL. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- board/freescale/imx8mp_evk/spl.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index ef14cfc227..6ccf5ac8fa 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -35,6 +35,16 @@ void spl_dram_init(void) void spl_board_init(void) { + /* + * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does + * not allow to change it. Should set the clock after PMIC + * setting done. Default is 400Mhz (system_pll1_800m with div = 2) + * set by ROM for ND VDD_SOC + */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); + puts("Normal Boot\n"); } @@ -84,6 +94,10 @@ int power_init_board(void) pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + /* Kernel uses OD/OD freq for SOC */ + /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ + pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + /* set WDOG_B_CFG to cold reset */ pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); From fd60fe7e61ba33f5101034f7183551708b1fecee Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Fri, 19 Mar 2021 15:57:05 +0800 Subject: [PATCH 013/117] imx8mn: Update the DDR4 timing script on imx8mn ddr4 evk On i.MX8MN, we can only support DLL-ON mode only, so update the timing to support 2400mts & 1066mts setpoint. Signed-off-by: Jacky Bai Reviewed-by: Ye Li Signed-off-by: Peng Fan --- board/freescale/imx8mn_evk/ddr4_timing.c | 1057 +++++++++------------- 1 file changed, 449 insertions(+), 608 deletions(-) diff --git a/board/freescale/imx8mn_evk/ddr4_timing.c b/board/freescale/imx8mn_evk/ddr4_timing.c index cfd193a78d..f1509e2159 100644 --- a/board/freescale/imx8mn_evk/ddr4_timing.c +++ b/board/freescale/imx8mn_evk/ddr4_timing.c @@ -1,121 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2019 NXP * - * SPDX-License-Identifier: GPL-2.0+ - * * Generated code from MX8M_DDR_tool - * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga */ #include #include struct dram_cfg_param ddr_ddrc_cfg[] = { - {0x3d400000, 0x81040010}, - {0x3d400030, 0x00000020}, - {0x3d400034, 0x00221306}, - {0x3d400050, 0x00210070}, - {0x3d400054, 0x00010008}, - {0x3d400060, 0x00000000}, - {0x3d400064, 0x0092014a}, - {0x3d4000c0, 0x00000000}, - {0x3d4000c4, 0x00001000}, - {0x3d4000d0, 0xc0030126}, - {0x3d4000d4, 0x00770000}, - {0x3d4000dc, 0x08340105}, - {0x3d4000e0, 0x00180200}, - {0x3d4000e4, 0x00110000}, - {0x3d4000e8, 0x02000740}, - {0x3d4000ec, 0x00000850}, - {0x3d4000f4, 0x00000ec7}, - {0x3d400100, 0x11122914}, - {0x3d400104, 0x0004051c}, - {0x3d400108, 0x0608050d}, - {0x3d40010c, 0x0000400c}, - {0x3d400110, 0x08030409}, - {0x3d400114, 0x06060403}, - {0x3d40011c, 0x00000606}, - {0x3d400120, 0x07070d0c}, - {0x3d400124, 0x0002040a}, - {0x3d40012c, 0x1809010e}, - {0x3d400130, 0x00000008}, - {0x3d40013c, 0x00000000}, - {0x3d400180, 0x01000040}, - {0x3d400184, 0x0000493e}, - {0x3d400190, 0x038b8207}, - {0x3d400194, 0x02020303}, - {0x3d400198, 0x07f04011}, - {0x3d40019c, 0x000000b0}, - {0x3d4001a0, 0xe0400018}, - {0x3d4001a4, 0x0048005a}, - {0x3d4001a8, 0x80000000}, - {0x3d4001b0, 0x00000001}, - {0x3d4001b4, 0x00000b07}, - {0x3d4001b8, 0x00000004}, - {0x3d4001c0, 0x00000001}, - {0x3d4001c4, 0x00000000}, - {0x3d400240, 0x06000610}, - {0x3d400244, 0x00001323}, - {0x3d400200, 0x00003f1f}, - {0x3d400204, 0x003f0909}, - {0x3d400208, 0x01010100}, - {0x3d40020c, 0x01010101}, - {0x3d400210, 0x00001f1f}, - {0x3d400214, 0x07070707}, - {0x3d400218, 0x07070707}, - {0x3d40021c, 0x00000f07}, - {0x3d400220, 0x00003f01}, - {0x3d402050, 0x00210070}, - {0x3d402064, 0x00180037}, - {0x3d4020dc, 0x00000105}, - {0x3d4020e0, 0x00000000}, - {0x3d4020e8, 0x02000740}, - {0x3d4020ec, 0x00000050}, - {0x3d402100, 0x08030604}, - {0x3d402104, 0x00020205}, - {0x3d402108, 0x05050309}, - {0x3d40210c, 0x0000400c}, - {0x3d402110, 0x02030202}, - {0x3d402114, 0x03030202}, - {0x3d402118, 0x0a070008}, - {0x3d40211c, 0x00000d09}, - {0x3d402120, 0x08084b09}, - {0x3d402124, 0x00020308}, - {0x3d402128, 0x000f0d06}, - {0x3d40212c, 0x12060111}, - {0x3d402130, 0x00000008}, - {0x3d40213c, 0x00000000}, - {0x3d402180, 0x01000040}, - {0x3d402190, 0x03848204}, - {0x3d402194, 0x02020303}, - {0x3d4021b4, 0x00000404}, - {0x3d4021b8, 0x00000004}, - {0x3d402240, 0x07000600}, - {0x3d403050, 0x00210070}, - {0x3d403064, 0x0006000d}, - {0x3d4030dc, 0x00000105}, - {0x3d4030e0, 0x00000000}, - {0x3d4030e8, 0x02000740}, - {0x3d4030ec, 0x00000050}, - {0x3d403100, 0x07010101}, - {0x3d403104, 0x00020202}, - {0x3d403108, 0x05050309}, - {0x3d40310c, 0x0000400c}, - {0x3d403110, 0x01030201}, - {0x3d403114, 0x03030202}, - {0x3d40311c, 0x00000303}, - {0x3d403120, 0x02020d02}, - {0x3d403124, 0x00020208}, - {0x3d403128, 0x000f0d06}, - {0x3d40312c, 0x0e02010e}, - {0x3d403130, 0x00000008}, - {0x3d40313c, 0x00000000}, - {0x3d403180, 0x01000040}, - {0x3d403190, 0x03848204}, - {0x3d403194, 0x02020303}, - {0x3d4031b4, 0x00000404}, - {0x3d4031b8, 0x00000004}, - {0x3d403240, 0x07000600}, + /** Initialize DDRC registers **/ + { 0x3d400000, 0x81040010 }, + { 0x3d400030, 0x20 }, + { 0x3d400034, 0x221306 }, + { 0x3d400050, 0x210070 }, + { 0x3d400054, 0x10008 }, + { 0x3d400060, 0x0 }, + { 0x3d400064, 0x92014a }, + { 0x3d4000c0, 0x0 }, + { 0x3d4000c4, 0x1000 }, + { 0x3d4000d0, 0xc0030126 }, + { 0x3d4000d4, 0x770000 }, + { 0x3d4000dc, 0x8340105 }, + { 0x3d4000e0, 0x180200 }, + { 0x3d4000e4, 0x110000 }, + { 0x3d4000e8, 0x2000600 }, + { 0x3d4000ec, 0x810 }, + { 0x3d4000f0, 0x20 }, + { 0x3d4000f4, 0xec7 }, + { 0x3d400100, 0x11122914 }, + { 0x3d400104, 0x4051c }, + { 0x3d400108, 0x608050d }, + { 0x3d40010c, 0x400c }, + { 0x3d400110, 0x8030409 }, + { 0x3d400114, 0x6060403 }, + { 0x3d40011c, 0x606 }, + { 0x3d400120, 0x7070d0c }, + { 0x3d400124, 0x2040a }, + { 0x3d40012c, 0x1809010e }, + { 0x3d400130, 0x8 }, + { 0x3d40013c, 0x0 }, + { 0x3d400180, 0x1000040 }, + { 0x3d400184, 0x493e }, + { 0x3d400190, 0x38b8207 }, + { 0x3d400194, 0x2020303 }, + { 0x3d400198, 0x7f04011 }, + { 0x3d40019c, 0xb0 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0x48005a }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x1 }, + { 0x3d4001b4, 0xb07 }, + { 0x3d4001b8, 0x4 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x3f1f }, + { 0x3d400204, 0x3f0909 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf07 }, + { 0x3d400220, 0x3f01 }, + { 0x3d400240, 0x6000610 }, + { 0x3d400244, 0x1323 }, + { 0x3d400400, 0x100 }, /* performance setting */ { 0x3d400250, 0x00001f05 }, @@ -126,141 +78,136 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400498, 0x03ff0000 }, { 0x3d40049c, 0x01000e00 }, { 0x3d4004a0, 0x03ff0000 }, + + { 0x3d402050, 0x210070 }, + { 0x3d402064, 0x400093 }, + { 0x3d4020dc, 0x105 }, + { 0x3d4020e0, 0x0 }, + { 0x3d4020e8, 0x2000600 }, + { 0x3d4020ec, 0x10 }, + { 0x3d402100, 0xb081209 }, + { 0x3d402104, 0x2020d }, + { 0x3d402108, 0x5050309 }, + { 0x3d40210c, 0x400c }, + { 0x3d402110, 0x5030206 }, + { 0x3d402114, 0x3030202 }, + { 0x3d40211c, 0x303 }, + { 0x3d402120, 0x4040d06 }, + { 0x3d402124, 0x20208 }, + { 0x3d40212c, 0x1205010e }, + { 0x3d402130, 0x8 }, + { 0x3d40213c, 0x0 }, + { 0x3d402180, 0x1000040 }, + { 0x3d402190, 0x3848204 }, + { 0x3d402194, 0x2020303 }, + { 0x3d4021b4, 0x404 }, + { 0x3d4021b8, 0x4 }, + { 0x3d402240, 0x6000600 }, + { 0x3d4020f4, 0xec7 }, }; /* PHY Initialize Configuration */ struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x0001005f, 0x000002fd}, - {0x0001015f, 0x000002fd}, - {0x0001105f, 0x000002fd}, - {0x0001115f, 0x000002fd}, - {0x0011005f, 0x000002fd}, - {0x0011015f, 0x000002fd}, - {0x0011105f, 0x000002fd}, - {0x0011115f, 0x000002fd}, - {0x0021005f, 0x000002fd}, - {0x0021015f, 0x000002fd}, - {0x0021105f, 0x000002fd}, - {0x0021115f, 0x000002fd}, - {0x00000055, 0x00000355}, - {0x00001055, 0x00000355}, - {0x00002055, 0x00000355}, - {0x00003055, 0x00000355}, - {0x00004055, 0x00000055}, - {0x00005055, 0x00000055}, - {0x00006055, 0x00000355}, - {0x00007055, 0x00000355}, - {0x00008055, 0x00000355}, - {0x00009055, 0x00000355}, - {0x000200c5, 0x0000000a}, - {0x001200c5, 0x00000007}, - {0x002200c5, 0x00000007}, - {0x0002002e, 0x00000002}, - {0x0012002e, 0x00000002}, - {0x0022002e, 0x00000002}, - {0x00020024, 0x00000008}, - {0x0002003a, 0x00000002}, - {0x0002007d, 0x00000212}, - {0x0002007c, 0x00000061}, - {0x00120024, 0x00000008}, - {0x0002003a, 0x00000002}, - {0x0012007d, 0x00000212}, - {0x0012007c, 0x00000061}, - {0x00220024, 0x00000008}, - {0x0002003a, 0x00000002}, - {0x0022007d, 0x00000212}, - {0x0022007c, 0x00000061}, - {0x00020056, 0x00000006}, - {0x00120056, 0x0000000a}, - {0x00220056, 0x0000000a}, - {0x0001004d, 0x0000001a}, - {0x0001014d, 0x0000001a}, - {0x0001104d, 0x0000001a}, - {0x0001114d, 0x0000001a}, - {0x0011004d, 0x0000001a}, - {0x0011014d, 0x0000001a}, - {0x0011104d, 0x0000001a}, - {0x0011114d, 0x0000001a}, - {0x0021004d, 0x0000001a}, - {0x0021014d, 0x0000001a}, - {0x0021104d, 0x0000001a}, - {0x0021114d, 0x0000001a}, - {0x00010049, 0x00000e38}, - {0x00010149, 0x00000e38}, - {0x00011049, 0x00000e38}, - {0x00011149, 0x00000e38}, - {0x00110049, 0x00000e38}, - {0x00110149, 0x00000e38}, - {0x00111049, 0x00000e38}, - {0x00111149, 0x00000e38}, - {0x00210049, 0x00000e38}, - {0x00210149, 0x00000e38}, - {0x00211049, 0x00000e38}, - {0x00211149, 0x00000e38}, - {0x00000043, 0x00000063}, - {0x00001043, 0x00000063}, - {0x00002043, 0x00000063}, - {0x00003043, 0x00000063}, - {0x00004043, 0x00000063}, - {0x00005043, 0x00000063}, - {0x00006043, 0x00000063}, - {0x00007043, 0x00000063}, - {0x00008043, 0x00000063}, - {0x00009043, 0x00000063}, - {0x00020018, 0x00000001}, - {0x00020075, 0x00000002}, - {0x00020050, 0x00000000}, - {0x00020008, 0x00000258}, - {0x00120008, 0x00000064}, - {0x00220008, 0x00000019}, - {0x00020088, 0x00000009}, - {0x000200b2, 0x00000268}, - {0x00010043, 0x000005b1}, - {0x00010143, 0x000005b1}, - {0x00011043, 0x000005b1}, - {0x00011143, 0x000005b1}, - {0x001200b2, 0x00000268}, - {0x00110043, 0x000005b1}, - {0x00110143, 0x000005b1}, - {0x00111043, 0x000005b1}, - {0x00111143, 0x000005b1}, - {0x002200b2, 0x00000268}, - {0x00210043, 0x000005b1}, - {0x00210143, 0x000005b1}, - {0x00211043, 0x000005b1}, - {0x00211143, 0x000005b1}, - {0x0002005b, 0x00007529}, - {0x0002005c, 0x00000000}, - {0x000200fa, 0x00000001}, - {0x001200fa, 0x00000001}, - {0x002200fa, 0x00000001}, - {0x00020019, 0x00000005}, - {0x00120019, 0x00000005}, - {0x00220019, 0x00000005}, - {0x000200f0, 0x00005665}, - {0x000200f1, 0x00005555}, - {0x000200f2, 0x00005555}, - {0x000200f3, 0x00005555}, - {0x000200f4, 0x00005555}, - {0x000200f5, 0x00005555}, - {0x000200f6, 0x00005555}, - {0x000200f7, 0x0000f000}, - {0x0001004a, 0x00000500}, - {0x0001104a, 0x00000500}, - {0x00020025, 0x00000000}, - {0x0002002d, 0x00000000}, - {0x0012002d, 0x00000000}, - {0x0022002d, 0x00000000}, - {0x0002002c, 0x00000000}, - {0x000200c7, 0x00000021}, - {0x000200ca, 0x00000024}, - {0x000200cc, 0x000001f7}, - {0x001200c7, 0x00000021}, - {0x001200ca, 0x00000024}, - {0x001200cc, 0x000001f7}, - {0x002200c7, 0x00000021}, - {0x002200ca, 0x00000024}, - {0x002200cc, 0x000001f7}, + { 0x1005f, 0x2fd }, + { 0x1015f, 0x2fd }, + { 0x1105f, 0x2fd }, + { 0x1115f, 0x2fd }, + { 0x11005f, 0x2fd }, + { 0x11015f, 0x2fd }, + { 0x11105f, 0x2fd }, + { 0x11115f, 0x2fd }, + { 0x55, 0x355 }, + { 0x1055, 0x355 }, + { 0x2055, 0x355 }, + { 0x3055, 0x355 }, + { 0x4055, 0x55 }, + { 0x5055, 0x55 }, + { 0x6055, 0x355 }, + { 0x7055, 0x355 }, + { 0x8055, 0x355 }, + { 0x9055, 0x355 }, + { 0x200c5, 0xa }, + { 0x1200c5, 0x6 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x6 }, + { 0x120056, 0xa }, + { 0x1004d, 0x1a }, + { 0x1014d, 0x1a }, + { 0x1104d, 0x1a }, + { 0x1114d, 0x1a }, + { 0x11004d, 0x1a }, + { 0x11014d, 0x1a }, + { 0x11104d, 0x1a }, + { 0x11114d, 0x1a }, + { 0x10049, 0xe38 }, + { 0x10149, 0xe38 }, + { 0x11049, 0xe38 }, + { 0x11149, 0xe38 }, + { 0x110049, 0xe38 }, + { 0x110149, 0xe38 }, + { 0x111049, 0xe38 }, + { 0x111149, 0xe38 }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x2 }, + { 0x20050, 0x0 }, + { 0x20008, 0x258 }, + { 0x120008, 0x10a }, + { 0x20088, 0x9 }, + { 0x200b2, 0x268 }, + { 0x10043, 0x5b1 }, + { 0x10143, 0x5b1 }, + { 0x11043, 0x5b1 }, + { 0x11143, 0x5b1 }, + { 0x1200b2, 0x268 }, + { 0x110043, 0x5b1 }, + { 0x110143, 0x5b1 }, + { 0x111043, 0x5b1 }, + { 0x111143, 0x5b1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x2005b, 0x7529 }, + { 0x2005c, 0x0 }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x200cc, 0x1f7 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x1200cc, 0x1f7 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, }; /* ddr phy trained csr */ @@ -792,378 +739,279 @@ struct dram_cfg_param ddr_ddrphy_trained_csr[] = { /* P0 message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_cfg[] = { - {0x000d0000, 0x00000000}, - {0x00020060, 0x00000002}, - {0x00054000, 0x00000000}, - {0x00054001, 0x00000000}, - {0x00054002, 0x00000000}, - {0x00054003, 0x00000960}, - {0x00054004, 0x00000002}, - {0x00054005, 0x00000000}, - {0x00054006, 0x0000025e}, - {0x00054007, 0x00001000}, - {0x00054008, 0x00000101}, - {0x00054009, 0x00000000}, - {0x0005400a, 0x00000000}, - {0x0005400b, 0x0000031f}, - {0x0005400c, 0x000000c8}, - {0x0005400d, 0x00000100}, - {0x0005400e, 0x00000000}, - {0x0005400f, 0x00000000}, - {0x00054010, 0x00000000}, - {0x00054011, 0x00000000}, - {0x00054012, 0x00000001}, - {0x0005402f, 0x00000834}, - {0x00054030, 0x00000105}, - {0x00054031, 0x00000018}, - {0x00054032, 0x00000200}, - {0x00054033, 0x00000200}, - {0x00054034, 0x00000740}, - {0x00054035, 0x00000850}, - {0x00054036, 0x00000103}, - {0x00054037, 0x00000000}, - {0x00054038, 0x00000000}, - {0x00054039, 0x00000000}, - {0x0005403a, 0x00000000}, - {0x0005403b, 0x00000000}, - {0x0005403c, 0x00000000}, - {0x0005403d, 0x00000000}, - {0x0005403e, 0x00000000}, - {0x0005403f, 0x00001221}, - {0x000541fc, 0x00000100}, - {0x000d0000, 0x00000001}, + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x810 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, }; /* P1 message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp1_cfg[] = { - {0x000d0000, 0x00000000}, - {0x00054000, 0x00000000}, - {0x00054001, 0x00000000}, - {0x00054002, 0x00000101}, - {0x00054003, 0x00000190}, - {0x00054004, 0x00000002}, - {0x00054005, 0x00000000}, - {0x00054006, 0x0000025e}, - {0x00054007, 0x00001000}, - {0x00054008, 0x00000101}, - {0x00054009, 0x00000000}, - {0x0005400a, 0x00000000}, - {0x0005400b, 0x0000021f}, - {0x0005400c, 0x000000c8}, - {0x0005400d, 0x00000100}, - {0x0005400e, 0x00000000}, - {0x0005400f, 0x00000000}, - {0x00054010, 0x00000000}, - {0x00054011, 0x00000000}, - {0x00054012, 0x00000001}, - {0x0005402f, 0x00000000}, - {0x00054030, 0x00000105}, - {0x00054031, 0x00000000}, - {0x00054032, 0x00000000}, - {0x00054033, 0x00000200}, - {0x00054034, 0x00000740}, - {0x00054035, 0x00000050}, - {0x00054036, 0x00000103}, - {0x00054037, 0x00000000}, - {0x00054038, 0x00000000}, - {0x00054039, 0x00000000}, - {0x0005403a, 0x00000000}, - {0x0005403b, 0x00000000}, - {0x0005403c, 0x00000000}, - {0x0005403d, 0x00000000}, - {0x0005403e, 0x00000000}, - {0x0005403f, 0x00001221}, - {0x000541fc, 0x00000100}, - {0x000d0000, 0x00000001}, + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x42a }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x10 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, }; -/* P2 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp2_cfg[] = { - {0x000d0000, 0x00000000}, - {0x00054000, 0x00000000}, - {0x00054001, 0x00000000}, - {0x00054002, 0x00000102}, - {0x00054003, 0x00000064}, - {0x00054004, 0x00000002}, - {0x00054005, 0x00000000}, - {0x00054006, 0x0000025e}, - {0x00054007, 0x00001000}, - {0x00054008, 0x00000101}, - {0x00054009, 0x00000000}, - {0x0005400a, 0x00000000}, - {0x0005400b, 0x0000021f}, - {0x0005400c, 0x000000c8}, - {0x0005400d, 0x00000100}, - {0x0005400e, 0x00000000}, - {0x0005400f, 0x00000000}, - {0x00054010, 0x00000000}, - {0x00054011, 0x00000000}, - {0x00054012, 0x00000001}, - {0x0005402f, 0x00000000}, - {0x00054030, 0x00000105}, - {0x00054031, 0x00000000}, - {0x00054032, 0x00000000}, - {0x00054033, 0x00000200}, - {0x00054034, 0x00000740}, - {0x00054035, 0x00000050}, - {0x00054036, 0x00000103}, - {0x00054037, 0x00000000}, - {0x00054038, 0x00000000}, - {0x00054039, 0x00000000}, - {0x0005403a, 0x00000000}, - {0x0005403b, 0x00000000}, - {0x0005403c, 0x00000000}, - {0x0005403d, 0x00000000}, - {0x0005403e, 0x00000000}, - {0x0005403f, 0x00001221}, - {0x000541fc, 0x00000100}, - {0x000d0000, 0x00000001}, -}; /* P0 2D message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0x000d0000, 0x00000000}, - {0x00054000, 0x00000000}, - {0x00054001, 0x00000000}, - {0x00054002, 0x00000000}, - {0x00054003, 0x00000960}, - {0x00054004, 0x00000002}, - {0x00054005, 0x00000000}, - {0x00054006, 0x0000025e}, - {0x00054007, 0x00001000}, - {0x00054008, 0x00000101}, - {0x00054009, 0x00000000}, - {0x0005400a, 0x00000000}, - {0x0005400b, 0x00000061}, - {0x0005400c, 0x000000c8}, - {0x0005400d, 0x00000100}, - {0x0005400e, 0x00001f7f}, - {0x0005400f, 0x00000000}, - {0x00054010, 0x00000000}, - {0x00054011, 0x00000000}, - {0x00054012, 0x00000001}, - {0x0005402f, 0x00000834}, - {0x00054030, 0x00000105}, - {0x00054031, 0x00000018}, - {0x00054032, 0x00000200}, - {0x00054033, 0x00000200}, - {0x00054034, 0x00000740}, - {0x00054035, 0x00000850}, - {0x00054036, 0x00000103}, - {0x00054037, 0x00000000}, - {0x00054038, 0x00000000}, - {0x00054039, 0x00000000}, - {0x0005403a, 0x00000000}, - {0x0005403b, 0x00000000}, - {0x0005403c, 0x00000000}, - {0x0005403d, 0x00000000}, - {0x0005403e, 0x00000000}, - {0x0005403f, 0x00001221}, - {0x000541fc, 0x00000100}, - {0x000d0000, 0x00000001}, + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x5400e, 0x1f7f }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x810 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, }; /* DRAM PHY init engine image */ struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x2}, - {0x90033, 0x10}, - {0x90034, 0x139}, - {0x90035, 0xb}, - {0x90036, 0x7c0}, - {0x90037, 0x139}, - {0x90038, 0x44}, - {0x90039, 0x633}, - {0x9003a, 0x159}, - {0x9003b, 0x14f}, - {0x9003c, 0x630}, - {0x9003d, 0x159}, - {0x9003e, 0x47}, - {0x9003f, 0x633}, - {0x90040, 0x149}, - {0x90041, 0x4f}, - {0x90042, 0x633}, - {0x90043, 0x179}, - {0x90044, 0x8}, - {0x90045, 0xe0}, - {0x90046, 0x109}, - {0x90047, 0x0}, - {0x90048, 0x7c8}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x1}, - {0x9004c, 0x8}, - {0x9004d, 0x0}, - {0x9004e, 0x45a}, - {0x9004f, 0x9}, - {0x90050, 0x0}, - {0x90051, 0x448}, - {0x90052, 0x109}, - {0x90053, 0x40}, - {0x90054, 0x633}, - {0x90055, 0x179}, - {0x90056, 0x1}, - {0x90057, 0x618}, - {0x90058, 0x109}, - {0x90059, 0x40c0}, - {0x9005a, 0x633}, - {0x9005b, 0x149}, - {0x9005c, 0x8}, - {0x9005d, 0x4}, - {0x9005e, 0x48}, - {0x9005f, 0x4040}, - {0x90060, 0x633}, - {0x90061, 0x149}, - {0x90062, 0x0}, - {0x90063, 0x4}, - {0x90064, 0x48}, - {0x90065, 0x40}, - {0x90066, 0x633}, - {0x90067, 0x149}, - {0x90068, 0x10}, - {0x90069, 0x4}, - {0x9006a, 0x18}, - {0x9006b, 0x0}, - {0x9006c, 0x4}, - {0x9006d, 0x78}, - {0x9006e, 0x549}, - {0x9006f, 0x633}, - {0x90070, 0x159}, - {0x90071, 0xd49}, - {0x90072, 0x633}, - {0x90073, 0x159}, - {0x90074, 0x94a}, - {0x90075, 0x633}, - {0x90076, 0x159}, - {0x90077, 0x441}, - {0x90078, 0x633}, - {0x90079, 0x149}, - {0x9007a, 0x42}, - {0x9007b, 0x633}, - {0x9007c, 0x149}, - {0x9007d, 0x1}, - {0x9007e, 0x633}, - {0x9007f, 0x149}, - {0x90080, 0x0}, - {0x90081, 0xe0}, - {0x90082, 0x109}, - {0x90083, 0xa}, - {0x90084, 0x10}, - {0x90085, 0x109}, - {0x90086, 0x9}, - {0x90087, 0x3c0}, - {0x90088, 0x149}, - {0x90089, 0x9}, - {0x9008a, 0x3c0}, - {0x9008b, 0x159}, - {0x9008c, 0x18}, - {0x9008d, 0x10}, - {0x9008e, 0x109}, - {0x9008f, 0x0}, - {0x90090, 0x3c0}, - {0x90091, 0x109}, - {0x90092, 0x18}, - {0x90093, 0x4}, - {0x90094, 0x48}, - {0x90095, 0x18}, - {0x90096, 0x4}, - {0x90097, 0x58}, - {0x90098, 0xb}, - {0x90099, 0x10}, - {0x9009a, 0x109}, - {0x9009b, 0x1}, - {0x9009c, 0x10}, - {0x9009d, 0x109}, - {0x9009e, 0x5}, - {0x9009f, 0x7c0}, - {0x900a0, 0x109}, - {0x900a1, 0x0}, - {0x900a2, 0x8140}, - {0x900a3, 0x10c}, - {0x900a4, 0x10}, - {0x900a5, 0x8138}, - {0x900a6, 0x10c}, - {0x900a7, 0x8}, - {0x900a8, 0x7c8}, - {0x900a9, 0x101}, - {0x900aa, 0x8}, - {0x900ab, 0x448}, - {0x900ac, 0x109}, - {0x900ad, 0xf}, - {0x900ae, 0x7c0}, - {0x900af, 0x109}, - {0x900b0, 0x47}, - {0x900b1, 0x630}, - {0x900b2, 0x109}, - {0x900b3, 0x8}, - {0x900b4, 0x618}, - {0x900b5, 0x109}, - {0x900b6, 0x8}, - {0x900b7, 0xe0}, - {0x900b8, 0x109}, - {0x900b9, 0x0}, - {0x900ba, 0x7c8}, - {0x900bb, 0x109}, - {0x900bc, 0x8}, - {0x900bd, 0x8140}, - {0x900be, 0x10c}, - {0x900bf, 0x0}, - {0x900c0, 0x1}, - {0x900c1, 0x8}, - {0x900c2, 0x8}, - {0x900c3, 0x4}, - {0x900c4, 0x8}, - {0x900c5, 0x8}, - {0x900c6, 0x7c8}, - {0x900c7, 0x101}, - {0x90006, 0x0}, - {0x90007, 0x0}, - {0x90008, 0x8}, - {0x90009, 0x0}, - {0x9000a, 0x0}, - {0x9000b, 0x0}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x90026, 0x2b}, - {0x2000b, 0x4b}, - {0x2000c, 0x96}, - {0x2000d, 0x5dc}, - {0x2000e, 0x2c}, - {0x12000b, 0xc}, - {0x12000c, 0x16}, - {0x12000d, 0xfa}, - {0x12000e, 0x10}, - {0x22000b, 0x3}, - {0x22000c, 0x3}, - {0x22000d, 0x3e}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0xffff}, - {0x90013, 0x6152}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x0}, - {0xd0000, 0x1}, + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xb }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x633 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x633 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x633 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x633 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x633 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x633 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xb }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x1 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x5 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x0 }, + { 0x900a2, 0x8140 }, + { 0x900a3, 0x10c }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x8138 }, + { 0x900a6, 0x10c }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7c8 }, + { 0x900a9, 0x101 }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x448 }, + { 0x900ac, 0x109 }, + { 0x900ad, 0xf }, + { 0x900ae, 0x7c0 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x47 }, + { 0x900b1, 0x630 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x8 }, + { 0x900b4, 0x618 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0xe0 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x0 }, + { 0x900ba, 0x7c8 }, + { 0x900bb, 0x109 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x8140 }, + { 0x900be, 0x10c }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x1 }, + { 0x900c1, 0x8 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x8 }, + { 0x900c5, 0x8 }, + { 0x900c6, 0x7c8 }, + { 0x900c7, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2b }, + { 0x2000b, 0x4b }, + { 0x2000c, 0x96 }, + { 0x2000d, 0x5dc }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x21 }, + { 0x12000c, 0x42 }, + { 0x12000d, 0x29a }, + { 0x12000e, 0x21 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } }; struct dram_fsp_msg ddr_dram_fsp_msg[] = { @@ -1175,19 +1023,12 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), }, { - /* P1 400mts 1D */ - .drate = 400, + /* P1 1066mts 1D */ + .drate = 1066, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp1_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), }, - { - /* P2 100mts 1D */ - .drate = 100, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, { /* P0 2400mts 2D */ .drate = 2400, @@ -1209,6 +1050,6 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 2400, 400, 100,}, + .fsp_table = { 2400, 1066, }, }; From 4eeb9fe84742af67c775afd5055b672b0639a244 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Mar 2021 15:57:06 +0800 Subject: [PATCH 014/117] power: pca9450: add a new parameter for power_pca9450_init Currently PCA9450 might have address 0x25 or 0x35, so let user choose the address. Signed-off-by: Peng Fan Reviewed-by: Jaehoon Chung --- board/freescale/imx8mp_evk/spl.c | 2 +- board/phytec/phycore_imx8mp/spl.c | 2 +- drivers/power/pmic/pmic_pca9450.c | 4 ++-- include/power/pca9450.h | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index 6ccf5ac8fa..a7564e9b1a 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -70,7 +70,7 @@ int power_init_board(void) struct pmic *p; int ret; - ret = power_pca9450_init(I2C_PMIC); + ret = power_pca9450_init(I2C_PMIC, 0x25); if (ret) printf("power init failed"); p = pmic_get("PCA9450"); diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index eefdd7fdda..f9fa8d1e12 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -53,7 +53,7 @@ int power_init_board(void) struct pmic *p; int ret; - ret = power_pca9450_init(0); + ret = power_pca9450_init(0, 0x25); if (ret) printf("power init failed"); p = pmic_get("PCA9450"); diff --git a/drivers/power/pmic/pmic_pca9450.c b/drivers/power/pmic/pmic_pca9450.c index d4f27428bd..8c4d0a9230 100644 --- a/drivers/power/pmic/pmic_pca9450.c +++ b/drivers/power/pmic/pmic_pca9450.c @@ -11,7 +11,7 @@ static const char pca9450_name[] = "PCA9450"; -int power_pca9450_init(unsigned char bus) +int power_pca9450_init(unsigned char bus, unsigned char addr) { struct pmic *p = pmic_alloc(); @@ -23,7 +23,7 @@ int power_pca9450_init(unsigned char bus) p->name = pca9450_name; p->interface = PMIC_I2C; p->number_of_regs = PCA9450_REG_NUM; - p->hw.i2c.addr = 0x25; + p->hw.i2c.addr = addr; p->hw.i2c.tx_num = 1; p->bus = bus; diff --git a/include/power/pca9450.h b/include/power/pca9450.h index 5a9a697d62..27703bb1f9 100644 --- a/include/power/pca9450.h +++ b/include/power/pca9450.h @@ -54,6 +54,6 @@ enum { PCA9450_REG_NUM, }; -int power_pca9450_init(unsigned char bus); +int power_pca9450_init(unsigned char bus, unsigned char addr); #endif From e3422b0d597621b9be51fe2503a93da1710fe385 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Mar 2021 15:57:07 +0800 Subject: [PATCH 015/117] imx8mn_evk: drop duplicated code uart clk has been enabled, no need enable again. Signed-off-by: Peng Fan --- board/freescale/imx8mn_evk/spl.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c index 6d5c7a5b46..80f79ce888 100644 --- a/board/freescale/imx8mn_evk/spl.c +++ b/board/freescale/imx8mn_evk/spl.c @@ -84,8 +84,6 @@ int board_early_init_f(void) imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - init_uart_clk(1); - return 0; } From 4e805c197be408954c50e5d1c7a492d1cf2c7c20 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Mar 2021 15:57:08 +0800 Subject: [PATCH 016/117] imx8mn: Add LPDDR4 EVK board support Add support for iMX8MN LPDDR4 EVK board which uses 2GB LPDDR4 and PCA9450B PMIC. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 3 + arch/arm/dts/imx8mn-evk-u-boot.dtsi | 26 + arch/arm/dts/imx8mn-evk.dts | 128 ++ arch/arm/mach-imx/imx8m/Kconfig | 6 + board/freescale/imx8mn_evk/Kconfig | 2 +- board/freescale/imx8mn_evk/Makefile | 1 + board/freescale/imx8mn_evk/lpddr4_timing.c | 1587 ++++++++++++++++++++ board/freescale/imx8mn_evk/spl.c | 43 + configs/imx8mn_evk_defconfig | 93 ++ 10 files changed, 1889 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx8mn-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-evk.dts create mode 100644 board/freescale/imx8mn_evk/lpddr4_timing.c create mode 100644 configs/imx8mn_evk_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cedddd370f..a5e836e877 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -799,6 +799,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-verdin.dtb \ phycore-imx8mm.dtb \ imx8mn-ddr4-evk.dtb \ + imx8mn-evk.dtb \ imx8mq-evk.dtb \ imx8mm-beacon-kit.dtb \ imx8mn-beacon-kit.dtb \ diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 025090fff4..8cd15be7a8 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -19,6 +19,9 @@ &clk { u-boot,dm-spl; u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; }; &osc_24m { diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-evk-u-boot.dtsi new file mode 100644 index 0000000000..2730ff6a81 --- /dev/null +++ b/arch/arm/dts/imx8mn-evk-u-boot.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8mn-ddr4-evk-u-boot.dtsi" + +&i2c1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mn-evk.dts b/arch/arm/dts/imx8mn-evk.dts new file mode 100644 index 0000000000..cd11fb28f5 --- /dev/null +++ b/arch/arm/dts/imx8mn-evk.dts @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mn.dtsi" +#include "imx8mn-evk.dtsi" +#include + +/ { + model = "NXP i.MX8MNano EVK board"; + compatible = "fsl,imx8mn-evk", "fsl,imx8mn"; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&i2c1 { + pmic: pca9450@25 { + compatible = "nxp,pca9450b"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1{ + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 12b8d0d831..59a45f7b01 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -49,6 +49,12 @@ config TARGET_IMX8MM_VENICE select SUPPORT_SPL select IMX8M_LPDDR4 +config TARGET_IMX8MN_EVK + bool "imx8mn LPDDR4 EVK board" + select IMX8MN + select SUPPORT_SPL + select IMX8M_LPDDR4 + config TARGET_IMX8MN_DDR4_EVK bool "imx8mn DDR4 EVK board" select IMX8MN diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig index 048fb7d97f..ace6fc1e39 100644 --- a/board/freescale/imx8mn_evk/Kconfig +++ b/board/freescale/imx8mn_evk/Kconfig @@ -1,4 +1,4 @@ -if TARGET_IMX8MN_DDR4_EVK +if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK config SYS_BOARD default "imx8mn_evk" diff --git a/board/freescale/imx8mn_evk/Makefile b/board/freescale/imx8mn_evk/Makefile index 9511a70c31..5d7dbe6628 100644 --- a/board/freescale/imx8mn_evk/Makefile +++ b/board/freescale/imx8mn_evk/Makefile @@ -8,5 +8,6 @@ obj-y += imx8mn_evk.o ifdef CONFIG_SPL_BUILD obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o endif diff --git a/board/freescale/imx8mn_evk/lpddr4_timing.c b/board/freescale/imx8mn_evk/lpddr4_timing.c new file mode 100644 index 0000000000..671e924132 --- /dev/null +++ b/board/freescale/imx8mn_evk/lpddr4_timing.c @@ -0,0 +1,1587 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x3d400020, 0x00000213}, + {0x3d400024, 0x0003e800}, + {0x3d400030, 0x00000120}, + {0x3d400000, 0xa3080020}, + {0x3d400064, 0x006100e0}, + {0x3d4000d0, 0xc003061c}, + {0x3d4000d4, 0x009e0000}, + {0x3d4000dc, 0x00d4002d}, + {0x3d4000e0, 0x00310000}, + {0x3d4000e8, 0x0066004d}, + {0x3d4000ec, 0x0016004a}, + {0x3d400100, 0x1a201b22}, + {0x3d400104, 0x00060633}, + {0x3d40010c, 0x00c0c000}, + {0x3d400110, 0x0f04080f}, + {0x3d400114, 0x02040c0c}, + {0x3d400118, 0x01010007}, + {0x3d40011c, 0x00000401}, + {0x3d400130, 0x00020600}, + {0x3d400134, 0x0c100002}, + {0x3d400138, 0x000000e6}, + {0x3d400144, 0x00a00050}, + {0x3d400180, 0x03200018}, + {0x3d400184, 0x028061a8}, + {0x3d400188, 0x00000000}, + {0x3d400190, 0x0497820a}, + {0x3d4001b4, 0x0000170a}, + {0x3d400108, 0x070e1617}, + {0x3d4001c0, 0x00000001}, + {0x3d400194, 0x00080303}, + {0x3d4001a0, 0xe0400018}, + {0x3d4001a4, 0x00df00e4}, + {0x3d4001a8, 0x80000000}, + {0x3d4001b0, 0x00000011}, + {0x3d4001c4, 0x00000001}, + {0x3d4000f4, 0x00000c99}, + {0x3d400200, 0x00000017}, + {0x3d400204, 0x00080808}, + {0x3d400208, 0x00000000}, + {0x3d40020c, 0x00000000}, + {0x3d400210, 0x00001f1f}, + {0x3d400214, 0x07070707}, + {0x3d400218, 0x07070707}, + {0x3d40021c, 0x00000f0f}, + {0x3d400250, 0x29001701}, + {0x3d400254, 0x0000002c}, + {0x3d40025c, 0x04000030}, + {0x3d400264, 0x900093e7}, + {0x3d40026c, 0x20005574}, + {0x3d400400, 0x00000111}, + {0x3d400408, 0x000072ff}, + {0x3d400494, 0x02100e07}, + {0x3d400498, 0x00620096}, + {0x3d40049c, 0x01100e07}, + {0x3d4004a0, 0x00c8012c}, + {0x3d402020, 0x00000011}, + {0x3d402024, 0x00007d00}, + {0x3d402050, 0x0020d040}, + {0x3d402064, 0x000c001d}, + {0x3d4020f4, 0x00000c99}, + {0x3d402100, 0x0a040305}, + {0x3d402104, 0x00030407}, + {0x3d402108, 0x0203060b}, + {0x3d40210c, 0x00505000}, + {0x3d402110, 0x02040202}, + {0x3d402114, 0x02030202}, + {0x3d402118, 0x01010004}, + {0x3d40211c, 0x00000301}, + {0x3d402130, 0x00020300}, + {0x3d402134, 0x0a100002}, + {0x3d402138, 0x0000001d}, + {0x3d402144, 0x0014000a}, + {0x3d402180, 0x00650004}, + {0x3d402190, 0x03818200}, + {0x3d402194, 0x00080303}, + {0x3d4021b4, 0x00000100}, + {0x3d4020dc, 0x00840000}, + {0x3d4020e0, 0x00310000}, + {0x3d4020e8, 0x0066004d}, + {0x3d4020ec, 0x0016004a}, + {0x3d403020, 0x00000011}, + {0x3d403024, 0x00001f40}, + {0x3d403050, 0x0020d040}, + {0x3d403064, 0x00030007}, + {0x3d4030f4, 0x00000c99}, + {0x3d403100, 0x0a010102}, + {0x3d403104, 0x00030404}, + {0x3d403108, 0x0203060b}, + {0x3d40310c, 0x00505000}, + {0x3d403110, 0x02040202}, + {0x3d403114, 0x02030202}, + {0x3d403118, 0x01010004}, + {0x3d40311c, 0x00000301}, + {0x3d403130, 0x00020300}, + {0x3d403134, 0x0a100002}, + {0x3d403138, 0x00000008}, + {0x3d403144, 0x00050003}, + {0x3d403180, 0x00190004}, + {0x3d403190, 0x03818200}, + {0x3d403194, 0x00080303}, + {0x3d4031b4, 0x00000100}, + {0x3d4030dc, 0x00840000}, + {0x3d4030e0, 0x00310000}, + {0x3d4030e8, 0x0066004d}, + {0x3d4030ec, 0x0016004a}, + + /* default boot point */ + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x000d0000, 0x00000000}, + {0x000100a0, 0x00000000}, + {0x000100a1, 0x00000001}, + {0x000100a2, 0x00000002}, + {0x000100a3, 0x00000003}, + {0x000100a4, 0x00000004}, + {0x000100a5, 0x00000005}, + {0x000100a6, 0x00000006}, + {0x000100a7, 0x00000007}, + {0x000110a0, 0x00000000}, + {0x000110a1, 0x00000001}, + {0x000110a2, 0x00000003}, + {0x000110a3, 0x00000004}, + {0x000110a4, 0x00000005}, + {0x000110a5, 0x00000002}, + {0x000110a6, 0x00000007}, + {0x000110a7, 0x00000006}, + {0x0001005f, 0x0000015f}, + {0x0001015f, 0x0000015f}, + {0x0001105f, 0x0000015f}, + {0x0001115f, 0x0000015f}, + {0x0011005f, 0x0000015f}, + {0x0011015f, 0x0000015f}, + {0x0011105f, 0x0000015f}, + {0x0011115f, 0x0000015f}, + {0x0021005f, 0x0000015f}, + {0x0021015f, 0x0000015f}, + {0x0021105f, 0x0000015f}, + {0x0021115f, 0x0000015f}, + {0x00000055, 0x0000016f}, + {0x00001055, 0x0000016f}, + {0x00002055, 0x0000016f}, + {0x00003055, 0x0000016f}, + {0x00004055, 0x0000016f}, + {0x00005055, 0x0000016f}, + {0x00006055, 0x0000016f}, + {0x00007055, 0x0000016f}, + {0x00008055, 0x0000016f}, + {0x00009055, 0x0000016f}, + {0x000200c5, 0x00000019}, + {0x001200c5, 0x00000007}, + {0x002200c5, 0x00000007}, + {0x0002002e, 0x00000002}, + {0x0012002e, 0x00000002}, + {0x0022002e, 0x00000002}, + {0x00090204, 0x00000000}, + {0x00190204, 0x00000000}, + {0x00290204, 0x00000000}, + {0x00020024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0002007d, 0x00000212}, + {0x0002007c, 0x00000061}, + {0x00120024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0012007d, 0x00000212}, + {0x0012007c, 0x00000061}, + {0x00220024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0022007d, 0x00000212}, + {0x0022007c, 0x00000061}, + {0x00020056, 0x00000003}, + {0x00120056, 0x00000003}, + {0x00220056, 0x00000003}, + {0x0001004d, 0x00000f80}, + {0x0001014d, 0x00000f80}, + {0x0001104d, 0x00000f80}, + {0x0001114d, 0x00000f80}, + {0x0011004d, 0x00000f80}, + {0x0011014d, 0x00000f80}, + {0x0011104d, 0x00000f80}, + {0x0011114d, 0x00000f80}, + {0x0021004d, 0x00000f80}, + {0x0021014d, 0x00000f80}, + {0x0021104d, 0x00000f80}, + {0x0021114d, 0x00000f80}, + {0x00010049, 0x00000fbe}, + {0x00010149, 0x00000fbe}, + {0x00011049, 0x00000fbe}, + {0x00011149, 0x00000fbe}, + {0x00110049, 0x00000fbe}, + {0x00110149, 0x00000fbe}, + {0x00111049, 0x00000fbe}, + {0x00111149, 0x00000fbe}, + {0x00210049, 0x00000fbe}, + {0x00210149, 0x00000fbe}, + {0x00211049, 0x00000fbe}, + {0x00211149, 0x00000fbe}, + {0x00000043, 0x00000063}, + {0x00001043, 0x00000063}, + {0x00002043, 0x00000063}, + {0x00003043, 0x00000063}, + {0x00004043, 0x00000063}, + {0x00005043, 0x00000063}, + {0x00006043, 0x00000063}, + {0x00007043, 0x00000063}, + {0x00008043, 0x00000063}, + {0x00009043, 0x00000063}, + {0x00020018, 0x00000001}, + {0x00020075, 0x00000004}, + {0x00020050, 0x00000000}, + {0x00020008, 0x00000320}, + {0x00120008, 0x00000064}, + {0x00220008, 0x00000019}, + {0x00020088, 0x00000009}, + {0x000200b2, 0x000000dc}, + {0x00010043, 0x000005a1}, + {0x00010143, 0x000005a1}, + {0x00011043, 0x000005a1}, + {0x00011143, 0x000005a1}, + {0x001200b2, 0x000000dc}, + {0x00110043, 0x000005a1}, + {0x00110143, 0x000005a1}, + {0x00111043, 0x000005a1}, + {0x00111143, 0x000005a1}, + {0x002200b2, 0x000000dc}, + {0x00210043, 0x000005a1}, + {0x00210143, 0x000005a1}, + {0x00211043, 0x000005a1}, + {0x00211143, 0x000005a1}, + {0x000200fa, 0x00000001}, + {0x001200fa, 0x00000001}, + {0x002200fa, 0x00000001}, + {0x00020019, 0x00000001}, + {0x00120019, 0x00000001}, + {0x00220019, 0x00000001}, + {0x000200f0, 0x00000660}, + {0x000200f1, 0x00000000}, + {0x000200f2, 0x00004444}, + {0x000200f3, 0x00008888}, + {0x000200f4, 0x00005665}, + {0x000200f5, 0x00000000}, + {0x000200f6, 0x00000000}, + {0x000200f7, 0x0000f000}, + {0x0001004a, 0x00000500}, + {0x0001104a, 0x00000500}, + {0x00020025, 0x00000000}, + {0x0002002d, 0x00000000}, + {0x0012002d, 0x00000000}, + {0x0022002d, 0x00000000}, + {0x0002002c, 0x00000000}, + {0x000200c7, 0x00000021}, + {0x000200ca, 0x00000024}, + {0x000200cc, 0x000001f7}, + {0x001200c7, 0x00000021}, + {0x001200ca, 0x00000024}, + {0x001200cc, 0x000001f7}, + {0x002200c7, 0x00000021}, + {0x002200ca, 0x00000024}, + {0x002200cc, 0x000001f7}, + {0x00020060, 0x00000002}, + {0x000d0000, 0x00000001}, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x0200cb, 0x0}, + {0x010043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x010143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x011043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x011143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x000080, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x001080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x002080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x003080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x004080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x005080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x006080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x007080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x008080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x009080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x010080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x010180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x011080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x011180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x010081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x010181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x011081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x011181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x0100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x0101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x0110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x0111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x0100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x0101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x0110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x0111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x010068, 0x0}, + {0x010168, 0x0}, + {0x010268, 0x0}, + {0x010368, 0x0}, + {0x010468, 0x0}, + {0x010568, 0x0}, + {0x010668, 0x0}, + {0x010768, 0x0}, + {0x010868, 0x0}, + {0x011068, 0x0}, + {0x011168, 0x0}, + {0x011268, 0x0}, + {0x011368, 0x0}, + {0x011468, 0x0}, + {0x011568, 0x0}, + {0x011668, 0x0}, + {0x011768, 0x0}, + {0x011868, 0x0}, + {0x010069, 0x0}, + {0x010169, 0x0}, + {0x010269, 0x0}, + {0x010369, 0x0}, + {0x010469, 0x0}, + {0x010569, 0x0}, + {0x010669, 0x0}, + {0x010769, 0x0}, + {0x010869, 0x0}, + {0x011069, 0x0}, + {0x011169, 0x0}, + {0x011269, 0x0}, + {0x011369, 0x0}, + {0x011469, 0x0}, + {0x011569, 0x0}, + {0x011669, 0x0}, + {0x011769, 0x0}, + {0x011869, 0x0}, + {0x01008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x01018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x01108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x01118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x01008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x01018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x01108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x01118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x0100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x0101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x0102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x0103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x0104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x0105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x0106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x0107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x0108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x0110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x0111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x0112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x0113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x0114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x0115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x0116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x0117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x0118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x0100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x0101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x0102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x0103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x0104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x0105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x0106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x0107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x0108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x0110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x0111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x0112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x0113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x0114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x0115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x0116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x0117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x0118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x010020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x011020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x020072, 0x0}, + {0x020073, 0x0}, + {0x020074, 0x0}, + {0x0100aa, 0x0}, + {0x0110aa, 0x0}, + {0x020010, 0x0}, + {0x120010, 0x0}, + {0x220010, 0x0}, + {0x020011, 0x0}, + {0x120011, 0x0}, + {0x220011, 0x0}, + {0x0100ae, 0x0}, + {0x1100ae, 0x0}, + {0x2100ae, 0x0}, + {0x0100af, 0x0}, + {0x1100af, 0x0}, + {0x2100af, 0x0}, + {0x0110ae, 0x0}, + {0x1110ae, 0x0}, + {0x2110ae, 0x0}, + {0x0110af, 0x0}, + {0x1110af, 0x0}, + {0x2110af, 0x0}, + {0x020020, 0x0}, + {0x120020, 0x0}, + {0x220020, 0x0}, + {0x0100a0, 0x0}, + {0x0100a1, 0x0}, + {0x0100a2, 0x0}, + {0x0100a3, 0x0}, + {0x0100a4, 0x0}, + {0x0100a5, 0x0}, + {0x0100a6, 0x0}, + {0x0100a7, 0x0}, + {0x0110a0, 0x0}, + {0x0110a1, 0x0}, + {0x0110a2, 0x0}, + {0x0110a3, 0x0}, + {0x0110a4, 0x0}, + {0x0110a5, 0x0}, + {0x0110a6, 0x0}, + {0x0110a7, 0x0}, + {0x02007c, 0x0}, + {0x12007c, 0x0}, + {0x22007c, 0x0}, + {0x02007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x0400fd, 0x0}, + {0x0400c0, 0x0}, + {0x090201, 0x0}, + {0x190201, 0x0}, + {0x290201, 0x0}, + {0x090202, 0x0}, + {0x190202, 0x0}, + {0x290202, 0x0}, + {0x090203, 0x0}, + {0x190203, 0x0}, + {0x290203, 0x0}, + {0x090204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x090205, 0x0}, + {0x190205, 0x0}, + {0x290205, 0x0}, + {0x090206, 0x0}, + {0x190206, 0x0}, + {0x290206, 0x0}, + {0x090207, 0x0}, + {0x190207, 0x0}, + {0x290207, 0x0}, + {0x090208, 0x0}, + {0x190208, 0x0}, + {0x290208, 0x0}, + {0x010062, 0x0}, + {0x010162, 0x0}, + {0x010262, 0x0}, + {0x010362, 0x0}, + {0x010462, 0x0}, + {0x010562, 0x0}, + {0x010662, 0x0}, + {0x010762, 0x0}, + {0x010862, 0x0}, + {0x011062, 0x0}, + {0x011162, 0x0}, + {0x011262, 0x0}, + {0x011362, 0x0}, + {0x011462, 0x0}, + {0x011562, 0x0}, + {0x011662, 0x0}, + {0x011762, 0x0}, + {0x011862, 0x0}, + {0x020077, 0x0}, + {0x010001, 0x0}, + {0x011001, 0x0}, + {0x010040, 0x0}, + {0x010140, 0x0}, + {0x010240, 0x0}, + {0x010340, 0x0}, + {0x010440, 0x0}, + {0x010540, 0x0}, + {0x010640, 0x0}, + {0x010740, 0x0}, + {0x010840, 0x0}, + {0x010030, 0x0}, + {0x010130, 0x0}, + {0x010230, 0x0}, + {0x010330, 0x0}, + {0x010430, 0x0}, + {0x010530, 0x0}, + {0x010630, 0x0}, + {0x010730, 0x0}, + {0x010830, 0x0}, + {0x011040, 0x0}, + {0x011140, 0x0}, + {0x011240, 0x0}, + {0x011340, 0x0}, + {0x011440, 0x0}, + {0x011540, 0x0}, + {0x011640, 0x0}, + {0x011740, 0x0}, + {0x011840, 0x0}, + {0x011030, 0x0}, + {0x011130, 0x0}, + {0x011230, 0x0}, + {0x011330, 0x0}, + {0x011430, 0x0}, + {0x011530, 0x0}, + {0x011630, 0x0}, + {0x011730, 0x0}, + {0x011830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000000}, + {0x00054003, 0x00000c80}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000131f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00002dd4}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00002dd4}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x0000d400}, + {0x00054033, 0x0000312d}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x0000d400}, + {0x00054039, 0x0000312d}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000101}, + {0x00054003, 0x00000190}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000121f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00000084}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00000084}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x00008400}, + {0x00054033, 0x00003100}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x00008400}, + {0x00054039, 0x00003100}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000102}, + {0x00054003, 0x00000064}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000121f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00000084}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00000084}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x00008400}, + {0x00054033, 0x00003100}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x00008400}, + {0x00054039, 0x00003100}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000000}, + {0x00054003, 0x00000c80}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x00000061}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00001f7f}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00002dd4}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00002dd4}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x0000d400}, + {0x00054033, 0x0000312d}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x0000d400}, + {0x00054039, 0x0000312d}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x0}, + {0x90051, 0x45a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x448}, + {0x90055, 0x109}, + {0x90056, 0x40}, + {0x90057, 0x633}, + {0x90058, 0x179}, + {0x90059, 0x1}, + {0x9005a, 0x618}, + {0x9005b, 0x109}, + {0x9005c, 0x40c0}, + {0x9005d, 0x633}, + {0x9005e, 0x149}, + {0x9005f, 0x8}, + {0x90060, 0x4}, + {0x90061, 0x48}, + {0x90062, 0x4040}, + {0x90063, 0x633}, + {0x90064, 0x149}, + {0x90065, 0x0}, + {0x90066, 0x4}, + {0x90067, 0x48}, + {0x90068, 0x40}, + {0x90069, 0x633}, + {0x9006a, 0x149}, + {0x9006b, 0x10}, + {0x9006c, 0x4}, + {0x9006d, 0x18}, + {0x9006e, 0x0}, + {0x9006f, 0x4}, + {0x90070, 0x78}, + {0x90071, 0x549}, + {0x90072, 0x633}, + {0x90073, 0x159}, + {0x90074, 0xd49}, + {0x90075, 0x633}, + {0x90076, 0x159}, + {0x90077, 0x94a}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0x441}, + {0x9007b, 0x633}, + {0x9007c, 0x149}, + {0x9007d, 0x42}, + {0x9007e, 0x633}, + {0x9007f, 0x149}, + {0x90080, 0x1}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0xe0}, + {0x90085, 0x109}, + {0x90086, 0xa}, + {0x90087, 0x10}, + {0x90088, 0x109}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x149}, + {0x9008c, 0x9}, + {0x9008d, 0x3c0}, + {0x9008e, 0x159}, + {0x9008f, 0x18}, + {0x90090, 0x10}, + {0x90091, 0x109}, + {0x90092, 0x0}, + {0x90093, 0x3c0}, + {0x90094, 0x109}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x48}, + {0x90098, 0x18}, + {0x90099, 0x4}, + {0x9009a, 0x58}, + {0x9009b, 0xb}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x1}, + {0x9009f, 0x10}, + {0x900a0, 0x109}, + {0x900a1, 0x5}, + {0x900a2, 0x7c0}, + {0x900a3, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x790}, + {0x900a6, 0x11a}, + {0x900a7, 0x8}, + {0x900a8, 0x7aa}, + {0x900a9, 0x2a}, + {0x900aa, 0x10}, + {0x900ab, 0x7b2}, + {0x900ac, 0x2a}, + {0x900ad, 0x0}, + {0x900ae, 0x7c8}, + {0x900af, 0x109}, + {0x900b0, 0x10}, + {0x900b1, 0x10}, + {0x900b2, 0x109}, + {0x900b3, 0x10}, + {0x900b4, 0x2a8}, + {0x900b5, 0x129}, + {0x900b6, 0x8}, + {0x900b7, 0x370}, + {0x900b8, 0x129}, + {0x900b9, 0xa}, + {0x900ba, 0x3c8}, + {0x900bb, 0x1a9}, + {0x900bc, 0xc}, + {0x900bd, 0x408}, + {0x900be, 0x199}, + {0x900bf, 0x14}, + {0x900c0, 0x790}, + {0x900c1, 0x11a}, + {0x900c2, 0x8}, + {0x900c3, 0x4}, + {0x900c4, 0x18}, + {0x900c5, 0xe}, + {0x900c6, 0x408}, + {0x900c7, 0x199}, + {0x900c8, 0x8}, + {0x900c9, 0x8568}, + {0x900ca, 0x108}, + {0x900cb, 0x18}, + {0x900cc, 0x790}, + {0x900cd, 0x16a}, + {0x900ce, 0x8}, + {0x900cf, 0x1d8}, + {0x900d0, 0x169}, + {0x900d1, 0x10}, + {0x900d2, 0x8558}, + {0x900d3, 0x168}, + {0x900d4, 0x70}, + {0x900d5, 0x788}, + {0x900d6, 0x16a}, + {0x900d7, 0x1ff8}, + {0x900d8, 0x85a8}, + {0x900d9, 0x1e8}, + {0x900da, 0x50}, + {0x900db, 0x798}, + {0x900dc, 0x16a}, + {0x900dd, 0x60}, + {0x900de, 0x7a0}, + {0x900df, 0x16a}, + {0x900e0, 0x8}, + {0x900e1, 0x8310}, + {0x900e2, 0x168}, + {0x900e3, 0x8}, + {0x900e4, 0xa310}, + {0x900e5, 0x168}, + {0x900e6, 0xa}, + {0x900e7, 0x408}, + {0x900e8, 0x169}, + {0x900e9, 0x6e}, + {0x900ea, 0x0}, + {0x900eb, 0x68}, + {0x900ec, 0x0}, + {0x900ed, 0x408}, + {0x900ee, 0x169}, + {0x900ef, 0x0}, + {0x900f0, 0x8310}, + {0x900f1, 0x168}, + {0x900f2, 0x0}, + {0x900f3, 0xa310}, + {0x900f4, 0x168}, + {0x900f5, 0x1ff8}, + {0x900f6, 0x85a8}, + {0x900f7, 0x1e8}, + {0x900f8, 0x68}, + {0x900f9, 0x798}, + {0x900fa, 0x16a}, + {0x900fb, 0x78}, + {0x900fc, 0x7a0}, + {0x900fd, 0x16a}, + {0x900fe, 0x68}, + {0x900ff, 0x790}, + {0x90100, 0x16a}, + {0x90101, 0x8}, + {0x90102, 0x8b10}, + {0x90103, 0x168}, + {0x90104, 0x8}, + {0x90105, 0xab10}, + {0x90106, 0x168}, + {0x90107, 0xa}, + {0x90108, 0x408}, + {0x90109, 0x169}, + {0x9010a, 0x58}, + {0x9010b, 0x0}, + {0x9010c, 0x68}, + {0x9010d, 0x0}, + {0x9010e, 0x408}, + {0x9010f, 0x169}, + {0x90110, 0x0}, + {0x90111, 0x8b10}, + {0x90112, 0x168}, + {0x90113, 0x1}, + {0x90114, 0xab10}, + {0x90115, 0x168}, + {0x90116, 0x0}, + {0x90117, 0x1d8}, + {0x90118, 0x169}, + {0x90119, 0x80}, + {0x9011a, 0x790}, + {0x9011b, 0x16a}, + {0x9011c, 0x18}, + {0x9011d, 0x7aa}, + {0x9011e, 0x6a}, + {0x9011f, 0xa}, + {0x90120, 0x0}, + {0x90121, 0x1e9}, + {0x90122, 0x8}, + {0x90123, 0x8080}, + {0x90124, 0x108}, + {0x90125, 0xf}, + {0x90126, 0x408}, + {0x90127, 0x169}, + {0x90128, 0xc}, + {0x90129, 0x0}, + {0x9012a, 0x68}, + {0x9012b, 0x9}, + {0x9012c, 0x0}, + {0x9012d, 0x1a9}, + {0x9012e, 0x0}, + {0x9012f, 0x408}, + {0x90130, 0x169}, + {0x90131, 0x0}, + {0x90132, 0x8080}, + {0x90133, 0x108}, + {0x90134, 0x8}, + {0x90135, 0x7aa}, + {0x90136, 0x6a}, + {0x90137, 0x0}, + {0x90138, 0x8568}, + {0x90139, 0x108}, + {0x9013a, 0xb7}, + {0x9013b, 0x790}, + {0x9013c, 0x16a}, + {0x9013d, 0x1f}, + {0x9013e, 0x0}, + {0x9013f, 0x68}, + {0x90140, 0x8}, + {0x90141, 0x8558}, + {0x90142, 0x168}, + {0x90143, 0xf}, + {0x90144, 0x408}, + {0x90145, 0x169}, + {0x90146, 0xd}, + {0x90147, 0x0}, + {0x90148, 0x68}, + {0x90149, 0x0}, + {0x9014a, 0x408}, + {0x9014b, 0x169}, + {0x9014c, 0x0}, + {0x9014d, 0x8558}, + {0x9014e, 0x168}, + {0x9014f, 0x8}, + {0x90150, 0x3c8}, + {0x90151, 0x1a9}, + {0x90152, 0x3}, + {0x90153, 0x370}, + {0x90154, 0x129}, + {0x90155, 0x20}, + {0x90156, 0x2aa}, + {0x90157, 0x9}, + {0x90158, 0x0}, + {0x90159, 0x400}, + {0x9015a, 0x10e}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x10c}, + {0x90164, 0x8}, + {0x90165, 0x7c8}, + {0x90166, 0x101}, + {0x90167, 0x8}, + {0x90168, 0x448}, + {0x90169, 0x109}, + {0x9016a, 0xf}, + {0x9016b, 0x7c0}, + {0x9016c, 0x109}, + {0x9016d, 0x0}, + {0x9016e, 0xe8}, + {0x9016f, 0x109}, + {0x90170, 0x47}, + {0x90171, 0x630}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0x618}, + {0x90175, 0x109}, + {0x90176, 0x8}, + {0x90177, 0xe0}, + {0x90178, 0x109}, + {0x90179, 0x0}, + {0x9017a, 0x7c8}, + {0x9017b, 0x109}, + {0x9017c, 0x8}, + {0x9017d, 0x8140}, + {0x9017e, 0x10c}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x8}, + {0x90185, 0x8}, + {0x90186, 0x7c8}, + {0x90187, 0x101}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x8}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x29}, + {0x90026, 0x6a}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x2000b, 0x64}, + {0x2000c, 0xc8}, + {0x2000d, 0x7d0}, + {0x2000e, 0x2c}, + {0x12000b, 0xc}, + {0x12000c, 0x19}, + {0x12000d, 0xfa}, + {0x12000e, 0x10}, + {0x22000b, 0x3}, + {0x22000c, 0x6}, + {0x22000d, 0x3e}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x2}, + {0xd0000, 0x1}, +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 400, 100, }, +}; diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c index 80f79ce888..5d4c2ac4c9 100644 --- a/board/freescale/imx8mn_evk/spl.c +++ b/board/freescale/imx8mn_evk/spl.c @@ -25,6 +25,12 @@ #include #include #include +#include +#include +#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -52,6 +58,43 @@ void spl_board_init(void) printf("Failed to find clock node. Check device tree\n"); } +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pca9450@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */ + /* Set DVS1 to 0.85v for suspend */ + /* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* set VDD_SNVS_0V8 from default 0.85V */ + pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); + + /* enable LDO4 to 1.2v */ + pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x44); + + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); + + return 0; +} +#endif + #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig new file mode 100644 index 0000000000..c53dc968c8 --- /dev/null +++ b/configs/imx8mn_evk_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_WATCHDOG=y From 98bcdf16356c563ae855b0f1fd40d2ead355713b Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 19 Mar 2021 15:57:09 +0800 Subject: [PATCH 017/117] imx8mn: Add low drive mode support for DDR4/LPDDR4 EVK Add dedicated defconfigs for iMX8MN low drive mode which set the VDD_SOC and VDD_DRAM to 0.8v, DDR at 1600MTS (800Mhz clock) and GPU at 200Mhz. Signed-off-by: Ye Li Acked-by: Peng Fan Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/soc.c | 45 + board/freescale/imx8mn_evk/Kconfig | 4 + board/freescale/imx8mn_evk/Makefile | 5 + board/freescale/imx8mn_evk/ddr4_timing_ld.c | 1057 ++++++++++++ board/freescale/imx8mn_evk/lpddr4_timing_ld.c | 1441 +++++++++++++++++ board/freescale/imx8mn_evk/spl.c | 7 +- 6 files changed, 2558 insertions(+), 1 deletion(-) create mode 100644 board/freescale/imx8mn_evk/ddr4_timing_ld.c create mode 100644 board/freescale/imx8mn_evk/lpddr4_timing_ld.c diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index e6bc977fc8..1a752d8fd8 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -726,6 +726,41 @@ int disable_vpu_nodes(void *blob) return -EPERM; } +#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE +static int low_drive_gpu_freq(void *blob) +{ + static const char *nodes_path_8mn[] = { + "/gpu@38000000", + "/soc@0/gpu@38000000" + }; + + int nodeoff, cnt, i; + u32 assignedclks[7]; + + nodeoff = fdt_path_offset(blob, nodes_path_8mn[0]); + if (nodeoff < 0) + return nodeoff; + + cnt = fdtdec_get_int_array_count(blob, nodeoff, "assigned-clock-rates", assignedclks, 7); + if (cnt < 0) + return cnt; + + if (cnt != 7) + printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt); + + assignedclks[cnt - 1] = 200000000; + assignedclks[cnt - 2] = 200000000; + + for (i = 0; i < cnt; i++) { + debug("<%u>, ", assignedclks[i]); + assignedclks[i] = cpu_to_fdt32(assignedclks[i]); + } + debug("\n"); + + return fdt_setprop(blob, nodeoff, "assigned-clock-rates", &assignedclks, sizeof(assignedclks)); +} +#endif + int disable_gpu_nodes(void *blob) { static const char * const nodes_path_8mn[] = { @@ -895,6 +930,16 @@ usb_modify_speed: #elif defined(CONFIG_IMX8MN) if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl()) disable_gpu_nodes(blob); +#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE + else { + int ldm_gpu = low_drive_gpu_freq(blob); + + if (ldm_gpu < 0) + printf("Update GPU node assigned-clock-rates failed\n"); + else + printf("Update GPU node assigned-clock-rates ok\n"); + } +#endif if (is_imx8mnd() || is_imx8mndl()) disable_cpu_nodes(blob, 2); diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig index ace6fc1e39..478f4ed66e 100644 --- a/board/freescale/imx8mn_evk/Kconfig +++ b/board/freescale/imx8mn_evk/Kconfig @@ -9,6 +9,10 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8mn_evk" +config IMX8MN_LOW_DRIVE_MODE + bool "Enable the low drive mode of iMX8MN on EVK board" + default n + source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/imx8mn_evk/Makefile b/board/freescale/imx8mn_evk/Makefile index 5d7dbe6628..42d1179724 100644 --- a/board/freescale/imx8mn_evk/Makefile +++ b/board/freescale/imx8mn_evk/Makefile @@ -8,6 +8,11 @@ obj-y += imx8mn_evk.o ifdef CONFIG_SPL_BUILD obj-y += spl.o +ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_ld.o +obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing_ld.o +else obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o endif +endif diff --git a/board/freescale/imx8mn_evk/ddr4_timing_ld.c b/board/freescale/imx8mn_evk/ddr4_timing_ld.c new file mode 100644 index 0000000000..983fc7d99f --- /dev/null +++ b/board/freescale/imx8mn_evk/ddr4_timing_ld.c @@ -0,0 +1,1057 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400000, 0x81040010 }, + { 0x3d400030, 0x20 }, + { 0x3d400034, 0x221306 }, + { 0x3d400050, 0x210070 }, + { 0x3d400054, 0x10008 }, + { 0x3d400060, 0x0 }, + { 0x3d400064, 0x6100dc }, + { 0x3d4000c0, 0x0 }, + { 0x3d4000c4, 0x1000 }, + { 0x3d4000d0, 0xc00200c5 }, + { 0x3d4000d4, 0x500000 }, + { 0x3d4000dc, 0x2340105 }, + { 0x3d4000e0, 0x0 }, + { 0x3d4000e4, 0x110000 }, + { 0x3d4000e8, 0x2000600 }, + { 0x3d4000ec, 0x410 }, + { 0x3d4000f0, 0x20 }, + { 0x3d4000f4, 0xec7 }, + { 0x3d400100, 0xd0c1b0d }, + { 0x3d400104, 0x30313 }, + { 0x3d400108, 0x508060a }, + { 0x3d40010c, 0x400c }, + { 0x3d400110, 0x6030306 }, + { 0x3d400114, 0x4040302 }, + { 0x3d40011c, 0x404 }, + { 0x3d400120, 0x5050d08 }, + { 0x3d400124, 0x20308 }, + { 0x3d40012c, 0x1406010e }, + { 0x3d400130, 0x8 }, + { 0x3d40013c, 0x0 }, + { 0x3d400180, 0x1000040 }, + { 0x3d400184, 0x30d4 }, + { 0x3d400190, 0x38b8204 }, + { 0x3d400194, 0x2020303 }, + { 0x3d400198, 0x7f04011 }, + { 0x3d40019c, 0xb0 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0x48005a }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x1 }, + { 0x3d4001b4, 0xb04 }, + { 0x3d4001b8, 0x4 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x3f1f }, + { 0x3d400204, 0x3f0909 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf07 }, + { 0x3d400220, 0x3f01 }, + { 0x3d400240, 0x600061c }, + { 0x3d400244, 0x1323 }, + { 0x3d400400, 0x100 }, + { 0x3d400250, 0x317d1a07 }, + { 0x3d400254, 0xf }, + { 0x3d40025c, 0x2a001b76 }, + { 0x3d400264, 0x7300b473 }, + { 0x3d40026c, 0x30000e06 }, + { 0x3d400300, 0x14 }, + { 0x3d40036c, 0x10 }, + { 0x3d400404, 0x13193 }, + { 0x3d400408, 0x6096 }, + { 0x3d400490, 0x1 }, + { 0x3d400494, 0x2000c00 }, + { 0x3d400498, 0x3c00db }, + { 0x3d40049c, 0x100009 }, + { 0x3d4004a0, 0x2 }, + { 0x3d402050, 0x210070 }, + { 0x3d402064, 0x400093 }, + { 0x3d4020dc, 0x40105 }, + { 0x3d4020e0, 0x0 }, + { 0x3d4020e8, 0x2000600 }, + { 0x3d4020ec, 0x10 }, + { 0x3d402100, 0xb081209 }, + { 0x3d402104, 0x2020d }, + { 0x3d402108, 0x5050309 }, + { 0x3d40210c, 0x400c }, + { 0x3d402110, 0x5030206 }, + { 0x3d402114, 0x3030202 }, + { 0x3d40211c, 0x303 }, + { 0x3d402120, 0x4040d06 }, + { 0x3d402124, 0x20208 }, + { 0x3d40212c, 0x1205010e }, + { 0x3d402130, 0x8 }, + { 0x3d40213c, 0x0 }, + { 0x3d402180, 0x1000040 }, + { 0x3d402190, 0x3858204 }, + { 0x3d402194, 0x2020303 }, + { 0x3d4021b4, 0x504 }, + { 0x3d4021b8, 0x4 }, + { 0x3d402240, 0x6000604 }, + { 0x3d4020f4, 0xec7 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x1005f, 0x2fd }, + { 0x1015f, 0x2fd }, + { 0x1105f, 0x2fd }, + { 0x1115f, 0x2fd }, + { 0x11005f, 0x2fd }, + { 0x11015f, 0x2fd }, + { 0x11105f, 0x2fd }, + { 0x11115f, 0x2fd }, + { 0x55, 0x355 }, + { 0x1055, 0x355 }, + { 0x2055, 0x355 }, + { 0x3055, 0x355 }, + { 0x4055, 0x55 }, + { 0x5055, 0x55 }, + { 0x6055, 0x355 }, + { 0x7055, 0x355 }, + { 0x8055, 0x355 }, + { 0x9055, 0x355 }, + { 0x200c5, 0xb }, + { 0x1200c5, 0x6 }, + { 0x2002e, 0x1 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x20056, 0xa }, + { 0x120056, 0xa }, + { 0x1004d, 0x1a }, + { 0x1014d, 0x1a }, + { 0x1104d, 0x1a }, + { 0x1114d, 0x1a }, + { 0x11004d, 0x1a }, + { 0x11014d, 0x1a }, + { 0x11104d, 0x1a }, + { 0x11114d, 0x1a }, + { 0x10049, 0xe38 }, + { 0x10149, 0xe38 }, + { 0x11049, 0xe38 }, + { 0x11149, 0xe38 }, + { 0x110049, 0xe38 }, + { 0x110149, 0xe38 }, + { 0x111049, 0xe38 }, + { 0x111149, 0xe38 }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x2 }, + { 0x20050, 0x0 }, + { 0x20008, 0x190 }, + { 0x120008, 0x10a }, + { 0x20088, 0x9 }, + { 0x200b2, 0x268 }, + { 0x10043, 0x5b1 }, + { 0x10143, 0x5b1 }, + { 0x11043, 0x5b1 }, + { 0x11143, 0x5b1 }, + { 0x1200b2, 0x268 }, + { 0x110043, 0x5b1 }, + { 0x110143, 0x5b1 }, + { 0x111043, 0x5b1 }, + { 0x111143, 0x5b1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x2005b, 0x7529 }, + { 0x2005c, 0x0 }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x200cc, 0x1f7 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x1200cc, 0x1f7 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x0200cb, 0x0}, + {0x010043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x010143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x011043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x011143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x000080, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x001080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x002080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x003080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x004080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x005080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x006080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x007080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x008080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x009080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x010080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x010180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x010081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x010181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x010082, 0x0}, + {0x110082, 0x0}, + {0x210082, 0x0}, + {0x010182, 0x0}, + {0x110182, 0x0}, + {0x210182, 0x0}, + {0x010083, 0x0}, + {0x110083, 0x0}, + {0x210083, 0x0}, + {0x010183, 0x0}, + {0x110183, 0x0}, + {0x210183, 0x0}, + {0x011080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x011180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x011081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x011181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x011082, 0x0}, + {0x111082, 0x0}, + {0x211082, 0x0}, + {0x011182, 0x0}, + {0x111182, 0x0}, + {0x211182, 0x0}, + {0x011083, 0x0}, + {0x111083, 0x0}, + {0x211083, 0x0}, + {0x011183, 0x0}, + {0x111183, 0x0}, + {0x211183, 0x0}, + {0x0100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x0101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x0100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x0101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x0100d2, 0x0}, + {0x1100d2, 0x0}, + {0x2100d2, 0x0}, + {0x0101d2, 0x0}, + {0x1101d2, 0x0}, + {0x2101d2, 0x0}, + {0x0100d3, 0x0}, + {0x1100d3, 0x0}, + {0x2100d3, 0x0}, + {0x0101d3, 0x0}, + {0x1101d3, 0x0}, + {0x2101d3, 0x0}, + {0x0110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x0111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x0110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x0111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x0110d2, 0x0}, + {0x1110d2, 0x0}, + {0x2110d2, 0x0}, + {0x0111d2, 0x0}, + {0x1111d2, 0x0}, + {0x2111d2, 0x0}, + {0x0110d3, 0x0}, + {0x1110d3, 0x0}, + {0x2110d3, 0x0}, + {0x0111d3, 0x0}, + {0x1111d3, 0x0}, + {0x2111d3, 0x0}, + {0x010068, 0x0}, + {0x010168, 0x0}, + {0x010268, 0x0}, + {0x010368, 0x0}, + {0x010468, 0x0}, + {0x010568, 0x0}, + {0x010668, 0x0}, + {0x010768, 0x0}, + {0x010868, 0x0}, + {0x010069, 0x0}, + {0x010169, 0x0}, + {0x010269, 0x0}, + {0x010369, 0x0}, + {0x010469, 0x0}, + {0x010569, 0x0}, + {0x010669, 0x0}, + {0x010769, 0x0}, + {0x010869, 0x0}, + {0x01006a, 0x0}, + {0x01016a, 0x0}, + {0x01026a, 0x0}, + {0x01036a, 0x0}, + {0x01046a, 0x0}, + {0x01056a, 0x0}, + {0x01066a, 0x0}, + {0x01076a, 0x0}, + {0x01086a, 0x0}, + {0x01006b, 0x0}, + {0x01016b, 0x0}, + {0x01026b, 0x0}, + {0x01036b, 0x0}, + {0x01046b, 0x0}, + {0x01056b, 0x0}, + {0x01066b, 0x0}, + {0x01076b, 0x0}, + {0x01086b, 0x0}, + {0x011068, 0x0}, + {0x011168, 0x0}, + {0x011268, 0x0}, + {0x011368, 0x0}, + {0x011468, 0x0}, + {0x011568, 0x0}, + {0x011668, 0x0}, + {0x011768, 0x0}, + {0x011868, 0x0}, + {0x011069, 0x0}, + {0x011169, 0x0}, + {0x011269, 0x0}, + {0x011369, 0x0}, + {0x011469, 0x0}, + {0x011569, 0x0}, + {0x011669, 0x0}, + {0x011769, 0x0}, + {0x011869, 0x0}, + {0x01106a, 0x0}, + {0x01116a, 0x0}, + {0x01126a, 0x0}, + {0x01136a, 0x0}, + {0x01146a, 0x0}, + {0x01156a, 0x0}, + {0x01166a, 0x0}, + {0x01176a, 0x0}, + {0x01186a, 0x0}, + {0x01106b, 0x0}, + {0x01116b, 0x0}, + {0x01126b, 0x0}, + {0x01136b, 0x0}, + {0x01146b, 0x0}, + {0x01156b, 0x0}, + {0x01166b, 0x0}, + {0x01176b, 0x0}, + {0x01186b, 0x0}, + {0x01008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x01018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x01008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x01018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x01008e, 0x0}, + {0x11008e, 0x0}, + {0x21008e, 0x0}, + {0x01018e, 0x0}, + {0x11018e, 0x0}, + {0x21018e, 0x0}, + {0x01008f, 0x0}, + {0x11008f, 0x0}, + {0x21008f, 0x0}, + {0x01018f, 0x0}, + {0x11018f, 0x0}, + {0x21018f, 0x0}, + {0x01108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x01118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x01108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x01118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x01108e, 0x0}, + {0x11108e, 0x0}, + {0x21108e, 0x0}, + {0x01118e, 0x0}, + {0x11118e, 0x0}, + {0x21118e, 0x0}, + {0x01108f, 0x0}, + {0x11108f, 0x0}, + {0x21108f, 0x0}, + {0x01118f, 0x0}, + {0x11118f, 0x0}, + {0x21118f, 0x0}, + {0x0100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x0101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x0102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x0103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x0104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x0105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x0106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x0107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x0108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x0100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x0101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x0102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x0103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x0104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x0105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x0106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x0107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x0108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x0100c2, 0x0}, + {0x1100c2, 0x0}, + {0x2100c2, 0x0}, + {0x0101c2, 0x0}, + {0x1101c2, 0x0}, + {0x2101c2, 0x0}, + {0x0102c2, 0x0}, + {0x1102c2, 0x0}, + {0x2102c2, 0x0}, + {0x0103c2, 0x0}, + {0x1103c2, 0x0}, + {0x2103c2, 0x0}, + {0x0104c2, 0x0}, + {0x1104c2, 0x0}, + {0x2104c2, 0x0}, + {0x0105c2, 0x0}, + {0x1105c2, 0x0}, + {0x2105c2, 0x0}, + {0x0106c2, 0x0}, + {0x1106c2, 0x0}, + {0x2106c2, 0x0}, + {0x0107c2, 0x0}, + {0x1107c2, 0x0}, + {0x2107c2, 0x0}, + {0x0108c2, 0x0}, + {0x1108c2, 0x0}, + {0x2108c2, 0x0}, + {0x0100c3, 0x0}, + {0x1100c3, 0x0}, + {0x2100c3, 0x0}, + {0x0101c3, 0x0}, + {0x1101c3, 0x0}, + {0x2101c3, 0x0}, + {0x0102c3, 0x0}, + {0x1102c3, 0x0}, + {0x2102c3, 0x0}, + {0x0103c3, 0x0}, + {0x1103c3, 0x0}, + {0x2103c3, 0x0}, + {0x0104c3, 0x0}, + {0x1104c3, 0x0}, + {0x2104c3, 0x0}, + {0x0105c3, 0x0}, + {0x1105c3, 0x0}, + {0x2105c3, 0x0}, + {0x0106c3, 0x0}, + {0x1106c3, 0x0}, + {0x2106c3, 0x0}, + {0x0107c3, 0x0}, + {0x1107c3, 0x0}, + {0x2107c3, 0x0}, + {0x0108c3, 0x0}, + {0x1108c3, 0x0}, + {0x2108c3, 0x0}, + {0x0110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x0111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x0112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x0113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x0114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x0115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x0116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x0117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x0118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x0110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x0111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x0112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x0113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x0114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x0115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x0116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x0117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x0118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x0110c2, 0x0}, + {0x1110c2, 0x0}, + {0x2110c2, 0x0}, + {0x0111c2, 0x0}, + {0x1111c2, 0x0}, + {0x2111c2, 0x0}, + {0x0112c2, 0x0}, + {0x1112c2, 0x0}, + {0x2112c2, 0x0}, + {0x0113c2, 0x0}, + {0x1113c2, 0x0}, + {0x2113c2, 0x0}, + {0x0114c2, 0x0}, + {0x1114c2, 0x0}, + {0x2114c2, 0x0}, + {0x0115c2, 0x0}, + {0x1115c2, 0x0}, + {0x2115c2, 0x0}, + {0x0116c2, 0x0}, + {0x1116c2, 0x0}, + {0x2116c2, 0x0}, + {0x0117c2, 0x0}, + {0x1117c2, 0x0}, + {0x2117c2, 0x0}, + {0x0118c2, 0x0}, + {0x1118c2, 0x0}, + {0x2118c2, 0x0}, + {0x0110c3, 0x0}, + {0x1110c3, 0x0}, + {0x2110c3, 0x0}, + {0x0111c3, 0x0}, + {0x1111c3, 0x0}, + {0x2111c3, 0x0}, + {0x0112c3, 0x0}, + {0x1112c3, 0x0}, + {0x2112c3, 0x0}, + {0x0113c3, 0x0}, + {0x1113c3, 0x0}, + {0x2113c3, 0x0}, + {0x0114c3, 0x0}, + {0x1114c3, 0x0}, + {0x2114c3, 0x0}, + {0x0115c3, 0x0}, + {0x1115c3, 0x0}, + {0x2115c3, 0x0}, + {0x0116c3, 0x0}, + {0x1116c3, 0x0}, + {0x2116c3, 0x0}, + {0x0117c3, 0x0}, + {0x1117c3, 0x0}, + {0x2117c3, 0x0}, + {0x0118c3, 0x0}, + {0x1118c3, 0x0}, + {0x2118c3, 0x0}, + {0x010020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x011020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x02007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x010040, 0x0}, + {0x010140, 0x0}, + {0x010240, 0x0}, + {0x010340, 0x0}, + {0x010440, 0x0}, + {0x010540, 0x0}, + {0x010640, 0x0}, + {0x010740, 0x0}, + {0x010840, 0x0}, + {0x010030, 0x0}, + {0x010130, 0x0}, + {0x010230, 0x0}, + {0x010330, 0x0}, + {0x010430, 0x0}, + {0x010530, 0x0}, + {0x010630, 0x0}, + {0x010730, 0x0}, + {0x010830, 0x0}, + {0x011040, 0x0}, + {0x011140, 0x0}, + {0x011240, 0x0}, + {0x011340, 0x0}, + {0x011440, 0x0}, + {0x011540, 0x0}, + {0x011640, 0x0}, + {0x011740, 0x0}, + {0x011840, 0x0}, + {0x011030, 0x0}, + {0x011130, 0x0}, + {0x011230, 0x0}, + {0x011330, 0x0}, + {0x011430, 0x0}, + {0x011530, 0x0}, + {0x011630, 0x0}, + {0x011730, 0x0}, + {0x011830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x234 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x410 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x42a }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x4 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x10 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x5400e, 0x1f7f }, + { 0x54012, 0x1 }, + { 0x5402f, 0x234 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x410 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xb }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x633 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x633 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x633 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x633 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x633 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x633 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xb }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x1 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x5 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x0 }, + { 0x900a2, 0x8140 }, + { 0x900a3, 0x10c }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x8138 }, + { 0x900a6, 0x10c }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7c8 }, + { 0x900a9, 0x101 }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x448 }, + { 0x900ac, 0x109 }, + { 0x900ad, 0xf }, + { 0x900ae, 0x7c0 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x47 }, + { 0x900b1, 0x630 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x8 }, + { 0x900b4, 0x618 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0xe0 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x0 }, + { 0x900ba, 0x7c8 }, + { 0x900bb, 0x109 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x8140 }, + { 0x900be, 0x10c }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x1 }, + { 0x900c1, 0x8 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x8 }, + { 0x900c5, 0x8 }, + { 0x900c6, 0x7c8 }, + { 0x900c7, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2b }, + { 0x2000b, 0x32 }, + { 0x2000c, 0x64 }, + { 0x2000d, 0x3e8 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x21 }, + { 0x12000c, 0x42 }, + { 0x12000d, 0x29a }, + { 0x12000e, 0x21 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1066mts 1D */ + .drate = 1066, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 1600mts 2D */ + .drate = 1600, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1600, 1066, }, +}; + diff --git a/board/freescale/imx8mn_evk/lpddr4_timing_ld.c b/board/freescale/imx8mn_evk/lpddr4_timing_ld.c new file mode 100644 index 0000000000..5faa0021a7 --- /dev/null +++ b/board/freescale/imx8mn_evk/lpddr4_timing_ld.c @@ -0,0 +1,1441 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x111 }, + { 0x3d400024, 0x1f400 }, + { 0x3d400064, 0x300070 }, + { 0x3d4000d0, 0xc002030f }, + { 0x3d4000d4, 0x500000 }, + { 0x3d4000dc, 0xa40012 }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x66004d }, + { 0x3d4000ec, 0x16004d }, + { 0x3d400100, 0x10100d11 }, + { 0x3d400104, 0x3041a }, + { 0x3d40010c, 0x606000 }, + { 0x3d400110, 0x8040408 }, + { 0x3d400114, 0x2030606 }, + { 0x3d400118, 0x1010004 }, + { 0x3d40011c, 0x301 }, + { 0x3d400130, 0x20300 }, + { 0x3d400134, 0xa100002 }, + { 0x3d400138, 0x73 }, + { 0x3d400144, 0x500028 }, + { 0x3d400180, 0x190000c }, + { 0x3d400184, 0x14030d4 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x4898204 }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x904 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x4070f0f }, + { 0x3d400200, 0x17 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x11 }, + { 0x3d402024, 0x7d00 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, + { 0x3d4020ec, 0x16004d }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x11 }, + { 0x3d403024, 0x1f40 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, + { 0x3d4030ec, 0x16004d }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0xb }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x1 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x190 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0xdc }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2005b, 0x7529 }, + { 0x2005c, 0x0 }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x200cc, 0x1f7 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x1200cc, 0x1f7 }, + { 0x2200c7, 0x21 }, + { 0x2200ca, 0x24 }, + { 0x2200cc, 0x1f7 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x0200cb, 0x0}, + {0x010043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x010143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x011043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x011143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x000080, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x001080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x002080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x003080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x004080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x005080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x006080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x007080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x008080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x009080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x010080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x010180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x011080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x011180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x010081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x010181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x011081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x011181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x0100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x0101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x0110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x0111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x0100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x0101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x0110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x0111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x010068, 0x0}, + {0x010168, 0x0}, + {0x010268, 0x0}, + {0x010368, 0x0}, + {0x010468, 0x0}, + {0x010568, 0x0}, + {0x010668, 0x0}, + {0x010768, 0x0}, + {0x010868, 0x0}, + {0x011068, 0x0}, + {0x011168, 0x0}, + {0x011268, 0x0}, + {0x011368, 0x0}, + {0x011468, 0x0}, + {0x011568, 0x0}, + {0x011668, 0x0}, + {0x011768, 0x0}, + {0x011868, 0x0}, + {0x010069, 0x0}, + {0x010169, 0x0}, + {0x010269, 0x0}, + {0x010369, 0x0}, + {0x010469, 0x0}, + {0x010569, 0x0}, + {0x010669, 0x0}, + {0x010769, 0x0}, + {0x010869, 0x0}, + {0x011069, 0x0}, + {0x011169, 0x0}, + {0x011269, 0x0}, + {0x011369, 0x0}, + {0x011469, 0x0}, + {0x011569, 0x0}, + {0x011669, 0x0}, + {0x011769, 0x0}, + {0x011869, 0x0}, + {0x01008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x01018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x01108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x01118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x01008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x01018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x01108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x01118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x0100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x0101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x0102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x0103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x0104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x0105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x0106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x0107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x0108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x0110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x0111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x0112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x0113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x0114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x0115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x0116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x0117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x0118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x0100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x0101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x0102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x0103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x0104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x0105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x0106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x0107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x0108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x0110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x0111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x0112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x0113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x0114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x0115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x0116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x0117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x0118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x010020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x011020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x020072, 0x0}, + {0x020073, 0x0}, + {0x020074, 0x0}, + {0x0100aa, 0x0}, + {0x0110aa, 0x0}, + {0x020010, 0x0}, + {0x120010, 0x0}, + {0x220010, 0x0}, + {0x020011, 0x0}, + {0x120011, 0x0}, + {0x220011, 0x0}, + {0x0100ae, 0x0}, + {0x1100ae, 0x0}, + {0x2100ae, 0x0}, + {0x0100af, 0x0}, + {0x1100af, 0x0}, + {0x2100af, 0x0}, + {0x0110ae, 0x0}, + {0x1110ae, 0x0}, + {0x2110ae, 0x0}, + {0x0110af, 0x0}, + {0x1110af, 0x0}, + {0x2110af, 0x0}, + {0x020020, 0x0}, + {0x120020, 0x0}, + {0x220020, 0x0}, + {0x0100a0, 0x0}, + {0x0100a1, 0x0}, + {0x0100a2, 0x0}, + {0x0100a3, 0x0}, + {0x0100a4, 0x0}, + {0x0100a5, 0x0}, + {0x0100a6, 0x0}, + {0x0100a7, 0x0}, + {0x0110a0, 0x0}, + {0x0110a1, 0x0}, + {0x0110a2, 0x0}, + {0x0110a3, 0x0}, + {0x0110a4, 0x0}, + {0x0110a5, 0x0}, + {0x0110a6, 0x0}, + {0x0110a7, 0x0}, + {0x02007c, 0x0}, + {0x12007c, 0x0}, + {0x22007c, 0x0}, + {0x02007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x0400fd, 0x0}, + {0x0400c0, 0x0}, + {0x090201, 0x0}, + {0x190201, 0x0}, + {0x290201, 0x0}, + {0x090202, 0x0}, + {0x190202, 0x0}, + {0x290202, 0x0}, + {0x090203, 0x0}, + {0x190203, 0x0}, + {0x290203, 0x0}, + {0x090204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x090205, 0x0}, + {0x190205, 0x0}, + {0x290205, 0x0}, + {0x090206, 0x0}, + {0x190206, 0x0}, + {0x290206, 0x0}, + {0x090207, 0x0}, + {0x190207, 0x0}, + {0x290207, 0x0}, + {0x090208, 0x0}, + {0x190208, 0x0}, + {0x290208, 0x0}, + {0x010062, 0x0}, + {0x010162, 0x0}, + {0x010262, 0x0}, + {0x010362, 0x0}, + {0x010462, 0x0}, + {0x010562, 0x0}, + {0x010662, 0x0}, + {0x010762, 0x0}, + {0x010862, 0x0}, + {0x011062, 0x0}, + {0x011162, 0x0}, + {0x011262, 0x0}, + {0x011362, 0x0}, + {0x011462, 0x0}, + {0x011562, 0x0}, + {0x011662, 0x0}, + {0x011762, 0x0}, + {0x011862, 0x0}, + {0x020077, 0x0}, + {0x010001, 0x0}, + {0x011001, 0x0}, + {0x010040, 0x0}, + {0x010140, 0x0}, + {0x010240, 0x0}, + {0x010340, 0x0}, + {0x010440, 0x0}, + {0x010540, 0x0}, + {0x010640, 0x0}, + {0x010740, 0x0}, + {0x010840, 0x0}, + {0x010030, 0x0}, + {0x010130, 0x0}, + {0x010230, 0x0}, + {0x010330, 0x0}, + {0x010430, 0x0}, + {0x010530, 0x0}, + {0x010630, 0x0}, + {0x010730, 0x0}, + {0x010830, 0x0}, + {0x011040, 0x0}, + {0x011140, 0x0}, + {0x011240, 0x0}, + {0x011340, 0x0}, + {0x011440, 0x0}, + {0x011540, 0x0}, + {0x011640, 0x0}, + {0x011740, 0x0}, + {0x011840, 0x0}, + {0x011030, 0x0}, + {0x011130, 0x0}, + {0x011230, 0x0}, + {0x011330, 0x0}, + {0x011430, 0x0}, + {0x011530, 0x0}, + {0x011630, 0x0}, + {0x011730, 0x0}, + {0x011830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x12a4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x12a4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x54032, 0xa400 }, + { 0x54033, 0x3112 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xa400 }, + { 0x54039, 0x3112 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x12a4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x12a4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x54032, 0xa400 }, + { 0x54033, 0x3112 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xa400 }, + { 0x54039, 0x3112 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x448 }, + { 0x90169, 0x109 }, + { 0x9016a, 0xf }, + { 0x9016b, 0x7c0 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x0 }, + { 0x9016e, 0xe8 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x47 }, + { 0x90171, 0x630 }, + { 0x90172, 0x109 }, + { 0x90173, 0x8 }, + { 0x90174, 0x618 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0xe0 }, + { 0x90178, 0x109 }, + { 0x90179, 0x0 }, + { 0x9017a, 0x7c8 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x8 }, + { 0x9017d, 0x8140 }, + { 0x9017e, 0x10c }, + { 0x9017f, 0x0 }, + { 0x90180, 0x1 }, + { 0x90181, 0x8 }, + { 0x90182, 0x8 }, + { 0x90183, 0x4 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x7c8 }, + { 0x90187, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x32 }, + { 0x2000c, 0x64 }, + { 0x2000d, 0x3e8 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 1600mts 2D */ + .drate = 1600, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1600, 400, 100, }, +}; diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c index 5d4c2ac4c9..03f2a56e80 100644 --- a/board/freescale/imx8mn_evk/spl.c +++ b/board/freescale/imx8mn_evk/spl.c @@ -75,10 +75,15 @@ int power_init_board(void) /* BUCKxOUT_DVS0/1 control BUCK123 output */ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); +#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE + /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); +#else /* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); +#endif /* Set DVS1 to 0.85v for suspend */ /* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); From c4f78cbf0e0682d5e2f097560163f44b9c7db11f Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 19 Mar 2021 15:57:11 +0800 Subject: [PATCH 018/117] imx8mn: Add support for 11x11 UltraLite part number There are 3 part numbers for 11x11 i.MX8MNano with different core number configuration: UltraLite Quad/Dual/Solo Comparing with i.MX8MN Lite parts, they have MIPI DSI disabled. So checking the MIPI DSI disable fuse to recognize these parts. Signed-off-by: Ye Li Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx/cpu.h | 11 ++++--- arch/arm/include/asm/mach-imx/sys_proto.h | 6 +++- arch/arm/mach-imx/cpu.c | 8 ++++- arch/arm/mach-imx/imx8m/soc.c | 36 +++++++++++++++-------- 4 files changed, 43 insertions(+), 18 deletions(-) diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index f37fe21446..28244d7671 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -40,10 +40,13 @@ #define MXC_CPU_IMX8MNL 0x8e /* dummy ID */ #define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */ #define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */ -#define MXC_CPU_IMX8MP 0x182/* dummy ID */ -#define MXC_CPU_IMX8MP6 0x184 /* dummy ID */ -#define MXC_CPU_IMX8MPL 0x186 /* dummy ID */ -#define MXC_CPU_IMX8MPD 0x187 /* dummy ID */ +#define MXC_CPU_IMX8MNUQ 0x182 /* dummy ID */ +#define MXC_CPU_IMX8MNUD 0x183 /* dummy ID */ +#define MXC_CPU_IMX8MNUS 0x184 /* dummy ID */ +#define MXC_CPU_IMX8MP 0x185/* dummy ID */ +#define MXC_CPU_IMX8MP6 0x186 /* dummy ID */ +#define MXC_CPU_IMX8MPL 0x187 /* dummy ID */ +#define MXC_CPU_IMX8MPD 0x188 /* dummy ID */ #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ #define MXC_CPU_IMX8QM 0x91 /* dummy ID */ #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 43eae6d796..c7668ffc4d 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -60,12 +60,16 @@ struct bd_info; #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL)) #define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \ is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \ - is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL)) + is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL) || \ + is_cpu_type(MXC_CPU_IMX8MNUD) || is_cpu_type(MXC_CPU_IMX8MNUS) || is_cpu_type(MXC_CPU_IMX8MNUQ)) #define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND)) #define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS)) #define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL)) #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL)) #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL)) +#define is_imx8mnuq() (is_cpu_type(MXC_CPU_IMX8MNUQ)) +#define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD)) +#define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS)) #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \ is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6)) #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD)) diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 38b87ed5c3..423b715352 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -117,7 +117,13 @@ const char *get_imx_type(u32 imxtype) case MXC_CPU_IMX8MNDL: return "8MNano DualLite"; /* Dual-core Lite version */ case MXC_CPU_IMX8MNSL: - return "8MNano SoloLite"; /* Single-core Lite version */ + return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */ + case MXC_CPU_IMX8MNUQ: + return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */ + case MXC_CPU_IMX8MNUD: + return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */ + case MXC_CPU_IMX8MNUS: + return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */ case MXC_CPU_IMX8MM: return "8MMQ"; /* Quad-core version of the imx8mm */ case MXC_CPU_IMX8MML: diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 1a752d8fd8..cda3a593ae 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -324,18 +324,30 @@ static u32 get_cpu_variant_type(u32 type) } else if (type == MXC_CPU_IMX8MN) { switch (value & 0x3) { case 2: - if (value & 0x1000000) - return MXC_CPU_IMX8MNDL; - else + if (value & 0x1000000) { + if (value & 0x10000000) /* MIPI DSI */ + return MXC_CPU_IMX8MNUD; + else + return MXC_CPU_IMX8MNDL; + } else { return MXC_CPU_IMX8MND; + } case 3: - if (value & 0x1000000) - return MXC_CPU_IMX8MNSL; - else + if (value & 0x1000000) { + if (value & 0x10000000) /* MIPI DSI */ + return MXC_CPU_IMX8MNUS; + else + return MXC_CPU_IMX8MNSL; + } else { return MXC_CPU_IMX8MNS; + } default: - if (value & 0x1000000) - return MXC_CPU_IMX8MNL; + if (value & 0x1000000) { + if (value & 0x10000000) /* MIPI DSI */ + return MXC_CPU_IMX8MNUQ; + else + return MXC_CPU_IMX8MNL; + } break; } } else if (type == MXC_CPU_IMX8MP) { @@ -468,7 +480,7 @@ int arch_cpu_init(void) if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() || is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() || - is_imx8mnsl() || is_imx8mpd()) { + is_imx8mnsl() || is_imx8mpd() || is_imx8mnud() || is_imx8mnus()) { /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */ struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840); struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880); @@ -477,7 +489,7 @@ int arch_cpu_init(void) writel(0x1, &pgc_core2->pgcr); writel(0x1, &pgc_core3->pgcr); - if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl()) { + if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) { writel(0x1, &pgc_core1->pgcr); writel(0xE, &gpc->cpu_pgc_dn_trg); } else { @@ -941,9 +953,9 @@ usb_modify_speed: } #endif - if (is_imx8mnd() || is_imx8mndl()) + if (is_imx8mnd() || is_imx8mndl() || is_imx8mnud()) disable_cpu_nodes(blob, 2); - else if (is_imx8mns() || is_imx8mnsl()) + else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) disable_cpu_nodes(blob, 3); #elif defined(CONFIG_IMX8MP) From 4e83c05722a8e0afbc32fd9d758fa745d371ca35 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 19 Mar 2021 15:57:12 +0800 Subject: [PATCH 019/117] imx8m: Update thermal and PMU kernel nodes for dual/single cores For dual core and single core iMX8M parts, the thermal node and PMU node in kernel DTB also needs update to remove the refers to deleted core nodes. Otherwise both driver will fail to work. Signed-off-by: Ye Li Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/soc.c | 76 +++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index cda3a593ae..7ff8d8fa8c 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -810,6 +810,79 @@ int disable_dsp_nodes(void *blob) return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp)); } +static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores) +{ + static const char * const thermal_path[] = { + "/thermal-zones/cpu-thermal/cooling-maps/map0" + }; + + int nodeoff, cnt, i, ret, j; + u32 cooling_dev[12]; + + for (i = 0; i < ARRAY_SIZE(thermal_path); i++) { + nodeoff = fdt_path_offset(blob, thermal_path[i]); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", cooling_dev, 12); + if (cnt < 0) + continue; + + if (cnt != 12) + printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt); + + for (j = 0; j < cnt; j++) + cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]); + + ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev, + sizeof(u32) * (12 - disabled_cores * 3)); + if (ret < 0) { + printf("Warning: %s, cooling-device setprop failed %d\n", + thermal_path[i], ret); + continue; + } + + printf("Update node %s, cooling-device prop\n", thermal_path[i]); + } +} + +static void disable_pmu_cpu_nodes(void *blob, u32 disabled_cores) +{ + static const char * const pmu_path[] = { + "/pmu" + }; + + int nodeoff, cnt, i, ret, j; + u32 irq_affinity[4]; + + for (i = 0; i < ARRAY_SIZE(pmu_path); i++) { + nodeoff = fdt_path_offset(blob, pmu_path[i]); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + cnt = fdtdec_get_int_array_count(blob, nodeoff, "interrupt-affinity", + irq_affinity, 4); + if (cnt < 0) + continue; + + if (cnt != 4) + printf("Warning: %s, interrupt-affinity count %d\n", pmu_path[i], cnt); + + for (j = 0; j < cnt; j++) + irq_affinity[j] = cpu_to_fdt32(irq_affinity[j]); + + ret = fdt_setprop(blob, nodeoff, "interrupt-affinity", &irq_affinity, + sizeof(u32) * (4 - disabled_cores)); + if (ret < 0) { + printf("Warning: %s, interrupt-affinity setprop failed %d\n", + pmu_path[i], ret); + continue; + } + + printf("Update node %s, interrupt-affinity prop\n", pmu_path[i]); + } +} + static int disable_cpu_nodes(void *blob, u32 disabled_cores) { static const char * const nodes_path[] = { @@ -842,6 +915,9 @@ static int disable_cpu_nodes(void *blob, u32 disabled_cores) } } + disable_thermal_cpu_nodes(blob, disabled_cores); + disable_pmu_cpu_nodes(blob, disabled_cores); + return 0; } From c0e2f76b697d67fd26e6fe47a11fd8d2f7ca833f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Mar 2021 15:57:13 +0800 Subject: [PATCH 020/117] imx8m: soc: update fuse path Update fuse path to disable modules correctly. Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/soc.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 7ff8d8fa8c..f322488c00 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -628,7 +628,8 @@ static int disable_mipi_dsi_nodes(void *blob) "/mipi_dsi_bridge@30A00000", "/dsi_phy@30A00300", "/soc@0/bus@30800000/mipi_dsi@30a00000", - "/soc@0/bus@30800000/dphy@30a00300" + "/soc@0/bus@30800000/dphy@30a00300", + "/soc@0/bus@30800000/mipi-dsi@30a00000", }; return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path)); @@ -656,7 +657,8 @@ static int check_mipi_dsi_nodes(void *blob) { static const char * const lcdif_path[] = { "/lcdif@30320000", - "/soc@0/bus@30000000/lcdif@30320000" + "/soc@0/bus@30000000/lcdif@30320000", + "/soc@0/bus@30000000/lcd-controller@30320000" }; static const char * const mipi_dsi_path[] = { "/mipi_dsi@30A00000", @@ -664,11 +666,13 @@ static int check_mipi_dsi_nodes(void *blob) }; static const char * const lcdif_ep_path[] = { "/lcdif@30320000/port@0/mipi-dsi-endpoint", - "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint" + "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint", + "/soc@0/bus@30000000/lcd-controller@30320000/port@0/endpoint" }; static const char * const mipi_dsi_ep_path[] = { "/mipi_dsi@30A00000/port@1/endpoint", - "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint" + "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint", + "/soc@0/bus@30800000/mipi-dsi@30a00000/ports/port@0/endpoint@0" }; int lookup_node; @@ -776,7 +780,8 @@ static int low_drive_gpu_freq(void *blob) int disable_gpu_nodes(void *blob) { static const char * const nodes_path_8mn[] = { - "/gpu@38000000" + "/gpu@38000000", + "/soc@/gpu@38000000" }; return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn)); From 8f9f6ba85556a4ab9f1df93d85ff44ce0dbbd4fa Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 19 Mar 2021 15:57:14 +0800 Subject: [PATCH 021/117] imx8m: ddr: Disable CA VREF Training for LPDDR4 Users reported LPDDR4 MR12 value is set to 0 during PHY training, not the value from FSP timing structure, which cause compliance test failed. The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing but not set in 1D. According to PHY training application node, to enable the feature both 1D and 2D need set this field to 1, otherwise the training result will be incorrect. The PHY training doc also recommends to set CATrainOpt[0] to 0 to use MR12 value from message block (FSP structure). So update the LPDDR4 scripts of all mscale to clear CATrainOpt[0]. Signed-off-by: Ye Li Reviewed-by: Jacky Bai Signed-off-by: Peng Fan --- board/freescale/imx8mn_evk/lpddr4_timing_ld.c | 1 - board/freescale/imx8mp_evk/lpddr4_timing.c | 2 -- 2 files changed, 3 deletions(-) diff --git a/board/freescale/imx8mn_evk/lpddr4_timing_ld.c b/board/freescale/imx8mn_evk/lpddr4_timing_ld.c index 5faa0021a7..aa23c35094 100644 --- a/board/freescale/imx8mn_evk/lpddr4_timing_ld.c +++ b/board/freescale/imx8mn_evk/lpddr4_timing_ld.c @@ -799,7 +799,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0x54008, 0x61 }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x310 }, diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c index 9d069fc27a..8c5306d5d2 100755 --- a/board/freescale/imx8mp_evk/lpddr4_timing.c +++ b/board/freescale/imx8mp_evk/lpddr4_timing.c @@ -1298,7 +1298,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0x54008, 0x61 }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x310 }, @@ -1330,7 +1329,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0x54008, 0x61 }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x310 }, From 0d77b4522f061705e238b9116c9321ed9630b0b7 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Mar 2021 15:57:15 +0800 Subject: [PATCH 022/117] arch: mach-imx: imx8m: fix unique_id read error for imx8mp The value of Unique ID in uboot and kernel is different for iMX8MP: serial#=02e1444a0002aaff root@imx8mpevk:/sys/devices/soc0# cat soc_uid D699300002E1444A The reason is that Fuse Addresses of Unique ID of iMX8MP are 0x420 and 0x430. Reviewed-by: Ye Li Signed-off-by: Alice Guo Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 3f50014618..49bac8c1fa 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -120,6 +120,16 @@ struct ocotp_regs { } bank[0]; }; +#ifdef CONFIG_IMX8MP +struct fuse_bank0_regs { + u32 lock; + u32 rsvd0[7]; + u32 uid_low; + u32 rsvd1[3]; + u32 uid_high; + u32 rsvd2[3]; +}; +#else struct fuse_bank0_regs { u32 lock; u32 rsvd0[3]; @@ -128,6 +138,7 @@ struct fuse_bank0_regs { u32 uid_high; u32 rsvd2[7]; }; +#endif struct fuse_bank1_regs { u32 tester3; From ea2b26fb1280a1009e6a59872d5e61d83c06422a Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 19 Mar 2021 15:57:16 +0800 Subject: [PATCH 023/117] iMX8MQ: Recognize the B2 revision i.MX8MQ B2 is using same value in OCOTP_READ_FUSE_DATA like B1, so we have to check the ROM verision to distinguish the revision. As we have checked the B1 rev for sticky bits work around in secure boot. So it won't apply on B2. Signed-off-by: Ye Li Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx/cpu.h | 1 + arch/arm/mach-imx/imx8m/soc.c | 11 ++++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 28244d7671..ef090eb2f2 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -65,6 +65,7 @@ #define CHIP_REV_1_5 0x15 #define CHIP_REV_2_0 0x20 #define CHIP_REV_2_1 0x21 +#define CHIP_REV_2_2 0x22 #define CHIP_REV_2_5 0x25 #define CHIP_REV_3_0 0x30 diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index f322488c00..f3b9f2ddd6 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -410,7 +410,16 @@ u32 get_cpu_rev(void) * 0xff0055aa is magic number for B1. */ if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) { - reg = CHIP_REV_2_1; + /* + * B2 uses same DIGPROG and OCOTP_READ_FUSE_DATA value with B1, + * so have to check ROM to distinguish them + */ + rom_version = readl((void __iomem *)ROM_VERSION_B0); + rom_version &= 0xff; + if (rom_version == CHIP_REV_2_2) + reg = CHIP_REV_2_2; + else + reg = CHIP_REV_2_1; } else { rom_version = readl((void __iomem *)ROM_VERSION_A0); From 10867a0dcbffe2ac440ba75dc485857e95dbb0c5 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 19 Mar 2021 15:57:17 +0800 Subject: [PATCH 024/117] misc: ocotp: Update OCOTP driver for iMX8MQ B2 i.MX8MQ B2 also has fixed value in OCOTP_READ_FUSE_DATA register, so it does not support "fuse sense" command like B1. Signed-off-by: Ye Li Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/misc/mxc_ocotp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index 926c62c8a1..b1893a5c7e 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -335,7 +335,7 @@ int fuse_sense(u32 bank, u32 word, u32 *val) struct ocotp_regs *regs; int ret; - if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1)) { + if (is_imx8mq() && (soc_rev() >= CHIP_REV_2_1)) { printf("mxc_ocotp %s(): fuse sense is disabled\n", __func__); return -EPERM; } From 9e05cf0152cf833154abf77b72e7623a7e0b4ad7 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 19 Mar 2021 15:57:18 +0800 Subject: [PATCH 025/117] imx8mq_evk: Applying default LPDDR4 script for B2 Both i.MX8MQ B1 and B2 should use default LPDDR4 script, while B0 has another dedicated script. Signed-off-by: Ye Li Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- board/freescale/imx8mq_evk/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c index 82753585f2..e8e0efe485 100644 --- a/board/freescale/imx8mq_evk/spl.c +++ b/board/freescale/imx8mq_evk/spl.c @@ -36,7 +36,7 @@ extern struct dram_timing_info dram_timing_b0; static void spl_dram_init(void) { /* ddr init */ - if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1) + if (soc_rev() >= CHIP_REV_2_1) ddr_init(&dram_timing); else ddr_init(&dram_timing_b0); From 48ab215741435cbe92bed41f6b0c30e2de6276ec Mon Sep 17 00:00:00 2001 From: Peng Date: Thu, 25 Mar 2021 17:30:00 +0800 Subject: [PATCH 026/117] imx8mn: evk: update MAINTAINERS Add imx8mn_evk_defconfig to be maintained Typo fix Signed-off-by: Peng --- board/freescale/imx8mn_evk/MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/freescale/imx8mn_evk/MAINTAINERS b/board/freescale/imx8mn_evk/MAINTAINERS index 3b0653d3c8..6d110ccf22 100644 --- a/board/freescale/imx8mn_evk/MAINTAINERS +++ b/board/freescale/imx8mn_evk/MAINTAINERS @@ -1,6 +1,7 @@ -i.MX8MM EVK BOARD +i.MX8MN EVK BOARD M: Peng Fan S: Maintained F: board/freescale/imx8mn_evk/ F: include/configs/imx8mn_evk.h F: configs/imx8mn_ddr4_evk_defconfig +F: configs/imx8mn_evk_defconfig From ac3a16f8501e93efb8554df2dc79a96b00b6eea8 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 25 Mar 2021 17:30:01 +0800 Subject: [PATCH 027/117] imx8m: add regs used by CAAM Add regs used by CAAM Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 49bac8c1fa..b800da13a1 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -65,6 +65,16 @@ #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000 #define FEC_QUIRK_ENET_MAC +#define CAAM_ARB_BASE_ADDR (0x00100000) +#define CAAM_ARB_END_ADDR (0x00107FFF) +#define CAAM_IPS_BASE_ADDR (0x30900000) +#define CONFIG_SYS_FSL_SEC_OFFSET (0) +#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ + CONFIG_SYS_FSL_JR0_OFFSET) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #if !defined(__ASSEMBLY__) #include #include From 30e39ac7c937e07002e2868b23b679e6bb0f2a58 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 25 Mar 2021 17:30:02 +0800 Subject: [PATCH 028/117] imx: imx7 Support for Manufacturing Protection This code was originally developed by Raul Cardenas and modified to be applied in U-Boot imx_v2017.03. More information about the initial submission can be seen in the link below: https://lists.denx.de/pipermail/u-boot/2016-February/245273.html i.MX7D has an a protection feature for Manufacturing process. This feature uses asymmetric encryption to sign and verify authenticated software handled between parties. This command enables the use of such feature. The private key is unique and generated once per device. And it is stored in secure memory and only accessible by CAAM. Therefore, the public key generation and signature functions are the only functions available for the user. The manufacturing-protection authentication process can be used to authenticate the chip to the OEM's server. Command usage: Print the public key for the device. - mfgprot pubk Generates Signature over given data. - mfgprot sign Signed-off-by: Raul Ulises Cardenas Signed-off-by: Breno Lima Reviewed-by: Fabio Estevam Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/Kconfig | 9 ++ arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/cmd_mfgprot.c | 150 +++++++++++++++++++++++++++++ drivers/crypto/fsl/Makefile | 1 + drivers/crypto/fsl/desc.h | 1 + drivers/crypto/fsl/fsl_mfgprot.c | 160 +++++++++++++++++++++++++++++++ include/fsl_sec.h | 8 ++ 7 files changed, 330 insertions(+) create mode 100644 arch/arm/mach-imx/cmd_mfgprot.c create mode 100644 drivers/crypto/fsl/fsl_mfgprot.c diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 8f64e23195..6d40c7fc4b 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -99,6 +99,15 @@ config CMD_NANDBCB This is similar to kobs-ng, which is used in Linux as separate rootfs package. +config FSL_MFGPROT + bool "Support the 'mfgprot' command" + depends on IMX_HAB && ARCH_MX7 + help + This option enables the manufacturing protection command + which can be used has a protection feature for Manufacturing + process. With this tool is possible to authenticate the + chip to the OEM's server. + config NXP_BOARD_REVISION bool "Read NXP board revision from fuses" depends on ARCH_MX6 || ARCH_MX7 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index e6b4654cd3..25f910b36a 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -35,6 +35,7 @@ ifeq ($(SOC),$(filter $(SOC),mx7)) obj-y += cpu.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o +obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6 mx7)) obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c new file mode 100644 index 0000000000..03fc7014e1 --- /dev/null +++ b/arch/arm/mach-imx/cmd_mfgprot.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * These commands enable the use of the CAAM MPPubK-generation and MPSign + * functions in supported i.MX devices. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/** + * do_mfgprot() - Handle the "mfgprot" command-line command + * @cmdtp: Command data struct pointer + * @flag: Command flag + * @argc: Command-line argument count + * @argv: Array of command-line arguments + * + * Returns zero on success, CMD_RET_USAGE in case of misuse and negative + * on error. + */ +static int do_mfgprot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + u8 *m_ptr, *dgst_ptr, *c_ptr, *d_ptr, *dst_ptr; + char *pubk, *sign, *sel; + int m_size, i, ret; + u32 m_addr; + + pubk = "pubk"; + sign = "sign"; + sel = argv[1]; + + /* Enable HAB clock */ + u32 jr_size = 4; + u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c); + + if (out_jr_size != jr_size) { + hab_caam_clock_enable(1); + sec_init(); + } + + if (strcmp(sel, pubk) == 0) { + dst_ptr = malloc_cache_aligned(FSL_CAAM_MP_PUBK_BYTES); + if (!dst_ptr) + return -ENOMEM; + + ret = gen_mppubk(dst_ptr); + if (ret) { + free(dst_ptr); + return ret; + } + + /* Output results */ + puts("Public key:\n"); + for (i = 0; i < FSL_CAAM_MP_PUBK_BYTES; i++) + printf("%02X", (dst_ptr)[i]); + puts("\n"); + free(dst_ptr); + + } else if (strcmp(sel, sign) == 0) { + if (argc != 4) + return CMD_RET_USAGE; + + m_addr = simple_strtoul(argv[2], NULL, 16); + m_size = simple_strtoul(argv[3], NULL, 10); + m_ptr = map_physmem(m_addr, m_size, MAP_NOCACHE); + if (!m_ptr) + return -ENOMEM; + + dgst_ptr = malloc_cache_aligned(FSL_CAAM_MP_MES_DGST_BYTES); + if (!dgst_ptr) { + ret = -ENOMEM; + goto free_m; + } + + c_ptr = malloc_cache_aligned(FSL_CAAM_MP_PRVK_BYTES); + if (!c_ptr) { + ret = -ENOMEM; + goto free_dgst; + } + + d_ptr = malloc_cache_aligned(FSL_CAAM_MP_PRVK_BYTES); + if (!d_ptr) { + ret = -ENOMEM; + goto free_c; + } + + ret = sign_mppubk(m_ptr, m_size, dgst_ptr, c_ptr, d_ptr); + if (ret) + goto free_d; + + /* Output results */ + puts("Message: "); + for (i = 0; i < m_size; i++) + printf("%02X ", (m_ptr)[i]); + puts("\n"); + + puts("Message Representative Digest(SHA-256):\n"); + for (i = 0; i < FSL_CAAM_MP_MES_DGST_BYTES; i++) + printf("%02X", (dgst_ptr)[i]); + puts("\n"); + + puts("Signature:\n"); + puts("C:\n"); + for (i = 0; i < FSL_CAAM_MP_PRVK_BYTES; i++) + printf("%02X", (c_ptr)[i]); + puts("\n"); + + puts("d:\n"); + for (i = 0; i < FSL_CAAM_MP_PRVK_BYTES; i++) + printf("%02X", (d_ptr)[i]); + puts("\n"); +free_d: + free(d_ptr); +free_c: + free(c_ptr); +free_dgst: + free(dgst_ptr); +free_m: + unmap_sysmem(m_ptr); + + } else { + return CMD_RET_USAGE; + } + return ret; +} + +/***************************************************/ +static char mfgprot_help_text[] = + "Usage:\n" + "Print the public key for Manufacturing Protection\n" + "\tmfgprot pubk\n" + "Generates a Manufacturing Protection signature\n" + "\tmfgprot sign "; + +U_BOOT_CMD( + mfgprot, 4, 1, do_mfgprot, + "Manufacturing Protection\n", + mfgprot_help_text +); diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index a5e8d38e38..eb689c1b9f 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_CMD_BLOB) += fsl_blob.o obj-$(CONFIG_CMD_DEKBLOB) += fsl_blob.o obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o obj-$(CONFIG_FSL_CAAM_RNG) += rng.o +obj-$(CONFIG_FSL_MFGPROT) += fsl_mfgprot.o diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h index 3589e6ea02..9d1ae059a7 100644 --- a/drivers/crypto/fsl/desc.h +++ b/drivers/crypto/fsl/desc.h @@ -740,6 +740,7 @@ struct __packed pdb_mp_sign { }; #define PDB_MP_CSEL_SHIFT 17 +#define PDB_MP_CSEL_WIDTH 4 #define PDB_MP_CSEL_P256 0x3 << PDB_MP_CSEL_SHIFT /* P-256 */ #define PDB_MP_CSEL_P384 0x4 << PDB_MP_CSEL_SHIFT /* P-384 */ #define PDB_MP_CSEL_P521 0x5 << PDB_MP_CSEL_SHIFT /* P-521 */ diff --git a/drivers/crypto/fsl/fsl_mfgprot.c b/drivers/crypto/fsl/fsl_mfgprot.c new file mode 100644 index 0000000000..fa874e7a9b --- /dev/null +++ b/drivers/crypto/fsl/fsl_mfgprot.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#include +#include +#include +#include +#include "desc.h" +#include "desc_constr.h" +#include "jobdesc.h" +#include "jr.h" + +/* Size of MFG descriptor */ +#define MFG_PUBK_DSC_WORDS 4 +#define MFG_SIGN_DSC_WORDS 8 + +static void mfg_build_sign_dsc(u32 *dsc_ptr, const u8 *m, int size, + u8 *dgst, u8 *c, u8 *d) +{ + u32 *dsc = dsc_ptr; + struct pdb_mp_sign *pdb; + + init_job_desc_pdb(dsc, 0, sizeof(struct pdb_mp_sign)); + + pdb = (struct pdb_mp_sign *)desc_pdb(dsc); + + /* Curve */ + pdb->pdb_hdr = (PDB_MP_CSEL_P256); + + /* Message Pointer */ + pdb_add_ptr(&pdb->dma_addr_msg, virt_to_phys((void *)m)); + + /* mes-resp Pointer */ + pdb_add_ptr(&pdb->dma_addr_hash, virt_to_phys((void *)dgst)); + + /* C Pointer */ + pdb_add_ptr(&pdb->dma_addr_c_sig, virt_to_phys((void *)c)); + + /* d Pointer */ + pdb_add_ptr(&pdb->dma_addr_d_sig, virt_to_phys((void *)d)); + + /* Message Size */ + pdb->img_size = size; + + /* MP PubK generate key command */ + append_cmd(dsc, (CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | + OP_PCLID_MP_SIGN)); +} + +static void mfg_build_pubk_dsc(u32 *dsc_ptr, u8 *dst) +{ + u32 *dsc = dsc_ptr; + struct pdb_mp_pub_k *pdb; + + init_job_desc_pdb(dsc, 0, sizeof(struct pdb_mp_pub_k)); + + pdb = (struct pdb_mp_pub_k *)desc_pdb(dsc); + + /* Curve */ + pdb->pdb_hdr = (PDB_MP_CSEL_P256); + + /* Message Pointer */ + pdb_add_ptr(&pdb->dma_pkey, virt_to_phys((void *)dst)); + + /* MP Sign key command */ + append_cmd(dsc, (CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | + OP_PCLID_MP_PUB_KEY)); +} + +int gen_mppubk(u8 *dst) +{ + int size, ret; + u32 *dsc; + + /* Job Descriptor initialization */ + dsc = memalign(ARCH_DMA_MINALIGN, + sizeof(uint32_t) * MFG_PUBK_DSC_WORDS); + if (!dsc) { + debug("Not enough memory for descriptor allocation\n"); + return -ENOMEM; + } + + mfg_build_pubk_dsc(dsc, dst); + + size = roundup(sizeof(uint32_t) * MFG_PUBK_DSC_WORDS, + ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dsc, (unsigned long)dsc + size); + + size = roundup(FSL_CAAM_MP_PUBK_BYTES, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dst, (unsigned long)dst + size); + + /* Execute Job Descriptor */ + puts("\nGenerating Manufacturing Protection Public Key\n"); + + ret = run_descriptor_jr(dsc); + if (ret) { + debug("Error in public key generation %d\n", ret); + goto err; + } + + size = roundup(FSL_CAAM_MP_PUBK_BYTES, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)dst, (unsigned long)dst + size); +err: + free(dsc); + return ret; +} + +int sign_mppubk(const u8 *m, int data_size, u8 *dgst, u8 *c, u8 *d) +{ + int size, ret; + u32 *dsc; + + /* Job Descriptor initialization */ + dsc = memalign(ARCH_DMA_MINALIGN, + sizeof(uint32_t) * MFG_SIGN_DSC_WORDS); + if (!dsc) { + debug("Not enough memory for descriptor allocation\n"); + return -ENOMEM; + } + + mfg_build_sign_dsc(dsc, m, data_size, dgst, c, d); + + size = roundup(sizeof(uint32_t) * MFG_SIGN_DSC_WORDS, + ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dsc, (unsigned long)dsc + size); + + size = roundup(data_size, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)m, (unsigned long)m + size); + + size = roundup(FSL_CAAM_MP_MES_DGST_BYTES, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dgst, (unsigned long)dgst + size); + + size = roundup(FSL_CAAM_MP_PRVK_BYTES, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)c, (unsigned long)c + size); + flush_dcache_range((unsigned long)d, (unsigned long)d + size); + + /* Execute Job Descriptor */ + puts("\nSigning message with Manufacturing Protection Public Key\n"); + + ret = run_descriptor_jr(dsc); + if (ret) { + debug("Error in public key generation %d\n", ret); + goto err; + } + + size = roundup(FSL_CAAM_MP_MES_DGST_BYTES, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)dgst, + (unsigned long)dgst + size); + + size = roundup(FSL_CAAM_MP_PRVK_BYTES, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)c, (unsigned long)c + size); + invalidate_dcache_range((unsigned long)d, (unsigned long)d + size); + +err: + free(dsc); + return ret; +} diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 1c6f1eb23e..40f1c5b10d 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -340,6 +340,10 @@ struct sg_entry { #endif +#define FSL_CAAM_MP_PUBK_BYTES 64 +#define FSL_CAAM_MP_PRVK_BYTES 32 +#define FSL_CAAM_MP_MES_DGST_BYTES 32 + /* blob_dek: * Encapsulates the src in a secure blob and stores it dst * @src: reference to the plaintext @@ -349,6 +353,10 @@ struct sg_entry { */ int blob_dek(const u8 *src, u8 *dst, u8 len); +int gen_mppubk(u8 *dst); + +int sign_mppubk(const u8 *m, int data_size, u8 *dgst, u8 *c, u8 *d); + #if defined(CONFIG_ARCH_C29X) int sec_init_idx(uint8_t); #endif From 8c497e148c0676977a1ef392595fd5b790e59ee4 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 25 Mar 2021 17:30:03 +0800 Subject: [PATCH 029/117] imx: Avoid hardcoded output ring size register offset (ORSR) The CAAM output ring size register offset is currently defined in fsl_sec.h as FSL_CAAM_ORSR_JRa_OFFSET, use this definition to avoid hardcoded value in i.MX common code. Signed-off-by: Breno Lima Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/cmd_dek.c | 3 ++- arch/arm/mach-imx/cmd_mfgprot.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 49dd473af7..5bf92cbecf 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -28,7 +28,8 @@ static int blob_encap_dek(const u8 *src, u8 *dst, u32 len) int ret = 0; u32 jr_size = 4; - u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c); + u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + + FSL_CAAM_ORSR_JRa_OFFSET); if (out_jr_size != jr_size) { hab_caam_clock_enable(1); sec_init(); diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c index 03fc7014e1..6e567027c0 100644 --- a/arch/arm/mach-imx/cmd_mfgprot.c +++ b/arch/arm/mach-imx/cmd_mfgprot.c @@ -42,7 +42,8 @@ static int do_mfgprot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) /* Enable HAB clock */ u32 jr_size = 4; - u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c); + u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + + FSL_CAAM_ORSR_JRa_OFFSET); if (out_jr_size != jr_size) { hab_caam_clock_enable(1); From 6d7b27033726fe32583ced72f144c288699eed04 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 25 Mar 2021 17:30:04 +0800 Subject: [PATCH 030/117] imx: Ensure CAAM clock is enabled prior getting out_jr_size Prior calling sec_in32() we have to ensure CAAM clock is enabled, the function sec_in32() is reading CAAM registers and if CAAM clock is disabled the system will hang. Signed-off-by: Breno Lima Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/cmd_dek.c | 6 +++--- arch/arm/mach-imx/cmd_mfgprot.c | 7 ++++--- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 5bf92cbecf..9a965576c7 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -28,12 +28,12 @@ static int blob_encap_dek(const u8 *src, u8 *dst, u32 len) int ret = 0; u32 jr_size = 4; + hab_caam_clock_enable(1); + u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + FSL_CAAM_ORSR_JRa_OFFSET); - if (out_jr_size != jr_size) { - hab_caam_clock_enable(1); + if (out_jr_size != jr_size) sec_init(); - } if (!((len == 128) | (len == 192) | (len == 256))) { debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n"); diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c index 6e567027c0..dd506a16e8 100644 --- a/arch/arm/mach-imx/cmd_mfgprot.c +++ b/arch/arm/mach-imx/cmd_mfgprot.c @@ -42,13 +42,14 @@ static int do_mfgprot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) /* Enable HAB clock */ u32 jr_size = 4; + + hab_caam_clock_enable(1); + u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + FSL_CAAM_ORSR_JRa_OFFSET); - if (out_jr_size != jr_size) { - hab_caam_clock_enable(1); + if (out_jr_size != jr_size) sec_init(); - } if (strcmp(sel, pubk) == 0) { dst_ptr = malloc_cache_aligned(FSL_CAAM_MP_PUBK_BYTES); From 55086e196eaca9403a636ea7079e7135bddbbece Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 25 Mar 2021 17:30:05 +0800 Subject: [PATCH 031/117] imx: Avoid hardcoded Job Ring Max size Prior instantiating RNG we have to ensure if the CAAM job rings are available. Avoid hardcoded job ring max size and use the definition at fsl_sec.h Signed-off-by: Breno Lima Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/cmd_dek.c | 3 +-- arch/arm/mach-imx/cmd_mfgprot.c | 4 +--- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 9a965576c7..bd380429c0 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -26,13 +26,12 @@ static int blob_encap_dek(const u8 *src, u8 *dst, u32 len) { int ret = 0; - u32 jr_size = 4; hab_caam_clock_enable(1); u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + FSL_CAAM_ORSR_JRa_OFFSET); - if (out_jr_size != jr_size) + if (out_jr_size != FSL_CAAM_MAX_JR_SIZE) sec_init(); if (!((len == 128) | (len == 192) | (len == 256))) { diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c index dd506a16e8..1430f61909 100644 --- a/arch/arm/mach-imx/cmd_mfgprot.c +++ b/arch/arm/mach-imx/cmd_mfgprot.c @@ -41,14 +41,12 @@ static int do_mfgprot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) sel = argv[1]; /* Enable HAB clock */ - u32 jr_size = 4; - hab_caam_clock_enable(1); u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + FSL_CAAM_ORSR_JRa_OFFSET); - if (out_jr_size != jr_size) + if (out_jr_size != FSL_CAAM_MAX_JR_SIZE) sec_init(); if (strcmp(sel, pubk) == 0) { From c428ca80c298df55db242571d868dae7b475ccb5 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 25 Mar 2021 17:30:06 +0800 Subject: [PATCH 032/117] imx: hab: Add function to authenticate kernel image When loading kernel image, the image size is parsed from header, so it does not include the CSF and IVT. Add back the authenticate_image function to wrap the imx_hab_authenticate_image with calculating IVT offset and full image size. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/hab.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index d0757d8b66..66ac440349 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -698,3 +698,15 @@ hab_authentication_exit: return result; } + +int authenticate_image(u32 ddr_start, u32 raw_image_size) +{ + u32 ivt_offset; + size_t bytes; + + ivt_offset = (raw_image_size + ALIGN_SIZE - 1) & + ~(ALIGN_SIZE - 1); + bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE; + + return imx_hab_authenticate_image(ddr_start, bytes, ivt_offset); +} From 507da978fa0a09874b5b154bec5521688d9660d8 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 25 Mar 2021 17:30:07 +0800 Subject: [PATCH 033/117] imx: HAB: Update hab codes to support ARM64 and i.MX8M There are some changes to support ARM64 i.MX8M platform in this patches: 1. The hab_rvt base and function vectors are different as i.MX6/7 2. Need to bypass an workaround for i.MX6 to fix problem in MMU. 3. The x18 register needed save & restore before calling any HAB API. According to ARM procedure call spec, the x18 is caller saved when it is used as temporary register. So calling HAB API may scratch this register, and cause crash once accessing the gd pointer. On ARMv7, the r9 is callee saved when it is used as variable register. So no need to save & restore it. 4. Add SEC_CONFIG fuse for iMX8M When current EL is not EL3, the direct calling to HAB will fail because CAAM/SNVS can't initialize at non-secure mode. In this case, we use SIP call to run the HAB in ATF. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/mach-imx/hab.h | 14 ++ arch/arm/mach-imx/hab.c | 229 +++++++++++++++++++++++++--- 2 files changed, 218 insertions(+), 25 deletions(-) diff --git a/arch/arm/include/asm/mach-imx/hab.h b/arch/arm/include/asm/mach-imx/hab.h index d8bd77075a..c4393ef443 100644 --- a/arch/arm/include/asm/mach-imx/hab.h +++ b/arch/arm/include/asm/mach-imx/hab.h @@ -165,6 +165,18 @@ typedef void hapi_clock_init_t(void); #define HAB_ENG_RTL 0x77 /* RTL simulation engine */ #define HAB_ENG_SW 0xff /* Software engine */ +#ifdef CONFIG_ARM64 +#define HAB_RVT_BASE 0x00000880 + +#define HAB_RVT_ENTRY (*(ulong *)(HAB_RVT_BASE + 0x08)) +#define HAB_RVT_EXIT (*(ulong *)(HAB_RVT_BASE + 0x10)) +#define HAB_RVT_CHECK_TARGET (*(ulong *)(HAB_RVT_BASE + 0x18)) +#define HAB_RVT_AUTHENTICATE_IMAGE (*(ulong *)(HAB_RVT_BASE + 0x20)) +#define HAB_RVT_REPORT_EVENT (*(ulong *)(HAB_RVT_BASE + 0x40)) +#define HAB_RVT_REPORT_STATUS (*(ulong *)(HAB_RVT_BASE + 0x48)) +#define HAB_RVT_FAILSAFE (*(ulong *)(HAB_RVT_BASE + 0x50)) +#else + #ifdef CONFIG_ROM_UNIFIED_SECTIONS #define HAB_RVT_BASE 0x00000100 #else @@ -186,6 +198,8 @@ typedef void hapi_clock_init_t(void); #define HAB_RVT_REPORT_STATUS (*(uint32_t *)(HAB_RVT_BASE + 0x24)) #define HAB_RVT_FAILSAFE (*(uint32_t *)(HAB_RVT_BASE + 0x28)) +#endif /*CONFIG_ARM64*/ + #define HAB_CID_ROM 0 /**< ROM Caller ID */ #define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/ diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 66ac440349..9ebdbe6ac3 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -10,10 +10,14 @@ #include #include #include +#include #include #include #include #include +#include + +DECLARE_GLOBAL_DATA_PTR; #define ALIGN_SIZE 0x1000 #define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8 @@ -21,7 +25,7 @@ #define MX6SL_PU_IROM_MMU_EN_VAR 0x00901c60 #define IS_HAB_ENABLED_BIT \ (is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \ - (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)) + ((is_soc_type(MXC_SOC_MX7) || is_soc_type(MXC_SOC_IMX8M)) ? 0x2000000 : 0x2)) static int ivt_header_error(const char *err_str, struct ivt_header *ivt_hdr) { @@ -48,6 +52,194 @@ static int verify_ivt_header(struct ivt_header *ivt_hdr) return result; } +#ifdef CONFIG_ARM64 +#define FSL_SIP_HAB 0xC2000007 +#define FSL_SIP_HAB_AUTHENTICATE 0x00 +#define FSL_SIP_HAB_ENTRY 0x01 +#define FSL_SIP_HAB_EXIT 0x02 +#define FSL_SIP_HAB_REPORT_EVENT 0x03 +#define FSL_SIP_HAB_REPORT_STATUS 0x04 +#define FSL_SIP_HAB_FAILSAFE 0x05 +#define FSL_SIP_HAB_CHECK_TARGET 0x06 +static volatile gd_t *gd_save; +#endif + +static inline void save_gd(void) +{ +#ifdef CONFIG_ARM64 + gd_save = gd; +#endif +} + +static inline void restore_gd(void) +{ +#ifdef CONFIG_ARM64 + /* + * Make will already error that reserving x18 is not supported at the + * time of writing, clang: error: unknown argument: '-ffixed-x18' + */ + __asm__ volatile("mov x18, %0\n" : : "r" (gd_save)); +#endif +} + +enum hab_status hab_rvt_report_event(enum hab_status status, u32 index, + u8 *event, size_t *bytes) +{ + enum hab_status ret; + hab_rvt_report_event_t *hab_rvt_report_event_func; + struct arm_smccc_res res __maybe_unused; + + hab_rvt_report_event_func = (hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT; +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_REPORT_EVENT, (unsigned long)index, + (unsigned long)event, (unsigned long)bytes, 0, 0, 0, &res); + return (enum hab_status)res.a0; + } +#endif + + save_gd(); + ret = hab_rvt_report_event_func(status, index, event, bytes); + restore_gd(); + + return ret; + +} + +enum hab_status hab_rvt_report_status(enum hab_config *config, enum hab_state *state) +{ + enum hab_status ret; + hab_rvt_report_status_t *hab_rvt_report_status_func; + struct arm_smccc_res res __maybe_unused; + + hab_rvt_report_status_func = (hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS; +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_REPORT_STATUS, (unsigned long)config, + (unsigned long)state, 0, 0, 0, 0, &res); + return (enum hab_status)res.a0; + } +#endif + + save_gd(); + ret = hab_rvt_report_status_func(config, state); + restore_gd(); + + return ret; +} + +enum hab_status hab_rvt_entry(void) +{ + enum hab_status ret; + hab_rvt_entry_t *hab_rvt_entry_func; + struct arm_smccc_res res __maybe_unused; + + hab_rvt_entry_func = (hab_rvt_entry_t *)HAB_RVT_ENTRY; +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_ENTRY, 0, 0, 0, 0, 0, 0, &res); + return (enum hab_status)res.a0; + } +#endif + + save_gd(); + ret = hab_rvt_entry_func(); + restore_gd(); + + return ret; +} + +enum hab_status hab_rvt_exit(void) +{ + enum hab_status ret; + hab_rvt_exit_t *hab_rvt_exit_func; + struct arm_smccc_res res __maybe_unused; + + hab_rvt_exit_func = (hab_rvt_exit_t *)HAB_RVT_EXIT; +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_EXIT, 0, 0, 0, 0, 0, 0, &res); + return (enum hab_status)res.a0; + } +#endif + + save_gd(); + ret = hab_rvt_exit_func(); + restore_gd(); + + return ret; +} + +void hab_rvt_failsafe(void) +{ + hab_rvt_failsafe_t *hab_rvt_failsafe_func; + + hab_rvt_failsafe_func = (hab_rvt_failsafe_t *)HAB_RVT_FAILSAFE; +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_FAILSAFE, 0, 0, 0, 0, 0, 0, NULL); + return; + } +#endif + + save_gd(); + hab_rvt_failsafe_func(); + restore_gd(); +} + +enum hab_status hab_rvt_check_target(enum hab_target type, const void *start, + size_t bytes) +{ + enum hab_status ret; + hab_rvt_check_target_t *hab_rvt_check_target_func; + struct arm_smccc_res res __maybe_unused; + + hab_rvt_check_target_func = (hab_rvt_check_target_t *)HAB_RVT_CHECK_TARGET; +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_CHECK_TARGET, (unsigned long)type, + (unsigned long)start, (unsigned long)bytes, 0, 0, 0, &res); + return (enum hab_status)res.a0; + } +#endif + + save_gd(); + ret = hab_rvt_check_target_func(type, start, bytes); + restore_gd(); + + return ret; +} + +void *hab_rvt_authenticate_image(uint8_t cid, ptrdiff_t ivt_offset, + void **start, size_t *bytes, hab_loader_callback_f_t loader) +{ + void *ret; + hab_rvt_authenticate_image_t *hab_rvt_authenticate_image_func; + struct arm_smccc_res res __maybe_unused; + + hab_rvt_authenticate_image_func = (hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE; +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_AUTHENTICATE, (unsigned long)ivt_offset, + (unsigned long)start, (unsigned long)bytes, 0, 0, 0, &res); + return (void *)res.a0; + } +#endif + + save_gd(); + ret = hab_rvt_authenticate_image_func(cid, ivt_offset, start, bytes, loader); + restore_gd(); + + return ret; +} + #if !defined(CONFIG_SPL_BUILD) #define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */ @@ -253,12 +445,6 @@ static int get_hab_status(void) size_t bytes = sizeof(event_data); /* Event size in bytes */ enum hab_config config = 0; enum hab_state state = 0; - hab_rvt_report_event_t *hab_rvt_report_event; - hab_rvt_report_status_t *hab_rvt_report_status; - - hab_rvt_report_event = (hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT; - hab_rvt_report_status = - (hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS; if (imx_hab_is_enabled()) puts("\nSecure boot enabled\n"); @@ -493,7 +679,7 @@ static bool csf_is_valid(struct ivt *ivt, ulong start_addr, size_t bytes) return false; } - csf_hdr = (u8 *)ivt->csf; + csf_hdr = (u8 *)(ulong)ivt->csf; /* Verify if CSF Header exist */ if (*csf_hdr != HAB_CMD_HDR) { @@ -561,25 +747,15 @@ bool imx_hab_is_enabled(void) int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, uint32_t ivt_offset) { - uint32_t load_addr = 0; + ulong load_addr = 0; size_t bytes; - uint32_t ivt_addr = 0; + ulong ivt_addr = 0; int result = 1; ulong start; - hab_rvt_authenticate_image_t *hab_rvt_authenticate_image; - hab_rvt_entry_t *hab_rvt_entry; - hab_rvt_exit_t *hab_rvt_exit; - hab_rvt_check_target_t *hab_rvt_check_target; struct ivt *ivt; struct ivt_header *ivt_hdr; enum hab_status status; - hab_rvt_authenticate_image = - (hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE; - hab_rvt_entry = (hab_rvt_entry_t *)HAB_RVT_ENTRY; - hab_rvt_exit = (hab_rvt_exit_t *)HAB_RVT_EXIT; - hab_rvt_check_target = (hab_rvt_check_target_t *)HAB_RVT_CHECK_TARGET; - if (!imx_hab_is_enabled()) { puts("hab fuse not enabled\n"); return 0; @@ -591,7 +767,7 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, hab_caam_clock_enable(1); /* Calculate IVT address header */ - ivt_addr = ddr_start + ivt_offset; + ivt_addr = (ulong) (ddr_start + ivt_offset); ivt = (struct ivt *)ivt_addr; ivt_hdr = &ivt->hdr; @@ -601,7 +777,7 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, /* Verify IVT body */ if (ivt->self != ivt_addr) { - printf("ivt->self 0x%08x pointer is 0x%08x\n", + printf("ivt->self 0x%08x pointer is 0x%08lx\n", ivt->self, ivt_addr); goto hab_authentication_exit; } @@ -624,9 +800,9 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, goto hab_exit_failure_print_status; } - status = hab_rvt_check_target(HAB_TGT_MEMORY, (void *)ddr_start, bytes); + status = hab_rvt_check_target(HAB_TGT_MEMORY, (void *)(ulong)ddr_start, bytes); if (status != HAB_SUCCESS) { - printf("HAB check target 0x%08x-0x%08x fail\n", + printf("HAB check target 0x%08x-0x%08lx fail\n", ddr_start, ddr_start + bytes); goto hab_exit_failure_print_status; } @@ -649,6 +825,8 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, printf("\tstart = 0x%08lx\n", start); printf("\tbytes = 0x%x\n", bytes); #endif + +#ifndef CONFIG_ARM64 /* * If the MMU is enabled, we have to notify the ROM * code, or it won't flush the caches when needed. @@ -676,8 +854,9 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, writel(1, MX6SL_PU_IROM_MMU_EN_VAR); } } +#endif - load_addr = (uint32_t)hab_rvt_authenticate_image( + load_addr = (ulong)hab_rvt_authenticate_image( HAB_CID_UBOOT, ivt_offset, (void **)&start, (size_t *)&bytes, NULL); From fe8acf556c3f6e83efb0836c31371d1b78289464 Mon Sep 17 00:00:00 2001 From: Utkarsh Gupta Date: Thu, 25 Mar 2021 17:30:08 +0800 Subject: [PATCH 034/117] imx: HAB: Validate IVT before authenticating image Calling csf_is_valid() with an un-signed image may lead to data abort as the CSF pointer could be pointing to a garbage address when accessed in HAB_HDR_LEN(*(const struct hab_hdr *)(ulong)ivt_initial->csf). Authenticate image from DDR location 0x80800000... Check CSF for Write Data command before authenticating image data abort pc : [] lr : [] reloc pc : [<8780294c>] lr : [<87802910>] sp : fdf45dc8 ip : 00000214 fp : 00000000 r10: fffb6170 r9 : fdf4fec0 r8 : 00722020 r7 : 80f20000 r6 : 80800000 r5 : 80800000 r4 : 00720000 r3 : 17a5aca3 r2 : 00000000 r1 : 80f2201f r0 : 00000019 Flags: NzcV IRQs off FIQs off Mode SVC_32 Resetting CPU ... resetting ... To avoid such errors during authentication process, validate IVT structure by calling validate_ivt function which checks the following values in an IVT: IVT_HEADER = 0x4X2000D1 ENTRY != 0x0 RES1 = 0x0 DCD = 0x0 /* Recommended */ SELF != 0x0 /* Absoulute address of IVT */ CSF != 0x0 RES2 = 0x0 This commit also checks if Image's start address is 4 byte aligned. commit "0088d127 MLK-14945 HAB: Check if IVT valid before authenticating image" removed as this patch addresses the issue. Signed-off-by: Utkarsh Gupta Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/hab.c | 59 ++++++++++++++++++++++++++++++----------- 1 file changed, 43 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 9ebdbe6ac3..f2d5f744e8 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -728,6 +728,48 @@ static bool csf_is_valid(struct ivt *ivt, ulong start_addr, size_t bytes) return true; } +/* + * Validate IVT structure of the image being authenticated + */ +static int validate_ivt(struct ivt *ivt_initial) +{ + struct ivt_header *ivt_hdr = &ivt_initial->hdr; + + if ((ulong)ivt_initial & 0x3) { + puts("Error: Image's start address is not 4 byte aligned\n"); + return 0; + } + + /* Check IVT fields before allowing authentication */ + if ((!verify_ivt_header(ivt_hdr)) && \ + (ivt_initial->entry != 0x0) && \ + (ivt_initial->reserved1 == 0x0) && \ + (ivt_initial->self == \ + (uint32_t)((ulong)ivt_initial & 0xffffffff)) && \ + (ivt_initial->csf != 0x0) && \ + (ivt_initial->reserved2 == 0x0)) { + /* Report boot failure if DCD pointer is found in IVT */ + if (ivt_initial->dcd != 0x0) + puts("Error: DCD pointer must be 0\n"); + else + return 1; + } + + puts("Error: Invalid IVT structure\n"); + debug("\nAllowed IVT structure:\n"); + debug("IVT HDR = 0x4X2000D1\n"); + debug("IVT ENTRY = 0xXXXXXXXX\n"); + debug("IVT RSV1 = 0x0\n"); + debug("IVT DCD = 0x0\n"); /* Recommended */ + debug("IVT BOOT_DATA = 0xXXXXXXXX\n"); /* Commonly 0x0 */ + debug("IVT SELF = 0xXXXXXXXX\n"); /* = ddr_start + ivt_offset */ + debug("IVT CSF = 0xXXXXXXXX\n"); + debug("IVT RSV2 = 0x0\n"); + + /* Invalid IVT structure */ + return 0; +} + bool imx_hab_is_enabled(void) { struct imx_sec_config_fuse_t *fuse = @@ -753,7 +795,6 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, int result = 1; ulong start; struct ivt *ivt; - struct ivt_header *ivt_hdr; enum hab_status status; if (!imx_hab_is_enabled()) { @@ -769,25 +810,11 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, /* Calculate IVT address header */ ivt_addr = (ulong) (ddr_start + ivt_offset); ivt = (struct ivt *)ivt_addr; - ivt_hdr = &ivt->hdr; /* Verify IVT header bugging out on error */ - if (verify_ivt_header(ivt_hdr)) + if (!validate_ivt(ivt)) goto hab_authentication_exit; - /* Verify IVT body */ - if (ivt->self != ivt_addr) { - printf("ivt->self 0x%08x pointer is 0x%08lx\n", - ivt->self, ivt_addr); - goto hab_authentication_exit; - } - - /* Verify if IVT DCD pointer is NULL */ - if (ivt->dcd) { - puts("Error: DCD pointer must be NULL\n"); - goto hab_authentication_exit; - } - start = ddr_start; bytes = image_size; From 1dc295148a93bc5b856b8b964079b54ea7f29514 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 25 Mar 2021 17:30:09 +0800 Subject: [PATCH 035/117] hab: Change calling to ROM API failsafe Modify to use hab_rvt_failsafe function for failsafe ROM API, not directly call its ROM address. This function will wrap the sip call for iMX8M platforms. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/hab.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index f2d5f744e8..bd00d4a458 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -539,14 +539,11 @@ static int do_authenticate_image(struct cmd_tbl *cmdtp, int flag, int argc, static int do_hab_failsafe(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - hab_rvt_failsafe_t *hab_rvt_failsafe; - if (argc != 1) { cmd_usage(cmdtp); return 1; } - hab_rvt_failsafe = (hab_rvt_failsafe_t *)HAB_RVT_FAILSAFE; hab_rvt_failsafe(); return 0; From 1d756add3c478f3fe79ed36aa86b2447949879b3 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 25 Mar 2021 17:30:10 +0800 Subject: [PATCH 036/117] imx: hab: Enable hab.c to authenticate additional images in open configuration Currently it's not possible to authenticate additional boot images in HAB open configuration. The hab.c code is checking if the SEC_CONFIG[1] fuse is programmed prior to calling the hab_authenticate_image() API function. Users cannot check if their additional boot images has been correctly signed prior to closing their device. Enable hab.c to authenticate additional boot images in open mode so HAB events can be retrieved through get_hab_status() function. Signed-off-by: Breno Lima Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/hab.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index bd00d4a458..01ddfab699 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -794,10 +794,8 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, struct ivt *ivt; enum hab_status status; - if (!imx_hab_is_enabled()) { + if (!imx_hab_is_enabled()) puts("hab fuse not enabled\n"); - return 0; - } printf("\nAuthenticate image from DDR location 0x%x...\n", ddr_start); @@ -896,7 +894,7 @@ hab_exit_failure_print_status: hab_authentication_exit: - if (load_addr != 0) + if (load_addr != 0 || !imx_hab_is_enabled()) result = 0; return result; From cd8355664db363768b672f9a362044e2db9bd86c Mon Sep 17 00:00:00 2001 From: Utkarsh Gupta Date: Thu, 25 Mar 2021 17:30:11 +0800 Subject: [PATCH 037/117] imx: hab: Display All HAB events via hab_status command Add ability for hab_status command to show All HAB events and not just HAB failure events Signed-off-by: Utkarsh Gupta Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/hab.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 01ddfab699..264e148ba6 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -456,8 +456,8 @@ static int get_hab_status(void) printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n", config, state); - /* Display HAB Error events */ - while (hab_rvt_report_event(HAB_FAILURE, index, event_data, + /* Display HAB events */ + while (hab_rvt_report_event(HAB_STS_ANY, index, event_data, &bytes) == HAB_SUCCESS) { puts("\n"); printf("--------- HAB Event %d -----------------\n", From f217470b392806be340e9c03d46e98bb29d7caec Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 25 Mar 2021 17:30:12 +0800 Subject: [PATCH 038/117] imx: hab: Check if IVT header is HABv4 The HABv4 implementation in ROM checks if HAB major version in IVT header is 4.x. The current implementation in hab.c code is only validating HAB v4.0 and HAB v4.1 and may be incompatible with newer HABv4 versions. Modify verify_ivt_header() function to align with HABv4 implementation in ROM code. Signed-off-by: Breno Lima Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/mach-imx/hab.h | 2 -- arch/arm/mach-imx/hab.c | 3 +-- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm/include/asm/mach-imx/hab.h b/arch/arm/include/asm/mach-imx/hab.h index c4393ef443..62218818f9 100644 --- a/arch/arm/include/asm/mach-imx/hab.h +++ b/arch/arm/include/asm/mach-imx/hab.h @@ -18,8 +18,6 @@ */ #define IVT_HEADER_MAGIC 0xD1 #define IVT_TOTAL_LENGTH 0x20 -#define IVT_HEADER_V1 0x40 -#define IVT_HEADER_V2 0x41 struct __packed ivt_header { uint8_t magic; diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 264e148ba6..5f46df0f8b 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -45,8 +45,7 @@ static int verify_ivt_header(struct ivt_header *ivt_hdr) if (be16_to_cpu(ivt_hdr->length) != IVT_TOTAL_LENGTH) result = ivt_header_error("bad length", ivt_hdr); - if (ivt_hdr->version != IVT_HEADER_V1 && - ivt_hdr->version != IVT_HEADER_V2) + if ((ivt_hdr->version & HAB_MAJ_MASK) != HAB_MAJ_VER) result = ivt_header_error("bad version", ivt_hdr); return result; From 58f75efeaf30c786c26fade79d127c988b813751 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 25 Mar 2021 17:30:13 +0800 Subject: [PATCH 039/117] mx7ulp: hab: Add hab_status command for HABv4 M4 boot When booting in low power or dual boot modes the M4 binary is authenticated by the M4 ROM code. Add an option in hab_status command so users can retrieve M4 HAB failure and warning events. => hab_status m4 Secure boot disabled HAB Configuration: 0xf0, HAB State: 0x66 No HAB Events Found! Add command documentation in mx6_mx7_secure_boot.txt guide. As HAB M4 API cannot be called from A7 core the code is parsing the M4 HAB persistent memory region. The HAB persistent memory stores HAB events, public keys and others HAB related information. The HAB persistent memory region addresses and sizes can be found in AN12263 "HABv4 RVT Guidelines and Recommendations". Reviewed-by: Utkarsh Gupta Reviewed-by: Ye Li Signed-off-by: Breno Lima Signed-off-by: Peng Fan --- arch/arm/include/asm/mach-imx/hab.h | 15 +++ arch/arm/mach-imx/hab.c | 99 ++++++++++++++++++++ doc/imx/habv4/guides/mx6_mx7_secure_boot.txt | 25 +++++ 3 files changed, 139 insertions(+) diff --git a/arch/arm/include/asm/mach-imx/hab.h b/arch/arm/include/asm/mach-imx/hab.h index 62218818f9..1085c37828 100644 --- a/arch/arm/include/asm/mach-imx/hab.h +++ b/arch/arm/include/asm/mach-imx/hab.h @@ -42,6 +42,15 @@ struct __packed hab_hdr { u8 par; /* Parameters field */ }; +/* Default event structure */ +struct __packed evt_def { + struct hab_hdr hdr; /* Header */ + uint32_t sts; /* Status */ + uint32_t ctx; /* Default context */ + uint8_t *data; /* Default data location */ + size_t bytes; /* Size of default data */ +}; + /* -------- start of HAB API updates ------------*/ /* The following are taken from HAB4 SIS */ @@ -211,6 +220,12 @@ typedef void hapi_clock_init_t(void); #define IVT_SIZE 0x20 #define CSF_PAD_SIZE 0x2000 +#define HAB_TAG_EVT 0xDB +#define HAB_TAG_EVT_DEF 0x0C + +#define HAB_MAJ_VER 0x40 +#define HAB_MAJ_MASK 0xF0 + /* ----------- end of HAB API updates ------------*/ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 5f46df0f8b..469ef0fd1c 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -27,6 +27,12 @@ DECLARE_GLOBAL_DATA_PTR; (is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \ ((is_soc_type(MXC_SOC_MX7) || is_soc_type(MXC_SOC_IMX8M)) ? 0x2000000 : 0x2)) +#ifdef CONFIG_MX7ULP +#define HAB_M4_PERSISTENT_START ((soc_rev() >= CHIP_REV_2_0) ? 0x20008040 : \ + 0x20008180) +#define HAB_M4_PERSISTENT_BYTES 0xB80 +#endif + static int ivt_header_error(const char *err_str, struct ivt_header *ivt_hdr) { printf("%s magic=0x%x length=0x%02x version=0x%x\n", err_str, @@ -477,15 +483,99 @@ static int get_hab_status(void) return 0; } +#ifdef CONFIG_MX7ULP + +static int get_record_len(struct record *rec) +{ + return (size_t)((rec->len[0] << 8) + (rec->len[1])); +} + +static int get_hab_status_m4(void) +{ + unsigned int index = 0; + uint8_t event_data[128]; + size_t record_len, offset = 0; + enum hab_config config = 0; + enum hab_state state = 0; + + if (imx_hab_is_enabled()) + puts("\nSecure boot enabled\n"); + else + puts("\nSecure boot disabled\n"); + + /* + * HAB in both A7 and M4 gather the security state + * and configuration of the chip from + * shared SNVS module + */ + hab_rvt_report_status(&config, &state); + printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n", + config, state); + + struct record *rec = (struct record *)(HAB_M4_PERSISTENT_START); + + record_len = get_record_len(rec); + + /* Check if HAB persistent memory is valid */ + if (rec->tag != HAB_TAG_EVT_DEF || + record_len != sizeof(struct evt_def) || + (rec->par & HAB_MAJ_MASK) != HAB_MAJ_VER) { + puts("\nERROR: Invalid HAB persistent memory\n"); + return 1; + } + + /* Parse events in HAB M4 persistent memory region */ + while (offset < HAB_M4_PERSISTENT_BYTES) { + rec = (struct record *)(HAB_M4_PERSISTENT_START + offset); + + record_len = get_record_len(rec); + + if (rec->tag == HAB_TAG_EVT) { + memcpy(&event_data, rec, record_len); + puts("\n"); + printf("--------- HAB Event %d -----------------\n", + index + 1); + puts("event data:\n"); + display_event(event_data, record_len); + puts("\n"); + index++; + } + + offset += record_len; + + /* Ensure all records start on a word boundary */ + if ((offset % 4) != 0) + offset = offset + (4 - (offset % 4)); + } + + if (!index) + puts("No HAB Events Found!\n\n"); + + return 0; +} +#endif + static int do_hab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { +#ifdef CONFIG_MX7ULP + if ((argc > 2)) { + cmd_usage(cmdtp); + return 1; + } + + if (strcmp("m4", argv[1]) == 0) + get_hab_status_m4(); + else + get_hab_status(); +#else if ((argc != 1)) { cmd_usage(cmdtp); return 1; } get_hab_status(); +#endif return 0; } @@ -588,11 +678,20 @@ error: return ret; } +#ifdef CONFIG_MX7ULP +U_BOOT_CMD( + hab_status, CONFIG_SYS_MAXARGS, 2, do_hab_status, + "display HAB status and events", + "hab_status - A7 HAB event and status\n" + "hab_status m4 - M4 HAB event and status" + ); +#else U_BOOT_CMD( hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status, "display HAB status", "" ); +#endif U_BOOT_CMD( hab_auth_img, 4, 0, do_authenticate_image, diff --git a/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt b/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt index 20fff937b6..53f71fbc3e 100644 --- a/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt +++ b/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt @@ -213,6 +213,30 @@ the example below: HAB Configuration: 0xf0, HAB State: 0x66 No HAB Events Found! +1.6.1 Verifying HAB events in i.MX7ULP +--------------------------------------- + +When booting i.MX7ULP in low power or dual boot modes the M4 binary is +authenticated by an independent HAB in M4 ROM code using a +different SRK key set. + +The U-Boot provides a M4 option in hab_status command so users can retrieve +M4 HAB failure and warning events. + +- Verify HAB M4 events: + + => hab_status m4 + + Secure boot disabled + + HAB Configuration: 0xf0, HAB State: 0x66 + No HAB Events Found! + +As HAB M4 API cannot be called from A7 core the command is parsing the M4 HAB +persistent memory region, M4 software should not modify this reserved region. + +Details about HAB persistent memory region can be found in AN12263[2]. + 1.7 Closing the device ----------------------- @@ -400,3 +424,4 @@ If no HAB events were found the zImage is successfully signed. References: [1] AN4581: "Secure Boot on i.MX 50, i.MX 53, i.MX 6 and i.MX 7 Series using HABv4" - Rev 2. +[2] AN12263: "HABv4 RVT Guidelines and Recommendations" - Rev 0. From e449e2d405eb74e1e6615ea8f49a780d00a07952 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 25 Mar 2021 17:30:14 +0800 Subject: [PATCH 040/117] imx: hab: Fix build warnings in 32-bit targets When building 32-bit targets with CONFIG_SECURE_BOOT and DEBUG enabled the following warnings are displayed: arch/arm/mach-imx/hab.c:840:41: warning: format '%lx' expects argument \ of type 'long unsigned int', but argument 3 has type 'uint32_t \ {aka unsigned int}' [-Wformat=] printf("HAB check target 0x%08x-0x%08lx fail\n", ~~~~^ %08x ddr_start, ddr_start + bytes); arch/arm/mach-imx/hab.c:845:45: warning: format '%x' expects argument \ of type 'unsigned int', but argument 3 has type 'ulong \ {aka long unsigned int}' [-Wformat=] printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n", ivt_offset, ivt_addr); ~^ %lx Fix warnings by providing the correct data type. Reviewed-by: Ye Li Signed-off-by: Breno Lima Signed-off-by: Peng Fan --- arch/arm/mach-imx/hab.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 469ef0fd1c..00bd157d0e 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -923,11 +923,11 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, status = hab_rvt_check_target(HAB_TGT_MEMORY, (void *)(ulong)ddr_start, bytes); if (status != HAB_SUCCESS) { printf("HAB check target 0x%08x-0x%08lx fail\n", - ddr_start, ddr_start + bytes); + ddr_start, ddr_start + (ulong)bytes); goto hab_exit_failure_print_status; } #ifdef DEBUG - printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n", ivt_offset, ivt_addr); + printf("\nivt_offset = 0x%x, ivt addr = 0x%lx\n", ivt_offset, ivt_addr); printf("ivt entry = 0x%08x, dcd = 0x%08x, csf = 0x%08x\n", ivt->entry, ivt->dcd, ivt->csf); puts("Dumping IVT\n"); From 2c0dcc5de6416510e8365f5e37de46c7a98d9a7e Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 25 Mar 2021 17:30:15 +0800 Subject: [PATCH 041/117] imx: HAB: Add support for iMX8MM The imx8mm has changed the address of rvt_hab, use new address for imx8mm. The authentication procedure is same as imx8mq. In u-boot, the authentication uses SIP call to trap ATF to run HAB authenticate. Users need to add CONFIG_SECURE_BOOT=y to defconfig to enable the feature. Signed-off-by: Ye Li Acked-by: Peng Fan Signed-off-by: Peng Fan --- arch/arm/include/asm/mach-imx/hab.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/mach-imx/hab.h b/arch/arm/include/asm/mach-imx/hab.h index 1085c37828..d63b85378a 100644 --- a/arch/arm/include/asm/mach-imx/hab.h +++ b/arch/arm/include/asm/mach-imx/hab.h @@ -173,7 +173,11 @@ typedef void hapi_clock_init_t(void); #define HAB_ENG_SW 0xff /* Software engine */ #ifdef CONFIG_ARM64 +#ifdef CONFIG_IMX8MQ #define HAB_RVT_BASE 0x00000880 +#else +#define HAB_RVT_BASE 0x00000900 +#endif #define HAB_RVT_ENTRY (*(ulong *)(HAB_RVT_BASE + 0x08)) #define HAB_RVT_EXIT (*(ulong *)(HAB_RVT_BASE + 0x10)) From a30798113c6f5919708cc849798a583d6e5aad53 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 25 Mar 2021 17:30:16 +0800 Subject: [PATCH 042/117] crypto: fsl: blob: Flush dcache range for destination address The blob command is not working on i.MX7D, i.MX8MQ and i.MX8MM devices. Due to different cache management it's necessary to flush dcache range for destination address so data can be available in memory. Add necessary operations in blob_encap() and blob_decap() functions. Signed-off-by: Breno Lima Reviewed-by: Ye Li Signed-off-by: Peng Fan --- drivers/crypto/fsl/fsl_blob.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c index d6bd861251..e8202cc569 100644 --- a/drivers/crypto/fsl/fsl_blob.c +++ b/drivers/crypto/fsl/fsl_blob.c @@ -65,6 +65,9 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) flush_dcache_range((unsigned long)desc, (unsigned long)desc + size); + flush_dcache_range((unsigned long)dst, + (unsigned long)dst + size); + ret = run_descriptor_jr(desc); if (ret) { @@ -130,6 +133,9 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len) flush_dcache_range((unsigned long)desc, (unsigned long)desc + size); + flush_dcache_range((unsigned long)dst, + (unsigned long)dst + size); + ret = run_descriptor_jr(desc); if (ret) { From 41b230bf296499982176b60737dccf466e8e8cc5 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 25 Mar 2021 17:30:17 +0800 Subject: [PATCH 043/117] iMX8M: Add support to enable CONFIG_IMX_HAB Add some SOC level codes and build configurations to use HAB lib for CONFIG_IMX_HAB (secure boot), like adding the SEC_CONFIG fuse, enable fuse driver, CAAM clock function, and add CAAM secure RAM to MMU table. The FSL_CAAM is temporally not enabled for iMX8M when CONFIG_IMX_HAB is set, because we don't need the CAAM driver for SPL. Signed-off-by: Ye Li Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8m/clock.h | 1 + arch/arm/mach-imx/Kconfig | 2 +- arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/imx8m/clock_imx8mm.c | 8 ++++++++ arch/arm/mach-imx/imx8m/clock_imx8mq.c | 7 +++++++ 5 files changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h index c545eb82b6..77d9428a18 100644 --- a/arch/arm/include/asm/arch-imx8m/clock.h +++ b/arch/arm/include/asm/arch-imx8m/clock.h @@ -275,3 +275,4 @@ void enable_ocotp_clk(unsigned char enable); int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); int set_clk_enet(enum enet_freq type); int set_clk_eqos(enum enet_freq type); +void hab_caam_clock_enable(unsigned char enable); diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 6d40c7fc4b..8c00ad1391 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -43,7 +43,7 @@ config USE_IMXIMG_PLUGIN config IMX_HAB bool "Support i.MX HAB features" - depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 + depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M select FSL_CAAM if HAS_CAAM imply CMD_DEKBLOB help diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 25f910b36a..63b3549d20 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -16,6 +16,7 @@ endif obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o obj-$(CONFIG_FEC_MXC) += mac.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o +obj-$(CONFIG_IMX_HAB) += hab.o obj-y += cpu.o endif diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 4024dafca1..029d06f27f 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -21,6 +21,14 @@ DECLARE_GLOBAL_DATA_PTR; static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; static u32 get_root_clk(enum clk_root_index clock_id); + +#ifdef CONFIG_IMX_HAB +void hab_caam_clock_enable(unsigned char enable) +{ + /* The CAAM clock is always on for iMX8M */ +} +#endif + void enable_ocotp_clk(unsigned char enable) { clock_enable(CCGR_OCOTP, !!enable); diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 759ec6d114..8fecc60ecb 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -310,6 +310,13 @@ static u32 get_root_clk(enum clk_root_index clock_id) return root_src_clk / (post_podf + 1) / (pre_podf + 1); } +#ifdef CONFIG_IMX_HAB +void hab_caam_clock_enable(unsigned char enable) +{ + /* The CAAM clock is always on for iMX8M */ +} +#endif + #ifdef CONFIG_MXC_OCOTP void enable_ocotp_clk(unsigned char enable) { From e149b98c11306703b9ac1e2f0014469621685be7 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 25 Mar 2021 17:30:18 +0800 Subject: [PATCH 044/117] imx: cmd_dek: Enable DEK only for chips supporting CAAM Since cmd_dek is using CAAM JR, so enable the CMD_DEK only when HAS_CAAM is set Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 8c00ad1391..ca06c1eaaf 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -45,7 +45,7 @@ config IMX_HAB bool "Support i.MX HAB features" depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M select FSL_CAAM if HAS_CAAM - imply CMD_DEKBLOB + imply CMD_DEKBLOB if HAS_CAAM help This option enables the support for secure boot (HAB). See doc/imx/habv4/* for more details. From c6d5809fe42b08675b99fc6e4651e4cb24a2e391 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 25 Mar 2021 17:30:19 +0800 Subject: [PATCH 045/117] mx6dq: hab: Fix chip version in hab.h code Since commit 8891410c729b ("MLK-19848 mx6dq: Fix chip version issue for rev1.3") it's not possible to call the HAB API functions on i.MX6DQ SoC Rev 1.3: Authenticate image from DDR location 0x12000000... undefined instruction pc : [<412c00dc>] lr : [<8ff560bc>] reloc pc : [] lr : [<178030bc>] sp : 8ef444a8 ip : 126e8068 fp : 8ff59aa8 r10: 8ffd51e4 r9 : 8ef50eb0 r8 : 006e8000 r7 : 00000000 r6 : 126ea01f r5 : 0000002b r4 : 126e8000 r3 : 412c00dd r2 : 00000001 r1 : 00000001 r0 : 00000063 Flags: nzCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... resetting ... The hab.h code is defining the HAB API base address according to the old SoC revision number, thus failing when calling the HAB API authenticate_image() function. Fix this issue by using mx6dq rev 1.3 instead of mx6dq rev 1.5. Signed-off-by: Breno Lima Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx/cpu.h | 1 + arch/arm/include/asm/mach-imx/hab.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index ef090eb2f2..bb13e07b66 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -62,6 +62,7 @@ #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 #define CHIP_REV_1_2 0x12 +#define CHIP_REV_1_3 0x13 #define CHIP_REV_1_5 0x15 #define CHIP_REV_2_0 0x20 #define CHIP_REV_2_1 0x21 diff --git a/arch/arm/include/asm/mach-imx/hab.h b/arch/arm/include/asm/mach-imx/hab.h index d63b85378a..2abf28ea45 100644 --- a/arch/arm/include/asm/mach-imx/hab.h +++ b/arch/arm/include/asm/mach-imx/hab.h @@ -195,7 +195,7 @@ typedef void hapi_clock_init_t(void); #define HAB_RVT_BASE_OLD 0x00000094 #define HAB_RVT_BASE ((is_mx6dqp()) ? \ HAB_RVT_BASE_NEW : \ - (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_3)) ? \ HAB_RVT_BASE_NEW : \ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ HAB_RVT_BASE_NEW : HAB_RVT_BASE_OLD) From 4e682d555d80875ad062e3366b8970e199e04395 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 25 Mar 2021 17:30:20 +0800 Subject: [PATCH 046/117] cmd: blob: Add IMX_HAB and CAAM supported SoCs as dependency In order to build CMD_BLOB on i.MX CAAM supported devices it's necessary to select IMX_HAB. Add IMX_HAB and CAAM supported SoCs as dependency. Signed-off-by: Breno Lima Reviewed-by: Ye Li Signed-off-by: Peng Fan --- cmd/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index 9bf5e863e4..e485dd8bea 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1960,6 +1960,8 @@ config CMD_AES config CMD_BLOB bool "Enable the 'blob' command" + depends on !MX6ULL && !MX6SLL && !MX6SL && !IMX8M && !MX7ULP + select IMX_HAB if ARCH_MX6 || ARCH_MX7 help This is used with the Freescale secure boot mechanism. From 81d5605a8654ae735e751b59f3f2d7b09fe29471 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 25 Mar 2021 17:30:21 +0800 Subject: [PATCH 047/117] cmd: blob: Instantiate RNG before running CMD_BLOB U-Boot can instantiate CAAM RNG if needed by crypto operations. Call sec_init() prior running a blob operation to ensure RNG is correctly instantiated. Make sure CAAM clock is enabled and check if a job ring is available for that operation. Signed-off-by: Breno Lima Reviewed-by: Ye Li Signed-off-by: Peng Fan --- cmd/blob.c | 14 ++++++++++++++ include/fsl_sec.h | 3 +++ 2 files changed, 17 insertions(+) diff --git a/cmd/blob.c b/cmd/blob.c index c80e6977b4..359c8940fb 100644 --- a/cmd/blob.c +++ b/cmd/blob.c @@ -9,6 +9,10 @@ #include #include #include +#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) +#include +#include +#endif /** * blob_decap() - Decapsulate the data as a blob @@ -74,6 +78,16 @@ static int do_blob(struct cmd_tbl *cmdtp, int flag, int argc, src_ptr = (uint8_t *)(uintptr_t)src_addr; dst_ptr = (uint8_t *)(uintptr_t)dst_addr; +#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) + + hab_caam_clock_enable(1); + + u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + + FSL_CAAM_ORSR_JRa_OFFSET); + if (out_jr_size != FSL_CAAM_MAX_JR_SIZE) + sec_init(); +#endif + if (enc) ret = blob_encap(km_ptr, src_ptr, dst_ptr, len); else diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 40f1c5b10d..c661bd6ead 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -344,6 +344,9 @@ struct sg_entry { #define FSL_CAAM_MP_PRVK_BYTES 32 #define FSL_CAAM_MP_MES_DGST_BYTES 32 +#define FSL_CAAM_ORSR_JRa_OFFSET 0x102c +#define FSL_CAAM_MAX_JR_SIZE 4 + /* blob_dek: * Encapsulates the src in a secure blob and stores it dst * @src: reference to the plaintext From 68a905d1ff5454201e1617d1cf920aa3648a5855 Mon Sep 17 00:00:00 2001 From: Franck LENORMAND Date: Thu, 25 Mar 2021 17:30:22 +0800 Subject: [PATCH 048/117] crypto: caam: change JR running loop Signed-off-by: Franck LENORMAND Signed-off-by: Peng Fan --- drivers/crypto/fsl/jr.c | 12 +++++++----- drivers/crypto/fsl/jr.h | 4 ++-- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 44273c345f..de5e68bf8e 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -21,6 +21,7 @@ #include #endif #include +#include #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1)) #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size)) @@ -355,8 +356,8 @@ static void desc_done(uint32_t status, void *arg) static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx) { - unsigned long long timeval = get_ticks(); - unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); + unsigned long long timeval = 0; + unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT; struct result op; int ret = 0; @@ -369,9 +370,10 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx) goto out; } - timeval = get_ticks(); - timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); while (op.done != 1) { + udelay(1); + timeval += 1; + ret = jr_dequeue(sec_idx); if (ret) { debug("Error in SEC deq\n"); @@ -379,7 +381,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx) goto out; } - if ((get_ticks() - timeval) > timeout) { + if (timeval > timeout) { debug("SEC Dequeue timed out\n"); ret = JQ_DEQ_TO_ERR; goto out; diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index ffd3a19273..1a215143d9 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -10,8 +10,8 @@ #include #define JR_SIZE 4 -/* Timeout currently defined as 90 sec */ -#define CONFIG_SEC_DEQ_TIMEOUT 90000000U +/* Timeout currently defined as 10 sec */ +#define CONFIG_USEC_DEQ_TIMEOUT 10000000U #define DEFAULT_JR_ID 0 #define DEFAULT_JR_LIODN 0 From b5438002416d24e09ddd9ad68dbd1b87548de157 Mon Sep 17 00:00:00 2001 From: Franck LENORMAND Date: Thu, 25 Mar 2021 17:30:23 +0800 Subject: [PATCH 049/117] caam: enable support for iMX7ULP Signed-off-by: Franck LENORMAND Signed-off-by: Peng Fan --- arch/arm/Kconfig | 3 +++ arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 12 ++++++++++++ arch/arm/mach-imx/mx7ulp/Kconfig | 1 + drivers/crypto/fsl/jobdesc.c | 2 +- include/fsl_sec.h | 8 ++++---- 5 files changed, 21 insertions(+), 5 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3307f2b3fc..70b9ad5b9f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -875,6 +875,9 @@ config ARCH_MX31 config ARCH_MX7ULP bool "NXP MX7ULP" select CPU_V7A + select SYS_FSL_HAS_SEC if IMX_HAB + select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE select ROM_UNIFIED_SECTIONS imply MXC_GPIO imply SYS_THUMB_BUILD diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index 9a420dc30b..cb0c2c15c0 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -16,6 +16,8 @@ #define CAAM_SEC_SRAM_SIZE (SZ_32K) #define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1) +#define CAAM_ARB_BASE_ADDR CAAM_SEC_SRAM_BASE + #define OCRAM_0_BASE (0x2F000000) #define OCRAM_0_SIZE (SZ_128K) #define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1) @@ -224,6 +226,16 @@ #define IOMUXC_DDR_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT))) #define MMDC0_PCC_REG (PCC3_RBASE + (4 * MMDC0_PCC3_SLOT)) +#define CAAM_IPS_BASE_ADDR (AIPS2_BASE + 0x240000) /* 40240000 */ + +#define CONFIG_SYS_FSL_SEC_OFFSET 0 +#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ + CONFIG_SYS_FSL_JR0_OFFSET) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + #define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32))) #define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33))) #define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34))) diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig index 6680f856c5..2ffac9cf7c 100644 --- a/arch/arm/mach-imx/mx7ulp/Kconfig +++ b/arch/arm/mach-imx/mx7ulp/Kconfig @@ -9,6 +9,7 @@ config LDO_ENABLED_MODE Select this option to enable the PMC1 LDO. config MX7ULP + select HAS_CAAM bool choice diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index fbc1aeddee..8c3db64527 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -15,7 +15,7 @@ #include "rsa_caam.h" #include -#if defined(CONFIG_MX6) || defined(CONFIG_MX7) +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) /*! * Secure memory run command * diff --git a/include/fsl_sec.h b/include/fsl_sec.h index c661bd6ead..a98f6cb12a 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -195,7 +195,7 @@ typedef struct ccsr_sec { struct jr_regs { #if defined(CONFIG_SYS_FSL_SEC_LE) && \ - !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) + !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)) u32 irba_l; u32 irba_h; #else @@ -209,7 +209,7 @@ struct jr_regs { u32 rsvd3; u32 irja; #if defined(CONFIG_SYS_FSL_SEC_LE) && \ - !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) + !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)) u32 orba_l; u32 orba_h; #else @@ -242,7 +242,7 @@ struct jr_regs { */ struct sg_entry { #if defined(CONFIG_SYS_FSL_SEC_LE) && \ - !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) + !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)) uint32_t addr_lo; /* Memory Address - lo */ uint32_t addr_hi; /* Memory Address of start of buffer - hi */ #else @@ -263,7 +263,7 @@ struct sg_entry { #define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */ -#if defined(CONFIG_MX6) || defined(CONFIG_MX7) +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) /* Job Ring Base Address */ #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1)) /* Secure Memory Offset varies accross versions */ From 88e7f5be3871a9002d4fa0fe7c9aabaab7edb0dc Mon Sep 17 00:00:00 2001 From: Franck LENORMAND Date: Thu, 25 Mar 2021 17:30:24 +0800 Subject: [PATCH 050/117] imx7ulp: Enable support for cmd blob Signed-off-by: Franck LENORMAND Signed-off-by: Peng Fan --- cmd/Kconfig | 4 ++-- cmd/blob.c | 6 ++++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index e485dd8bea..10393eea44 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1960,8 +1960,8 @@ config CMD_AES config CMD_BLOB bool "Enable the 'blob' command" - depends on !MX6ULL && !MX6SLL && !MX6SL && !IMX8M && !MX7ULP - select IMX_HAB if ARCH_MX6 || ARCH_MX7 + depends on !MX6ULL && !MX6SLL && !MX6SL && !IMX8M + select IMX_HAB if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP help This is used with the Freescale secure boot mechanism. diff --git a/cmd/blob.c b/cmd/blob.c index 359c8940fb..4e244cd126 100644 --- a/cmd/blob.c +++ b/cmd/blob.c @@ -9,7 +9,8 @@ #include #include #include -#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) +#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) || \ + defined(CONFIG_ARCH_MX7ULP) #include #include #endif @@ -78,7 +79,8 @@ static int do_blob(struct cmd_tbl *cmdtp, int flag, int argc, src_ptr = (uint8_t *)(uintptr_t)src_addr; dst_ptr = (uint8_t *)(uintptr_t)dst_addr; -#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) +#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) || \ + defined(CONFIG_ARCH_MX7ULP) hab_caam_clock_enable(1); From 940d36d5d1d2dc2697b0b379712a3bf40a34e57a Mon Sep 17 00:00:00 2001 From: Aymen Sghaier Date: Thu, 25 Mar 2021 17:30:25 +0800 Subject: [PATCH 051/117] crypto: caam: Add CAAM support to i.MX8M platforms This patch enable CAAM support for i.MX8M platforms. Signed-off-by: Aymen Sghaier Signed-off-by: Peng Fan --- arch/arm/Kconfig | 3 +++ arch/arm/mach-imx/imx8m/Kconfig | 1 + drivers/crypto/fsl/jobdesc.c | 4 +++- include/fsl_sec.h | 13 +++++++++---- 4 files changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 70b9ad5b9f..76adf7fdb2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -839,6 +839,9 @@ config ARCH_IMX8 config ARCH_IMX8M bool "NXP i.MX8M platform" select ARM64 + select SYS_FSL_HAS_SEC if IMX_HAB + select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE select DM select SUPPORT_SPL imply CMD_DM diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 59a45f7b01..e7e1315bac 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -2,6 +2,7 @@ if ARCH_IMX8M config IMX8M bool + select HAS_CAAM select ROM_UNIFIED_SECTIONS config IMX8MQ diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index 8c3db64527..0120a5c977 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -4,6 +4,7 @@ * Basic job descriptor construction * * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * */ @@ -15,7 +16,8 @@ #include "rsa_caam.h" #include -#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ + defined(CONFIG_IMX8M) /*! * Secure memory run command * diff --git a/include/fsl_sec.h b/include/fsl_sec.h index a98f6cb12a..c531a14477 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -3,6 +3,7 @@ * Common internal memory map for some Freescale SoCs * * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP */ #ifndef __FSL_SEC_H @@ -195,7 +196,8 @@ typedef struct ccsr_sec { struct jr_regs { #if defined(CONFIG_SYS_FSL_SEC_LE) && \ - !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)) + !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) u32 irba_l; u32 irba_h; #else @@ -209,7 +211,8 @@ struct jr_regs { u32 rsvd3; u32 irja; #if defined(CONFIG_SYS_FSL_SEC_LE) && \ - !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)) + !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) u32 orba_l; u32 orba_h; #else @@ -242,7 +245,8 @@ struct jr_regs { */ struct sg_entry { #if defined(CONFIG_SYS_FSL_SEC_LE) && \ - !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)) + !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) uint32_t addr_lo; /* Memory Address - lo */ uint32_t addr_hi; /* Memory Address of start of buffer - hi */ #else @@ -263,7 +267,8 @@ struct sg_entry { #define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */ -#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) /* Job Ring Base Address */ #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1)) /* Secure Memory Offset varies accross versions */ From dde92e2d1501c0f4e7fc04e10b2a9614a1d63e32 Mon Sep 17 00:00:00 2001 From: Aymen Sghaier Date: Thu, 25 Mar 2021 17:30:26 +0800 Subject: [PATCH 052/117] crypto: caam: Fix build warnings pointer casting Enabling CAAM driver for i.MX8M platforms, a 64 bits architecture, lead to casting warnings: from/to pointer to/from integer with different size. This patch fix these warnings Signed-off-by: Aymen Sghaier Signed-off-by: Peng Fan --- drivers/crypto/fsl/jr.c | 5 +++-- include/fsl_sec.h | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index de5e68bf8e..68954db99a 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * Based on CAAM driver in drivers/crypto/caam in Linux */ @@ -35,10 +36,10 @@ uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = { }; #define SEC_ADDR(idx) \ - ((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx])) + (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx])) #define SEC_JR0_ADDR(idx) \ - (SEC_ADDR(idx) + \ + (ulong)(SEC_ADDR(idx) + \ (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET)) struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC]; diff --git a/include/fsl_sec.h b/include/fsl_sec.h index c531a14477..dca0dd0328 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -13,8 +13,8 @@ #include #ifdef CONFIG_SYS_FSL_SEC_LE -#define sec_in32(a) in_le32(a) -#define sec_out32(a, v) out_le32(a, v) +#define sec_in32(a) in_le32((ulong *)(ulong)a) +#define sec_out32(a, v) out_le32((ulong *)(ulong)a, v) #define sec_in16(a) in_le16(a) #define sec_clrbits32 clrbits_le32 #define sec_setbits32 setbits_le32 From 2532429b166246ef82b975435925e2772df3e70b Mon Sep 17 00:00:00 2001 From: Aymen Sghaier Date: Thu, 25 Mar 2021 17:30:27 +0800 Subject: [PATCH 053/117] crypto: Add blob command support for i.MX8M platforms This patch enable blob command for mScale platforms. Signed-off-by: Aymen Sghaier Signed-off-by: Peng Fan --- cmd/Kconfig | 4 ++-- cmd/blob.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index 10393eea44..c735e81b37 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1960,8 +1960,8 @@ config CMD_AES config CMD_BLOB bool "Enable the 'blob' command" - depends on !MX6ULL && !MX6SLL && !MX6SL && !IMX8M - select IMX_HAB if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP + depends on !MX6ULL && !MX6SLL && !MX6SL + select IMX_HAB if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_IMX8M help This is used with the Freescale secure boot mechanism. diff --git a/cmd/blob.c b/cmd/blob.c index 4e244cd126..887219cc07 100644 --- a/cmd/blob.c +++ b/cmd/blob.c @@ -10,7 +10,7 @@ #include #include #if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) || \ - defined(CONFIG_ARCH_MX7ULP) + defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8M) #include #include #endif @@ -80,7 +80,7 @@ static int do_blob(struct cmd_tbl *cmdtp, int flag, int argc, dst_ptr = (uint8_t *)(uintptr_t)dst_addr; #if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) || \ - defined(CONFIG_ARCH_MX7ULP) + defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8M) hab_caam_clock_enable(1); From a018e6e4f7c58fe3e82d17ea552db3449c60dacc Mon Sep 17 00:00:00 2001 From: Aymen Sghaier Date: Thu, 25 Mar 2021 17:30:28 +0800 Subject: [PATCH 054/117] crypto: caam: Fix pointer size to 32bit for i.MX8M The CAAM block used in i.MX8M is 32 bits address size but when the flag PHYS_64BIT is enabled for armv8, the CAAM driver will try to use a wrong pointer size. This patch fixes this issue. Signed-off-by: Aymen Sghaier Signed-off-by: Peng Fan --- drivers/crypto/fsl/desc_constr.h | 29 +++++++++++++++-------------- drivers/crypto/fsl/fsl_hash.c | 3 ++- drivers/crypto/fsl/jobdesc.c | 13 +++++++------ drivers/crypto/fsl/jr.c | 16 ++++++++-------- drivers/crypto/fsl/jr.h | 7 ++++--- 5 files changed, 36 insertions(+), 32 deletions(-) diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h index b82ba83e73..9edb8dc64a 100644 --- a/drivers/crypto/fsl/desc_constr.h +++ b/drivers/crypto/fsl/desc_constr.h @@ -3,6 +3,7 @@ * caam descriptor construction helper functions * * Copyright 2008-2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * Based on desc_constr.h file in linux drivers/crypto/caam */ @@ -12,7 +13,7 @@ #define IMMEDIATE (1 << 23) #define CAAM_CMD_SZ sizeof(u32) -#define CAAM_PTR_SZ sizeof(dma_addr_t) +#define CAAM_PTR_SZ sizeof(u32) #define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE) #define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3) @@ -35,7 +36,7 @@ LDST_SRCDST_WORD_DECOCTRL | \ (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT)) -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) struct ptr_addr_t { #ifdef CONFIG_SYS_FSL_SEC_LE u32 low; @@ -49,9 +50,9 @@ struct ptr_addr_t { }; #endif -static inline void pdb_add_ptr(dma_addr_t *offset, dma_addr_t ptr) +static inline void pdb_add_ptr(u32 *offset, u32 ptr) { -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) /* The Position of low and high part of 64 bit address * will depend on the endianness of CAAM Block */ struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset; @@ -102,11 +103,11 @@ static inline void init_job_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes) options); } -static inline void append_ptr(u32 *desc, dma_addr_t ptr) +static inline void append_ptr(u32 *desc, uint32_t ptr) { - dma_addr_t *offset = (dma_addr_t *)desc_end(desc); + u32 *offset = (u32 *)desc_end(desc); -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) /* The Position of low and high part of 64 bit address * will depend on the endianness of CAAM Block */ struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset; @@ -159,7 +160,7 @@ static inline u32 *write_cmd(u32 *desc, u32 command) return desc + 1; } -static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len, +static inline void append_cmd_ptr(u32 *desc, uint32_t ptr, int len, u32 command) { append_cmd(desc, command | len); @@ -167,7 +168,7 @@ static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len, } /* Write length after pointer, rather than inside command */ -static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr, +static inline void append_cmd_ptr_extlen(u32 *desc, uint32_t ptr, unsigned int len, u32 command) { append_cmd(desc, command); @@ -225,7 +226,7 @@ APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD) APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE) #define APPEND_CMD_PTR(cmd, op) \ -static inline void append_##cmd(u32 *desc, dma_addr_t ptr, unsigned int len, \ +static inline void append_##cmd(u32 *desc, uint32_t ptr, unsigned int len, \ u32 options) \ { \ PRINT_POS; \ @@ -236,7 +237,7 @@ APPEND_CMD_PTR(load, LOAD) APPEND_CMD_PTR(fifo_load, FIFO_LOAD) APPEND_CMD_PTR(fifo_store, FIFO_STORE) -static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len, +static inline void append_store(u32 *desc, uint32_t ptr, unsigned int len, u32 options) { u32 cmd_src; @@ -254,7 +255,7 @@ static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len, } #define APPEND_SEQ_PTR_INTLEN(cmd, op) \ -static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, dma_addr_t ptr, \ +static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, uint32_t ptr, \ unsigned int len, \ u32 options) \ { \ @@ -278,7 +279,7 @@ APPEND_CMD_PTR_TO_IMM(load, LOAD); APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD); #define APPEND_CMD_PTR_EXTLEN(cmd, op) \ -static inline void append_##cmd##_extlen(u32 *desc, dma_addr_t ptr, \ +static inline void append_##cmd##_extlen(u32 *desc, uint32_t ptr, \ unsigned int len, u32 options) \ { \ PRINT_POS; \ @@ -292,7 +293,7 @@ APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR) * the size of its type */ #define APPEND_CMD_PTR_LEN(cmd, op, type) \ -static inline void append_##cmd(u32 *desc, dma_addr_t ptr, \ +static inline void append_##cmd(u32 *desc, uint32_t ptr, \ type len, u32 options) \ { \ PRINT_POS; \ diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index 61f953e8a6..75500a621f 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * */ @@ -95,7 +96,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf, return -EINVAL; } -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, (uint32_t)(addr >> 32)); #else sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, 0x0); diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index 0120a5c977..cd9d064657 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -165,9 +165,10 @@ int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt, append_u32(desc, aad_w2); - append_cmd_ptr(desc, (dma_addr_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR); + append_cmd_ptr(desc, (uint32_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR); - append_cmd_ptr(desc, (dma_addr_t)dek_blob + 8, out_sz, CMD_SEQ_OUT_PTR); + append_cmd_ptr(desc, (uint32_t)((ulong)dek_blob + 8), + out_sz, CMD_SEQ_OUT_PTR); append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB | OP_PCLID_SECMEM); @@ -183,7 +184,7 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc, /* SHA 256 , output is of length 32 words */ uint32_t storelen = alg_size; u32 options; - dma_addr_t dma_addr_in, dma_addr_out; + u32 dma_addr_in, dma_addr_out; dma_addr_in = virt_to_phys((void *)msg); dma_addr_out = virt_to_phys((void *)digest); @@ -212,7 +213,7 @@ void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *plain_txt, uint8_t *enc_blob, uint32_t in_sz) { - dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; + u32 dma_addr_key_idnfr, dma_addr_in, dma_addr_out; uint32_t key_sz = KEY_IDNFR_SZ_BYTES; /* output blob will have 32 bytes key blob in beginning and * 16 byte HMAC identifier at end of data blob */ @@ -237,7 +238,7 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *enc_blob, uint8_t *plain_txt, uint32_t out_sz) { - dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; + u32 dma_addr_key_idnfr, dma_addr_in, dma_addr_out; uint32_t key_sz = KEY_IDNFR_SZ_BYTES; uint32_t in_sz = out_sz + KEY_BLOB_SIZE + MAC_SIZE; @@ -313,7 +314,7 @@ void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc, struct pk_in_params *pkin, uint8_t *out, uint32_t out_siz) { - dma_addr_t dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out; + u32 dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out; dma_addr_e = virt_to_phys((void *)pkin->e); dma_addr_a = virt_to_phys((void *)pkin->a); diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 68954db99a..060a012eb2 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -87,13 +87,13 @@ static void jr_initregs(uint8_t sec_idx) phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring); phys_addr_t op_base = virt_to_phys((void *)jr->output_ring); -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) sec_out32(®s->irba_h, ip_base >> 32); #else sec_out32(®s->irba_h, 0x0); #endif sec_out32(®s->irba_l, (uint32_t)ip_base); -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) sec_out32(®s->orba_h, op_base >> 32); #else sec_out32(®s->orba_h, 0x0); @@ -119,7 +119,7 @@ static int jr_init(uint8_t sec_idx) jr->liodn = DEFAULT_JR_LIODN; #endif jr->size = JR_SIZE; - jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN, + jr->input_ring = (uint32_t *)memalign(ARCH_DMA_MINALIGN, JR_SIZE * sizeof(dma_addr_t)); if (!jr->input_ring) return -1; @@ -196,7 +196,7 @@ static int jr_enqueue(uint32_t *desc_addr, uint32_t desc_word; int length = desc_len(desc_addr); int i; -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) uint32_t *addr_hi, *addr_lo; #endif @@ -223,7 +223,7 @@ static int jr_enqueue(uint32_t *desc_addr, sizeof(struct jr_info), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) /* Write the 64 bit Descriptor address on Input Ring. * The 32 bit hign and low part of the address will * depend on endianness of SEC block. @@ -272,7 +272,7 @@ static int jr_dequeue(int sec_idx) int idx, i, found; void (*callback)(uint32_t status, void *arg); void *arg = NULL; -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) uint32_t *addr_hi, *addr_lo; #else uint32_t *addr; @@ -284,7 +284,7 @@ static int jr_dequeue(int sec_idx) found = 0; phys_addr_t op_desc; - #ifdef CONFIG_PHYS_64BIT + #if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) /* Read the 64 bit Descriptor address from Output Ring. * The 32 bit hign and low part of the address will * depend on endianness of SEC block. @@ -678,7 +678,7 @@ int sec_init_idx(uint8_t sec_idx) mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); #endif -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) mcr |= (1 << MCFGR_PS_SHIFT); #endif sec_out32(&sec->mcfgr, mcr); diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 1a215143d9..92566dd2d6 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * */ @@ -41,8 +42,8 @@ #define RNG4_MAX_HANDLES 2 struct op_ring { - phys_addr_t desc; - uint32_t status; + u32 desc; + u32 status; } __packed; struct jr_info { @@ -83,7 +84,7 @@ struct jobring { * by SEC */ /*Circular Ring of i/p descriptors */ - dma_addr_t *input_ring; + u32 *input_ring; /* Circular Ring of o/p descriptors */ /* Circula Ring containing info regarding descriptors in i/p * and o/p ring From 45f39e9fb70dc8a9cb17135d2146de402494a59e Mon Sep 17 00:00:00 2001 From: Aymen Sghaier Date: Thu, 25 Mar 2021 17:30:29 +0800 Subject: [PATCH 055/117] crypto: caam: Add secure memory vid 3 support In i.MX8M platforms the secure memory block has a newer version than those used in i.MX6/7 platforms, this patch update the driver to use the correct registers offsets. Signed-off-by: Aymen Sghaier Signed-off-by: Peng Fan --- include/fsl_sec.h | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/include/fsl_sec.h b/include/fsl_sec.h index dca0dd0328..09ce916297 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -276,7 +276,8 @@ struct sg_entry { #define SM_V2_OFFSET 0xa00 /*Secure Memory Versioning */ #define SMVID_V2 0x20105 -#define SM_VERSION(x) (x < SMVID_V2 ? 1 : 2) +#define SM_VERSION(x) ({typeof(x) _x = x; \ + _x < SMVID_V2 ? 1 : (_x < 0x20300 ? 2 : 3); }) #define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET) /* CAAM Job Ring 0 Registers */ /* Secure Memory Partition Owner register */ @@ -303,8 +304,10 @@ struct sg_entry { #define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4) #define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC) #define SM_PERM(v) (v == 1 ? 0x10 : 0x4) -#define SM_GROUP2(v) (v == 1 ? 0x14 : 0x8) -#define SM_GROUP1(v) (v == 1 ? 0x18 : 0xC) +#define SM_GROUP2(v) ({typeof(v) _v = v; \ + _v == 1 ? 0x14 : (_v == 2 ? 0x8 : 0xC); }) +#define SM_GROUP1(v) ({typeof(v) _v = v; \ + _v == 1 ? 0x18 : (_v == 2 ? 0xC : 0x8); }) #define CMD_PAGE_ALLOC 0x1 #define CMD_PAGE_DEALLOC 0x2 #define CMD_PART_DEALLOC 0x3 @@ -322,10 +325,15 @@ struct sg_entry { #define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000) #define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000) -#define JR_MID 2 /* Matches ROM configuration */ -#define KS_G1 (1 << JR_MID) /* CAAM only */ -#define PERM 0x0000B008 /* Clear on release, lock SMAP - * lock SMAG group 1 Blob */ +#ifdef CONFIG_IMX8M +#define JR_MID (1) /* Matches ATF configuration */ +#define KS_G1 (0x10000 << JR_MID) /* CAAM only */ +#define PERM (0xB080) /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */ +#else +#define JR_MID (2) /* Matches ROM configuration */ +#define KS_G1 BIT(JR_MID) /* CAAM only */ +#define PERM (0xB008) /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */ +#endif /* CONFIG_IMX8M */ /* HAB WRAPPED KEY header */ #define WRP_HDR_SIZE 0x08 From 613cf239ed490f900b8f822df4a2d5a1a27d7a47 Mon Sep 17 00:00:00 2001 From: Clement Le Marquis Date: Thu, 25 Mar 2021 17:30:32 +0800 Subject: [PATCH 056/117] imx: caam: new u-boot command to set PRIBLOB bitfield from CAAM SCFGR register to 0x3 It is highly recommended to set the PRIBLOB bitfield to 0x3 once your encrypted boot image has booted up, this prevents the generation of new blobs that can be used to decrypt an encrypted boot image. The PRIBLOB is a sticky type bit and cannot be changed until the next power on reset. Add the set_priblob_bitfield U-Boot command to prevent the generation of new blobs. Signed-off-by: Clement Le Marquis Acked-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/Kconfig | 7 +++++++ arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/priblob.c | 33 +++++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+) create mode 100644 arch/arm/mach-imx/priblob.c diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index ca06c1eaaf..27b0b081ad 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -81,6 +81,13 @@ config CMD_DEKBLOB creates a blob of data. See also CMD_BLOB and doc/imx/habv4/* for more information. +config CMD_PRIBLOB + bool "Support the set_priblob_bitfield command" + depends on HAS_CAAM && IMX_HAB + help + This option enables the priblob command which can be used + to set the priblob setting to 0x3. + config CMD_HDMIDETECT bool "Support the 'hdmidet' command" help diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 63b3549d20..82aa39dee7 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imxrt)) obj-y += misc.o +obj-$(CONFIG_CMD_PRIBLOB) += priblob.o obj-$(CONFIG_SPL_BUILD) += spl.o endif ifeq ($(SOC),$(filter $(SOC),mx7)) diff --git a/arch/arm/mach-imx/priblob.c b/arch/arm/mach-imx/priblob.c new file mode 100644 index 0000000000..e253eddfdc --- /dev/null +++ b/arch/arm/mach-imx/priblob.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/* + * Boot command to get and set the PRIBLOB bitfield form the SCFGR register + * of the CAAM IP. It is recommended to set this bitfield to 3 once your + * encrypted boot image is ready, to prevent the generation of blobs usable + * to decrypt an encrypted boot image. + */ + +#include +#include +#include +#include "../drivers/crypto/fsl_caam_internal.h" + +int do_priblob_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + writel((readl(CAAM_SCFGR) & 0xFFFFFFFC) | 3, CAAM_SCFGR); + printf("New priblob setting = 0x%x\n", readl(CAAM_SCFGR) & 0x3); + + return 0; +} + +U_BOOT_CMD( + set_priblob_bitfield, 1, 0, do_priblob_write, + "Set the PRIBLOB bitfield to 3", + "\n" + " - Write 3 in PRIBLOB bitfield of SCFGR regiter of CAAM IP.\n" + " Prevent the generation of blobs usable to decrypt an\n" + " encrypted boot image." +); From 56d2050f40287fe46757d4cbe69d62a1381c3c64 Mon Sep 17 00:00:00 2001 From: Clement Faure Date: Thu, 25 Mar 2021 17:30:33 +0800 Subject: [PATCH 057/117] imx8m: Add DEK blob encapsulation for imx8m Add DEK blob encapsulation support for IMX8M through "dek_blob" command. On ARMv8, u-boot runs in non-secure, thus cannot encapsulate a DEK blob for encrypted boot. The DEK blob is encapsulated by OP-TEE through a trusted application call. U-boot sends and receives the DEK and the DEK blob binaries through OP-TEE dynamic shared memory. To enable the DEK blob encapsulation, add to the defconfig: CONFIG_SECURE_BOOT=y CONFIG_FAT_WRITE=y CONFIG_CMD_DEKBLOB=y Signed-off-by: Clement Faure Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/dts/imx8mm-evk-u-boot.dtsi | 7 ++ arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 6 ++ arch/arm/dts/imx8mp-evk-u-boot.dtsi | 6 ++ arch/arm/mach-imx/Kconfig | 17 ++++ arch/arm/mach-imx/cmd_dek.c | 100 ++++++++++++++++++++--- drivers/crypto/fsl/Makefile | 3 +- include/fsl_sec.h | 4 +- 7 files changed, 128 insertions(+), 15 deletions(-) diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index 7f48912b49..6d204526af 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -9,6 +9,13 @@ wdt = <&wdog1>; u-boot,dm-spl; }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; }; &{/soc@0} { diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 8cd15be7a8..a0fd2a3098 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -9,6 +9,12 @@ wdt = <&wdog1>; u-boot,dm-spl; }; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; }; &{/soc@0} { diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 6a91404d7b..27075c5217 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -9,6 +9,12 @@ wdt = <&wdog1>; u-boot,dm-spl; }; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; }; &{/soc@0} { diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 27b0b081ad..3bcfced8f0 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -75,12 +75,29 @@ config CMD_BMODE config CMD_DEKBLOB bool "Support the 'dek_blob' command" + select IMX_CAAM_DEK_ENCAP if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP + select IMX_OPTEE_DEK_ENCAP if ARCH_IMX8M help This enables the 'dek_blob' command which is used with the Freescale secure boot mechanism. This command encapsulates and creates a blob of data. See also CMD_BLOB and doc/imx/habv4/* for more information. +config IMX_CAAM_DEK_ENCAP + bool "Support the DEK blob encapsulation with CAAM U-Boot driver" + help + This enables the DEK blob encapsulation with the U-Boot CAAM driver. + This option is only available on imx6, imx7 and imx7ulp. + +config IMX_OPTEE_DEK_ENCAP + select TEE + select OPTEE + bool "Support the DEK blob encapsulation with OP-TEE" + help + This enabled the DEK blob encapsulation with OP-TEE. The communication + with OP-TEE is done through a SMC call and OP-TEE shared memory. This + option is available on imx8mm. + config CMD_PRIBLOB bool "Support the set_priblob_bitfield command" depends on HAS_CAAM && IMX_HAB diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index bd380429c0..75aec2cef0 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -14,6 +14,7 @@ #include #include #include +#include /** * blob_dek() - Encapsulate the DEK as a blob using CAM's Key @@ -23,9 +24,13 @@ * * Returns zero on success,and negative on error. */ -static int blob_encap_dek(const u8 *src, u8 *dst, u32 len) +#ifdef CONFIG_IMX_CAAM_DEK_ENCAP +static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len) { - int ret = 0; + u8 *src_ptr, *dst_ptr; + + src_ptr = map_sysmem(src_addr, len / 8); + dst_ptr = map_sysmem(dst_addr, BLOB_SIZE(len / 8)); hab_caam_clock_enable(1); @@ -40,10 +45,90 @@ static int blob_encap_dek(const u8 *src, u8 *dst, u32 len) } len /= 8; - ret = blob_dek(src, dst, len); + return blob_dek(src_ptr, dst_ptr, len); +} +#endif /* CONFIG_IMX_CAAM_DEK_ENCAP */ + +#ifdef CONFIG_IMX_OPTEE_DEK_ENCAP + +#define PTA_DEK_BLOB_PTA_UUID {0xef477737, 0x0db1, 0x4a9d, \ + {0x84, 0x37, 0xf2, 0xf5, 0x35, 0xc0, 0xbd, 0x92} } + +#define OPTEE_BLOB_HDR_SIZE 8 + +static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len) +{ + struct udevice *dev = NULL; + struct tee_shm *shm_input, *shm_output; + struct tee_open_session_arg arg = {0}; + struct tee_invoke_arg arg_func = {0}; + const struct tee_optee_ta_uuid uuid = PTA_DEK_BLOB_PTA_UUID; + struct tee_param param[4] = {0}; + int ret; + + /* Get tee device */ + dev = tee_find_device(NULL, NULL, NULL, NULL); + if (!dev) { + printf("Cannot get OP-TEE device\n"); + return -1; + } + + /* Set TA UUID */ + tee_optee_ta_uuid_to_octets(arg.uuid, &uuid); + + /* Open TA session */ + ret = tee_open_session(dev, &arg, 0, NULL); + if (ret < 0) { + printf("Cannot open session with PTA Blob 0x%X\n", ret); + return -1; + } + + /* Allocate shared input and output buffers for TA */ + ret = tee_shm_register(dev, (void *)(ulong)src_addr, len / 8, 0x0, &shm_input); + if (ret < 0) { + printf("Cannot register input shared memory 0x%X\n", ret); + goto error; + } + + ret = tee_shm_register(dev, (void *)(ulong)dst_addr, + BLOB_SIZE(len / 8) + OPTEE_BLOB_HDR_SIZE, + 0x0, &shm_output); + if (ret < 0) { + printf("Cannot register output shared memory 0x%X\n", ret); + goto error; + } + + param[0].u.memref.shm = shm_input; + param[0].u.memref.size = shm_input->size; + param[0].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + param[1].u.memref.shm = shm_output; + param[1].u.memref.size = shm_output->size; + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_OUTPUT; + param[2].attr = TEE_PARAM_ATTR_TYPE_NONE; + param[3].attr = TEE_PARAM_ATTR_TYPE_NONE; + + arg_func.func = 0; + arg_func.session = arg.session; + + /* Generate DEK blob */ + arg_func.session = arg.session; + ret = tee_invoke_func(dev, &arg_func, 4, param); + if (ret < 0) + printf("Cannot generate Blob with PTA DEK Blob 0x%X\n", ret); + +error: + /* Free shared memory */ + tee_shm_free(shm_input); + tee_shm_free(shm_output); + + /* Close session */ + ret = tee_close_session(dev, arg.session); + if (ret < 0) + printf("Cannot close session with PTA DEK Blob 0x%X\n", ret); return ret; } +#endif /* CONFIG_IMX_OPTEE_DEK_ENCAP */ /** * do_dek_blob() - Handle the "dek_blob" command-line command @@ -59,8 +144,6 @@ static int do_dek_blob(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { uint32_t src_addr, dst_addr, len; - uint8_t *src_ptr, *dst_ptr; - int ret = 0; if (argc != 4) return CMD_RET_USAGE; @@ -69,12 +152,7 @@ static int do_dek_blob(struct cmd_tbl *cmdtp, int flag, int argc, dst_addr = simple_strtoul(argv[2], NULL, 16); len = simple_strtoul(argv[3], NULL, 10); - src_ptr = map_sysmem(src_addr, len/8); - dst_ptr = map_sysmem(dst_addr, BLOB_SIZE(len/8)); - - ret = blob_encap_dek(src_ptr, dst_ptr, len); - - return ret; + return blob_encap_dek(src_addr, dst_addr, len); } /***************************************************/ diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index eb689c1b9f..f9c3ccecfc 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -4,8 +4,7 @@ obj-y += sec.o obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o -obj-$(CONFIG_CMD_BLOB) += fsl_blob.o -obj-$(CONFIG_CMD_DEKBLOB) += fsl_blob.o +obj-$(CONFIG_CMD_BLOB)$(CONFIG_IMX_CAAM_DEK_ENCAP) += fsl_blob.o obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o obj-$(CONFIG_FSL_CAAM_RNG) += rng.o obj-$(CONFIG_FSL_MFGPROT) += fsl_mfgprot.o diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 09ce916297..c4121696f8 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -28,6 +28,8 @@ #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined #endif +#define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */ + /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* RNG4 TRNG test registers */ @@ -265,8 +267,6 @@ struct sg_entry { #define SG_ENTRY_OFFSET_SHIFT 0 }; -#define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */ - #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) /* Job Ring Base Address */ From 69f542ca2b68b88cd31118c3bf926dd59b544473 Mon Sep 17 00:00:00 2001 From: Clement Faure Date: Thu, 25 Mar 2021 17:30:34 +0800 Subject: [PATCH 058/117] imx8: Add DEK blob encapsulation Add DEK encapsulation support for imx8. The DEK blob is generated by the SECO through the SCFW API. Signed-off-by: Clement Faure Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8/image.h | 11 ++ arch/arm/mach-imx/Kconfig | 7 ++ arch/arm/mach-imx/cmd_dek.c | 152 +++++++++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 1 + 4 files changed, 171 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8/image.h b/arch/arm/include/asm/arch-imx8/image.h index c1e5700859..547beeb986 100644 --- a/arch/arm/include/asm/arch-imx8/image.h +++ b/arch/arm/include/asm/arch-imx8/image.h @@ -53,4 +53,15 @@ struct signature_block_hdr { u16 signature_offset; u32 reserved; } __packed; + +struct generate_key_blob_hdr { + u8 version; + u8 length_lsb; + u8 length_msb; + u8 tag; + u8 flags; + u8 size; + u8 algorithm; + u8 mode; +} __packed; #endif diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 3bcfced8f0..26bfc5ccc4 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -77,6 +77,7 @@ config CMD_DEKBLOB bool "Support the 'dek_blob' command" select IMX_CAAM_DEK_ENCAP if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP select IMX_OPTEE_DEK_ENCAP if ARCH_IMX8M + select IMX_SECO_DEK_ENCAP if ARCH_IMX8 help This enables the 'dek_blob' command which is used with the Freescale secure boot mechanism. This command encapsulates and @@ -98,6 +99,12 @@ config IMX_OPTEE_DEK_ENCAP with OP-TEE is done through a SMC call and OP-TEE shared memory. This option is available on imx8mm. +config IMX_SECO_DEK_ENCAP + bool "Support the DEK blob encapsulation with SECO" + help + This enabled the DEK blob encapsulation with the SECO API. This option + is only available on imx8. + config CMD_PRIBLOB bool "Support the set_priblob_bitfield command" depends on HAS_CAAM && IMX_HAB diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 75aec2cef0..b10ead1942 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -15,6 +15,11 @@ #include #include #include +#ifdef CONFIG_IMX_SECO_DEK_ENCAP +#include +#include +#endif +#include /** * blob_dek() - Encapsulate the DEK as a blob using CAM's Key @@ -129,6 +134,153 @@ error: return ret; } #endif /* CONFIG_IMX_OPTEE_DEK_ENCAP */ +#ifdef CONFIG_IMX_SECO_DEK_ENCAP + +#define DEK_BLOB_KEY_ID 0x0 + +#define AHAB_PRIVATE_KEY 0x81 +#define AHAB_VERSION 0x00 +#define AHAB_MODE_CBC 0x67 +#define AHAB_ALG_AES 0x55 +#define AHAB_128_AES_KEY 0x10 +#define AHAB_192_AES_KEY 0x18 +#define AHAB_256_AES_KEY 0x20 +#define AHAB_FLAG_KEK 0x80 +#define AHAB_DEK_BLOB 0x01 + +#define DEK_BLOB_HDR_SIZE 8 +#define SECO_PT 2U + +static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len) +{ + sc_err_t err; + sc_rm_mr_t mr_input, mr_output; + struct generate_key_blob_hdr hdr; + u8 in_size, out_size; + u8 *src_ptr, *dst_ptr; + int ret = 0; + int i; + + /* Set sizes */ + in_size = sizeof(struct generate_key_blob_hdr) + len / 8; + out_size = BLOB_SIZE(len / 8) + DEK_BLOB_HDR_SIZE; + + /* Get src and dst virtual addresses */ + src_ptr = map_sysmem(src_addr, in_size); + dst_ptr = map_sysmem(dst_addr, out_size); + + /* Check addr input */ + if (!(src_ptr && dst_ptr)) { + debug("src_addr or dst_addr invalid\n"); + return -1; + } + + /* Build key header */ + hdr.version = AHAB_VERSION; + hdr.length_lsb = sizeof(struct generate_key_blob_hdr) + len / 8; + hdr.length_msb = 0x00; + hdr.tag = AHAB_PRIVATE_KEY; + hdr.flags = AHAB_DEK_BLOB; + hdr.algorithm = AHAB_ALG_AES; + hdr.mode = AHAB_MODE_CBC; + + switch (len) { + case 128: + hdr.size = AHAB_128_AES_KEY; + break; + case 192: + hdr.size = AHAB_192_AES_KEY; + break; + case 256: + hdr.size = AHAB_256_AES_KEY; + break; + default: + /* Not supported */ + debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n"); + return -1; + } + + /* Build input message */ + memmove((void *)(src_ptr + sizeof(struct generate_key_blob_hdr)), + (void *)src_ptr, len / 8); + memcpy((void *)src_ptr, (void *)&hdr, + sizeof(struct generate_key_blob_hdr)); + + /* Flush the cache before triggering the CAAM DMA */ + flush_dcache_range(src_addr, src_addr + in_size); + + /* Find input memory region */ + err = sc_rm_find_memreg((-1), &mr_input, src_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1), + ALIGN(src_addr + in_size, CONFIG_SYS_CACHELINE_SIZE)); + if (err) { + printf("Error: find memory region 0x%X\n", src_addr); + return -ENOMEM; + } + + /* Find output memory region */ + err = sc_rm_find_memreg((-1), &mr_output, dst_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1), + ALIGN(dst_addr + out_size, CONFIG_SYS_CACHELINE_SIZE)); + if (err) { + printf("Error: find memory region 0x%X\n", dst_addr); + return -ENOMEM; + } + + /* Set memory region permissions for SECO */ + err = sc_rm_set_memreg_permissions(-1, mr_input, SECO_PT, + SC_RM_PERM_FULL); + if (err) { + printf("Set permission failed for input memory region\n"); + ret = -EPERM; + goto error; + } + + err = sc_rm_set_memreg_permissions(-1, mr_output, SECO_PT, + SC_RM_PERM_FULL); + if (err) { + printf("Set permission failed for output memory region\n"); + ret = -EPERM; + goto error; + } + + /* Flush output data before SECO operation */ + flush_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr + + roundup(out_size, ARCH_DMA_MINALIGN))); + + /* Generate DEK blob */ + err = sc_seco_gen_key_blob((-1), 0x0, src_addr, dst_addr, out_size); + if (err) { + ret = -EPERM; + goto error; + } + + /* Invalidate output buffer */ + invalidate_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr + + roundup(out_size, ARCH_DMA_MINALIGN))); + + printf("DEK Blob\n"); + for (i = 0; i < DEK_BLOB_HDR_SIZE + BLOB_SIZE(len / 8); i++) + printf("%02X", dst_ptr[i]); + printf("\n"); + +error: + /* Remove memory region permission to SECO */ + err = sc_rm_set_memreg_permissions(-1, mr_input, SECO_PT, + SC_RM_PERM_NONE); + if (err) { + printf("Error: remove permission failed for input\n"); + ret = -EPERM; + } + + err = sc_rm_set_memreg_permissions(-1, mr_output, SECO_PT, + SC_RM_PERM_NONE); + if (err) { + printf("Error: remove permission failed for output\n"); + ret = -EPERM; + } + + return ret; +} +#endif /* CONFIG_IMX_SECO_DEK_ENCAP */ /** * do_dek_blob() - Handle the "dek_blob" command-line command diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 04b9729109..4e76612d05 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -2,6 +2,7 @@ if ARCH_IMX8 config AHAB_BOOT bool "Support i.MX8 AHAB features" + imply CMD_DEKBLOB help This option enables the support for AHAB secure boot. From 58fc03e2a65884c17841dd4eee58c97bbeb2297b Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 25 Mar 2021 17:30:35 +0800 Subject: [PATCH 059/117] fsl_mfgprot: Fix typo in sign_mppubk() The signature is generated using manufacturing protection private key. Fix typo in fsl_mfgprot.c. Signed-off-by: Breno Lima Signed-off-by: Peng Fan --- drivers/crypto/fsl/fsl_mfgprot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/fsl/fsl_mfgprot.c b/drivers/crypto/fsl/fsl_mfgprot.c index fa874e7a9b..29af79f577 100644 --- a/drivers/crypto/fsl/fsl_mfgprot.c +++ b/drivers/crypto/fsl/fsl_mfgprot.c @@ -138,7 +138,7 @@ int sign_mppubk(const u8 *m, int data_size, u8 *dgst, u8 *c, u8 *d) flush_dcache_range((unsigned long)d, (unsigned long)d + size); /* Execute Job Descriptor */ - puts("\nSigning message with Manufacturing Protection Public Key\n"); + puts("\nSigning message with Manufacturing Protection Private Key\n"); ret = run_descriptor_jr(dsc); if (ret) { From 2ff17d2f74c544111478437971a7dd15d3468c02 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 25 Mar 2021 17:30:36 +0800 Subject: [PATCH 060/117] crypto: fsl: refactor for 32 bit version CAAM support on ARM64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Previous patch "MLK-18044-4: crypto: caam: Fix pointer size to 32bit for i.MX8M" breaks the 64 bits CAAM. Since i.MX CAAM are all 32 bits no matter the ARM arch (32 or 64), to adapt and not break 64 bits CAAM support, add a new config CONFIG_CAAM_64BIT and new relevant type "caam_dma_addr_t". This config is default enabled when CONFIG_PHYS_64BIT is set except for iMX8M. Signed-off-by: Ye Li Reviewed-by: Horia Geantă Signed-off-by: Peng Fan --- drivers/crypto/fsl/Kconfig | 6 ++++ drivers/crypto/fsl/desc.h | 48 +++++++++++++++++--------------- drivers/crypto/fsl/desc_constr.h | 29 ++++++++++--------- drivers/crypto/fsl/fsl_hash.c | 7 ++--- drivers/crypto/fsl/jobdesc.c | 13 ++++----- drivers/crypto/fsl/jr.c | 36 ++++++++++++------------ drivers/crypto/fsl/jr.h | 10 +++---- drivers/crypto/fsl/type.h | 16 +++++++++++ 8 files changed, 93 insertions(+), 72 deletions(-) create mode 100644 drivers/crypto/fsl/type.h diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index 5ed6140da3..1f5dfb94bb 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -7,6 +7,12 @@ config FSL_CAAM Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses Job Ring as interface to communicate with CAAM. +config CAAM_64BIT + bool + default y if PHYS_64BIT && !ARCH_IMX8M + help + Select Crypto driver for 64 bits CAAM version + config SYS_FSL_HAS_SEC bool help diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h index 9d1ae059a7..5705c4f944 100644 --- a/drivers/crypto/fsl/desc.h +++ b/drivers/crypto/fsl/desc.h @@ -11,6 +11,8 @@ #ifndef DESC_H #define DESC_H +#include "type.h" + #define KEY_BLOB_SIZE 32 #define MAC_SIZE 16 @@ -693,29 +695,29 @@ /* Structures for Protocol Data Blocks */ struct __packed pdb_ecdsa_verify { uint32_t pdb_hdr; - dma_addr_t dma_q; /* Pointer to q (elliptic curve) */ - dma_addr_t dma_r; /* Pointer to r (elliptic curve) */ - dma_addr_t dma_g_xy; /* Pointer to Gx,y (elliptic curve) */ - dma_addr_t dma_pkey; /* Pointer to Wx,y (public key) */ - dma_addr_t dma_hash; /* Pointer to hash input */ - dma_addr_t dma_c; /* Pointer to C_signature */ - dma_addr_t dma_d; /* Pointer to D_signature */ - dma_addr_t dma_buf; /* Pointer to 64-byte temp buffer */ - dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */ + caam_dma_addr_t dma_q; /* Pointer to q (elliptic curve) */ + caam_dma_addr_t dma_r; /* Pointer to r (elliptic curve) */ + caam_dma_addr_t dma_g_xy; /* Pointer to Gx,y (elliptic curve) */ + caam_dma_addr_t dma_pkey; /* Pointer to Wx,y (public key) */ + caam_dma_addr_t dma_hash; /* Pointer to hash input */ + caam_dma_addr_t dma_c; /* Pointer to C_signature */ + caam_dma_addr_t dma_d; /* Pointer to D_signature */ + caam_dma_addr_t dma_buf; /* Pointer to 64-byte temp buffer */ + caam_dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */ uint32_t img_size; /* Length of Message */ }; struct __packed pdb_ecdsa_sign { uint32_t pdb_hdr; - dma_addr_t dma_q; /* Pointer to q (elliptic curve) */ - dma_addr_t dma_r; /* Pointer to r (elliptic curve) */ - dma_addr_t dma_g_xy; /* Pointer to Gx,y (elliptic curve) */ - dma_addr_t dma_pri_key; /* Pointer to S (Private key) */ - dma_addr_t dma_hash; /* Pointer to hash input */ - dma_addr_t dma_c; /* Pointer to C_signature */ - dma_addr_t dma_d; /* Pointer to D_signature */ - dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */ - dma_addr_t dma_u; /* Pointer to Per Message Random */ + caam_dma_addr_t dma_q; /* Pointer to q (elliptic curve) */ + caam_dma_addr_t dma_r; /* Pointer to r (elliptic curve) */ + caam_dma_addr_t dma_g_xy; /* Pointer to Gx,y (elliptic curve) */ + caam_dma_addr_t dma_pri_key; /* Pointer to S (Private key) */ + caam_dma_addr_t dma_hash; /* Pointer to hash input */ + caam_dma_addr_t dma_c; /* Pointer to C_signature */ + caam_dma_addr_t dma_d; /* Pointer to D_signature */ + caam_dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */ + caam_dma_addr_t dma_u; /* Pointer to Per Message Random */ uint32_t img_size; /* Length of Message */ }; @@ -726,16 +728,16 @@ struct __packed pdb_ecdsa_sign { struct __packed pdb_mp_pub_k { uint32_t pdb_hdr; #define PDB_MP_PUB_K_SGF_SHIFT 31 - dma_addr_t dma_pkey; /* Pointer to Wx,y (public key) */ + caam_dma_addr_t dma_pkey; /* Pointer to Wx,y (public key) */ }; struct __packed pdb_mp_sign { uint32_t pdb_hdr; #define PDB_MP_SIGN_SGF_SHIFT 28 - dma_addr_t dma_addr_msg; /* Pointer to Message */ - dma_addr_t dma_addr_hash; /* Pointer to hash output */ - dma_addr_t dma_addr_c_sig; /* Pointer to C_signature */ - dma_addr_t dma_addr_d_sig; /* Pointer to D_signature */ + caam_dma_addr_t dma_addr_msg; /* Pointer to Message */ + caam_dma_addr_t dma_addr_hash; /* Pointer to hash output */ + caam_dma_addr_t dma_addr_c_sig; /* Pointer to C_signature */ + caam_dma_addr_t dma_addr_d_sig; /* Pointer to D_signature */ uint32_t img_size; /* Length of Message */ }; diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h index 9edb8dc64a..209557c4ff 100644 --- a/drivers/crypto/fsl/desc_constr.h +++ b/drivers/crypto/fsl/desc_constr.h @@ -3,7 +3,6 @@ * caam descriptor construction helper functions * * Copyright 2008-2014 Freescale Semiconductor, Inc. - * Copyright 2018 NXP * * Based on desc_constr.h file in linux drivers/crypto/caam */ @@ -13,7 +12,7 @@ #define IMMEDIATE (1 << 23) #define CAAM_CMD_SZ sizeof(u32) -#define CAAM_PTR_SZ sizeof(u32) +#define CAAM_PTR_SZ sizeof(caam_dma_addr_t) #define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE) #define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3) @@ -36,7 +35,7 @@ LDST_SRCDST_WORD_DECOCTRL | \ (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT)) -#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) +#ifdef CONFIG_CAAM_64BIT struct ptr_addr_t { #ifdef CONFIG_SYS_FSL_SEC_LE u32 low; @@ -50,9 +49,9 @@ struct ptr_addr_t { }; #endif -static inline void pdb_add_ptr(u32 *offset, u32 ptr) +static inline void pdb_add_ptr(caam_dma_addr_t *offset, caam_dma_addr_t ptr) { -#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) +#ifdef CONFIG_CAAM_64BIT /* The Position of low and high part of 64 bit address * will depend on the endianness of CAAM Block */ struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset; @@ -103,11 +102,11 @@ static inline void init_job_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes) options); } -static inline void append_ptr(u32 *desc, uint32_t ptr) +static inline void append_ptr(u32 *desc, caam_dma_addr_t ptr) { - u32 *offset = (u32 *)desc_end(desc); + caam_dma_addr_t *offset = (caam_dma_addr_t *)desc_end(desc); -#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) +#ifdef CONFIG_CAAM_64BIT /* The Position of low and high part of 64 bit address * will depend on the endianness of CAAM Block */ struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset; @@ -160,7 +159,7 @@ static inline u32 *write_cmd(u32 *desc, u32 command) return desc + 1; } -static inline void append_cmd_ptr(u32 *desc, uint32_t ptr, int len, +static inline void append_cmd_ptr(u32 *desc, caam_dma_addr_t ptr, int len, u32 command) { append_cmd(desc, command | len); @@ -168,7 +167,7 @@ static inline void append_cmd_ptr(u32 *desc, uint32_t ptr, int len, } /* Write length after pointer, rather than inside command */ -static inline void append_cmd_ptr_extlen(u32 *desc, uint32_t ptr, +static inline void append_cmd_ptr_extlen(u32 *desc, caam_dma_addr_t ptr, unsigned int len, u32 command) { append_cmd(desc, command); @@ -226,7 +225,7 @@ APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD) APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE) #define APPEND_CMD_PTR(cmd, op) \ -static inline void append_##cmd(u32 *desc, uint32_t ptr, unsigned int len, \ +static inline void append_##cmd(u32 *desc, caam_dma_addr_t ptr, unsigned int len, \ u32 options) \ { \ PRINT_POS; \ @@ -237,7 +236,7 @@ APPEND_CMD_PTR(load, LOAD) APPEND_CMD_PTR(fifo_load, FIFO_LOAD) APPEND_CMD_PTR(fifo_store, FIFO_STORE) -static inline void append_store(u32 *desc, uint32_t ptr, unsigned int len, +static inline void append_store(u32 *desc, caam_dma_addr_t ptr, unsigned int len, u32 options) { u32 cmd_src; @@ -255,7 +254,7 @@ static inline void append_store(u32 *desc, uint32_t ptr, unsigned int len, } #define APPEND_SEQ_PTR_INTLEN(cmd, op) \ -static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, uint32_t ptr, \ +static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, caam_dma_addr_t ptr, \ unsigned int len, \ u32 options) \ { \ @@ -279,7 +278,7 @@ APPEND_CMD_PTR_TO_IMM(load, LOAD); APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD); #define APPEND_CMD_PTR_EXTLEN(cmd, op) \ -static inline void append_##cmd##_extlen(u32 *desc, uint32_t ptr, \ +static inline void append_##cmd##_extlen(u32 *desc, caam_dma_addr_t ptr, \ unsigned int len, u32 options) \ { \ PRINT_POS; \ @@ -293,7 +292,7 @@ APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR) * the size of its type */ #define APPEND_CMD_PTR_LEN(cmd, op, type) \ -static inline void append_##cmd(u32 *desc, uint32_t ptr, \ +static inline void append_##cmd(u32 *desc, caam_dma_addr_t ptr, \ type len, u32 options) \ { \ PRINT_POS; \ diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index 75500a621f..8b5c26db07 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2018 NXP * */ @@ -88,7 +87,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf, enum caam_hash_algos caam_algo) { uint32_t final; - phys_addr_t addr = virt_to_phys((void *)buf); + caam_dma_addr_t addr = virt_to_phys((void *)buf); struct sha_ctx *ctx = hash_ctx; if (ctx->sg_num >= MAX_SG_32) { @@ -96,12 +95,12 @@ static int caam_hash_update(void *hash_ctx, const void *buf, return -EINVAL; } -#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) +#ifdef CONFIG_CAAM_64BIT sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, (uint32_t)(addr >> 32)); #else sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, 0x0); #endif - sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_lo, (uint32_t)addr); + sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_lo, (caam_dma_addr_t)addr); sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag, (size & SG_ENTRY_LENGTH_MASK)); diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index cd9d064657..d235415531 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -165,10 +165,9 @@ int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt, append_u32(desc, aad_w2); - append_cmd_ptr(desc, (uint32_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR); + append_cmd_ptr(desc, (caam_dma_addr_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR); - append_cmd_ptr(desc, (uint32_t)((ulong)dek_blob + 8), - out_sz, CMD_SEQ_OUT_PTR); + append_cmd_ptr(desc, (caam_dma_addr_t)(ulong)(dek_blob + 8), out_sz, CMD_SEQ_OUT_PTR); append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB | OP_PCLID_SECMEM); @@ -184,7 +183,7 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc, /* SHA 256 , output is of length 32 words */ uint32_t storelen = alg_size; u32 options; - u32 dma_addr_in, dma_addr_out; + caam_dma_addr_t dma_addr_in, dma_addr_out; dma_addr_in = virt_to_phys((void *)msg); dma_addr_out = virt_to_phys((void *)digest); @@ -213,7 +212,7 @@ void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *plain_txt, uint8_t *enc_blob, uint32_t in_sz) { - u32 dma_addr_key_idnfr, dma_addr_in, dma_addr_out; + caam_dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; uint32_t key_sz = KEY_IDNFR_SZ_BYTES; /* output blob will have 32 bytes key blob in beginning and * 16 byte HMAC identifier at end of data blob */ @@ -238,7 +237,7 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *enc_blob, uint8_t *plain_txt, uint32_t out_sz) { - u32 dma_addr_key_idnfr, dma_addr_in, dma_addr_out; + caam_dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; uint32_t key_sz = KEY_IDNFR_SZ_BYTES; uint32_t in_sz = out_sz + KEY_BLOB_SIZE + MAC_SIZE; @@ -314,7 +313,7 @@ void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc, struct pk_in_params *pkin, uint8_t *out, uint32_t out_siz) { - u32 dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out; + caam_dma_addr_t dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out; dma_addr_e = virt_to_phys((void *)pkin->e); dma_addr_a = virt_to_phys((void *)pkin->a); diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 060a012eb2..22b649219e 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -84,16 +84,16 @@ static void jr_initregs(uint8_t sec_idx) { struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); struct jobring *jr = &jr0[sec_idx]; - phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring); - phys_addr_t op_base = virt_to_phys((void *)jr->output_ring); + caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring); + caam_dma_addr_t op_base = virt_to_phys((void *)jr->output_ring); -#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) +#ifdef CONFIG_CAAM_64BIT sec_out32(®s->irba_h, ip_base >> 32); #else sec_out32(®s->irba_h, 0x0); #endif sec_out32(®s->irba_l, (uint32_t)ip_base); -#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) +#ifdef CONFIG_CAAM_64BIT sec_out32(®s->orba_h, op_base >> 32); #else sec_out32(®s->orba_h, 0x0); @@ -119,8 +119,8 @@ static int jr_init(uint8_t sec_idx) jr->liodn = DEFAULT_JR_LIODN; #endif jr->size = JR_SIZE; - jr->input_ring = (uint32_t *)memalign(ARCH_DMA_MINALIGN, - JR_SIZE * sizeof(dma_addr_t)); + jr->input_ring = (caam_dma_addr_t *)memalign(ARCH_DMA_MINALIGN, + JR_SIZE * sizeof(caam_dma_addr_t)); if (!jr->input_ring) return -1; @@ -131,7 +131,7 @@ static int jr_init(uint8_t sec_idx) if (!jr->output_ring) return -1; - memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t)); + memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t)); memset(jr->output_ring, 0, jr->op_size); start_jr0(sec_idx); @@ -150,7 +150,7 @@ static int jr_sw_cleanup(uint8_t sec_idx) jr->read_idx = 0; jr->write_idx = 0; memset(jr->info, 0, sizeof(jr->info)); - memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t)); + memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t)); memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring)); return 0; @@ -196,7 +196,7 @@ static int jr_enqueue(uint32_t *desc_addr, uint32_t desc_word; int length = desc_len(desc_addr); int i; -#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) +#ifdef CONFIG_CAAM_64BIT uint32_t *addr_hi, *addr_lo; #endif @@ -210,7 +210,7 @@ static int jr_enqueue(uint32_t *desc_addr, sec_out32((uint32_t *)&desc_addr[i], desc_word); } - phys_addr_t desc_phys_addr = virt_to_phys(desc_addr); + caam_dma_addr_t desc_phys_addr = virt_to_phys(desc_addr); jr->info[head].desc_phys_addr = desc_phys_addr; jr->info[head].callback = (void *)callback; @@ -223,7 +223,7 @@ static int jr_enqueue(uint32_t *desc_addr, sizeof(struct jr_info), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); -#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) +#ifdef CONFIG_CAAM_64BIT /* Write the 64 bit Descriptor address on Input Ring. * The 32 bit hign and low part of the address will * depend on endianness of SEC block. @@ -242,11 +242,11 @@ static int jr_enqueue(uint32_t *desc_addr, #else /* Write the 32 bit Descriptor address on Input Ring. */ sec_out32(&jr->input_ring[head], desc_phys_addr); -#endif /* ifdef CONFIG_PHYS_64BIT */ +#endif /* ifdef CONFIG_CAAM_64BIT */ start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1); end = ALIGN((unsigned long)&jr->input_ring[head] + - sizeof(dma_addr_t), ARCH_DMA_MINALIGN); + sizeof(caam_dma_addr_t), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); jr->head = (head + 1) & (jr->size - 1); @@ -272,7 +272,7 @@ static int jr_dequeue(int sec_idx) int idx, i, found; void (*callback)(uint32_t status, void *arg); void *arg = NULL; -#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) +#ifdef CONFIG_CAAM_64BIT uint32_t *addr_hi, *addr_lo; #else uint32_t *addr; @@ -283,8 +283,8 @@ static int jr_dequeue(int sec_idx) found = 0; - phys_addr_t op_desc; - #if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) + caam_dma_addr_t op_desc; + #ifdef CONFIG_CAAM_64BIT /* Read the 64 bit Descriptor address from Output Ring. * The 32 bit hign and low part of the address will * depend on endianness of SEC block. @@ -304,7 +304,7 @@ static int jr_dequeue(int sec_idx) /* Read the 32 bit Descriptor address from Output Ring. */ addr = (uint32_t *)&jr->output_ring[jr->tail].desc; op_desc = sec_in32(addr); - #endif /* ifdef CONFIG_PHYS_64BIT */ + #endif /* ifdef CONFIG_CAAM_64BIT */ uint32_t status = sec_in32(&jr->output_ring[jr->tail].status); @@ -678,7 +678,7 @@ int sec_init_idx(uint8_t sec_idx) mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); #endif -#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) +#ifdef CONFIG_CAAM_64BIT mcr |= (1 << MCFGR_PS_SHIFT); #endif sec_out32(&sec->mcfgr, mcr); diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 92566dd2d6..1047aa772c 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. - * Copyright 2018 NXP * */ @@ -9,6 +8,7 @@ #define __JR_H #include +#include "type.h" #define JR_SIZE 4 /* Timeout currently defined as 10 sec */ @@ -42,13 +42,13 @@ #define RNG4_MAX_HANDLES 2 struct op_ring { - u32 desc; - u32 status; + caam_dma_addr_t desc; + uint32_t status; } __packed; struct jr_info { void (*callback)(uint32_t status, void *arg); - phys_addr_t desc_phys_addr; + caam_dma_addr_t desc_phys_addr; uint32_t desc_len; uint32_t op_done; void *arg; @@ -84,7 +84,7 @@ struct jobring { * by SEC */ /*Circular Ring of i/p descriptors */ - u32 *input_ring; + caam_dma_addr_t *input_ring; /* Circular Ring of o/p descriptors */ /* Circula Ring containing info regarding descriptors in i/p * and o/p ring diff --git a/drivers/crypto/fsl/type.h b/drivers/crypto/fsl/type.h new file mode 100644 index 0000000000..b7031a60fd --- /dev/null +++ b/drivers/crypto/fsl/type.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + * + */ + +#ifndef CRYPTO_FSL_TYPE_H +#define CRYPTO_FSL_TYPE_H + +#ifdef CONFIG_CAAM_64BIT +typedef unsigned long long caam_dma_addr_t; +#else +typedef u32 caam_dma_addr_t; +#endif + +#endif From 8996e6b7c6a102232bed6b31f73936f59b5541b1 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 6 Apr 2021 11:58:57 +0800 Subject: [PATCH 061/117] imx8mm_evk: switch to use binman to pack images Use binman to pack images Signed-off-by: Peng Fan --- arch/arm/dts/imx8mm-evk-u-boot.dtsi | 106 ++++++++++++++++++ arch/arm/mach-imx/imx8m/Kconfig | 1 + .../imx8mm_evk/imximage-8mm-lpddr4.cfg | 9 ++ configs/imx8mm_evk_defconfig | 4 +- 4 files changed, 118 insertions(+), 2 deletions(-) create mode 100644 board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index 6d204526af..495bef3d38 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -4,6 +4,10 @@ */ / { + binman: binman { + multiple-images; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; @@ -144,3 +148,105 @@ &wdog1 { u-boot,dm-spl; }; + +&binman { + u-boot-spl-ddr { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; + + u-boot-spl { + align-end = <4>; + }; + + blob_1: blob-ext@1 { + filename = "lpddr4_pmu_train_1d_imem.bin"; + size = <0x8000>; + }; + + blob_2: blob-ext@2 { + filename = "lpddr4_pmu_train_1d_dmem.bin"; + size = <0x4000>; + }; + + blob_3: blob-ext@3 { + filename = "lpddr4_pmu_train_2d_imem.bin"; + size = <0x8000>; + }; + + blob_4: blob-ext@4 { + filename = "lpddr4_pmu_train_2d_dmem.bin"; + size = <0x4000>; + }; + }; + + + flash { + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; + + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load ATF before U-Boot"; + #address-cells = <1>; + fit,external-offset = ; + + images { + uboot { + description = "U-Boot (64-bit)"; + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = ; + + uboot_blob: blob-ext { + filename = "u-boot-nodtb.bin"; + }; + }; + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x920000>; + entry = <0x920000>; + + atf_blob: blob-ext { + filename = "bl31.bin"; + }; + }; + + fdt { + description = "NAME"; + type = "flat_dt"; + compression = "none"; + + uboot_fdt_blob: blob-ext { + filename = "u-boot.dtb"; + }; + }; + }; + + configurations { + default = "conf"; + + conf { + description = "NAME"; + firmware = "uboot"; + loadables = "atf"; + fdt = "fdt"; + }; + }; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index e7e1315bac..d9a99e9ccb 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -40,6 +40,7 @@ config TARGET_IMX8MQ_PHANBELL config TARGET_IMX8MM_EVK bool "imx8mm LPDDR4 EVK board" + select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 diff --git a/board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg b/board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg new file mode 100644 index 0000000000..b89092a559 --- /dev/null +++ b/board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#define __ASSEMBLY__ + +BOOT_FROM sd +LOADER mkimage.flash.mkimage 0x7E1000 diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index ae9e0626dd..23741a1c8a 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -21,9 +21,9 @@ CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y From a505fd3cc69e7c5af841cab92742f3ffc92d39ec Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 6 Apr 2021 11:58:58 +0800 Subject: [PATCH 062/117] doc: imx8mm_evk: update doc after using binman Update doc after switch to binman to pack images Signed-off-by: Peng Fan --- doc/board/freescale/imx8mm_evk.rst | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/doc/board/freescale/imx8mm_evk.rst b/doc/board/freescale/imx8mm_evk.rst index a9ccdb7850..7fd3d72564 100644 --- a/doc/board/freescale/imx8mm_evk.rst +++ b/doc/board/freescale/imx8mm_evk.rst @@ -43,13 +43,14 @@ Build U-Boot $ export CROSS_COMPILE=aarch64-poky-linux- $ make imx8mm_evk_defconfig $ export ATF_LOAD_ADDR=0x920000 - $ make flash.bin + $ make Burn the flash.bin to MicroSD card offset 33KB: .. code-block:: bash $sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 conv=notrunc + $sudo dd if=u-boot.itb of=/dev/sdc bs=1024 seek=384 conv=sync Boot ---- From 353dfe4b4359de2f18bf35ccffe5d85bd5ff8924 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 6 Apr 2021 11:58:59 +0800 Subject: [PATCH 063/117] imx8mn-ddr4-evk: switch to use binman Use binman to pack images Signed-off-by: Peng Fan --- arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 106 ++++++++++++++++++ arch/arm/mach-imx/imx8m/Kconfig | 1 + .../imx8mn_evk/imximage-8mn-ddr4.cfg | 10 ++ configs/imx8mn_ddr4_evk_defconfig | 4 +- 4 files changed, 119 insertions(+), 2 deletions(-) create mode 100644 board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index a0fd2a3098..1d3844437d 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -4,6 +4,10 @@ */ / { + binman: binman { + multiple-images; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; @@ -119,3 +123,105 @@ &wdog1 { u-boot,dm-spl; }; + +&binman { + u-boot-spl-ddr { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; + + u-boot-spl { + align-end = <4>; + }; + + blob_1: blob-ext@1 { + filename = "ddr4_imem_1d_201810.bin"; + size = <0x8000>; + }; + + blob_2: blob-ext@2 { + filename = "ddr4_dmem_1d_201810.bin"; + size = <0x4000>; + }; + + blob_3: blob-ext@3 { + filename = "ddr4_imem_2d_201810.bin"; + size = <0x8000>; + }; + + blob_4: blob-ext@4 { + filename = "ddr4_dmem_2d_201810.bin"; + size = <0x4000>; + }; + }; + + + flash { + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; + + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load ATF before U-Boot"; + #address-cells = <1>; + fit,external-offset = ; + + images { + uboot { + description = "U-Boot (64-bit)"; + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = ; + + uboot_blob: blob-ext { + filename = "u-boot-nodtb.bin"; + }; + }; + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x960000>; + entry = <0x960000>; + + atf_blob: blob-ext { + filename = "bl31.bin"; + }; + }; + + fdt { + description = "NAME"; + type = "flat_dt"; + compression = "none"; + + uboot_fdt_blob: blob-ext { + filename = "u-boot.dtb"; + }; + }; + }; + + configurations { + default = "conf"; + + conf { + description = "NAME"; + firmware = "uboot"; + loadables = "atf"; + fdt = "fdt"; + }; + }; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index d9a99e9ccb..be697bddfa 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -59,6 +59,7 @@ config TARGET_IMX8MN_EVK config TARGET_IMX8MN_DDR4_EVK bool "imx8mn DDR4 EVK board" + select BINMAN select IMX8MN select SUPPORT_SPL select IMX8M_DDR4 diff --git a/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg b/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg new file mode 100644 index 0000000000..22aec26da7 --- /dev/null +++ b/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#define __ASSEMBLY__ + +ROM_VERSION v2 +BOOT_FROM sd +LOADER mkimage.flash.mkimage 0x912000 diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 2c12bdabe0..b10cd13fc3 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -22,9 +22,9 @@ CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk" CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-ddr4.cfg" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg" CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y From d6afc6b3a04aaf3f7494d3510c401bbde4db2ca0 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 6 Apr 2021 11:59:00 +0800 Subject: [PATCH 064/117] imx8mn-evk: switch to use binman Use binman to pack images. Signed-off-by: Peng Fan --- arch/arm/dts/imx8mn-evk-u-boot.dtsi | 102 ++++++++++++++++++++++++++++ arch/arm/mach-imx/imx8m/Kconfig | 1 + configs/imx8mn_evk_defconfig | 4 +- 3 files changed, 105 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-evk-u-boot.dtsi index 2730ff6a81..3db46d4cbc 100644 --- a/arch/arm/dts/imx8mn-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-evk-u-boot.dtsi @@ -24,3 +24,105 @@ &pinctrl_pmic { u-boot,dm-spl; }; + +&binman { + u-boot-spl-ddr { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; + + u-boot-spl { + align-end = <4>; + }; + + blob_1: blob-ext@1 { + filename = "lpddr4_pmu_train_1d_imem.bin"; + size = <0x8000>; + }; + + blob_2: blob-ext@2 { + filename = "lpddr4_pmu_train_1d_dmem.bin"; + size = <0x4000>; + }; + + blob_3: blob-ext@3 { + filename = "lpddr4_pmu_train_2d_imem.bin"; + size = <0x8000>; + }; + + blob_4: blob-ext@4 { + filename = "lpddr4_pmu_train_2d_dmem.bin"; + size = <0x4000>; + }; + }; + + + flash { + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; + + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load ATF before U-Boot"; + #address-cells = <1>; + fit,external-offset = ; + + images { + uboot { + description = "U-Boot (64-bit)"; + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = ; + + uboot_blob: blob-ext { + filename = "u-boot-nodtb.bin"; + }; + }; + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x960000>; + entry = <0x960000>; + + atf_blob: blob-ext { + filename = "bl31.bin"; + }; + }; + + fdt { + description = "NAME"; + type = "flat_dt"; + compression = "none"; + + uboot_fdt_blob: blob-ext { + filename = "u-boot.dtb"; + }; + }; + }; + + configurations { + default = "conf"; + + conf { + description = "NAME"; + firmware = "uboot"; + loadables = "atf"; + fdt = "fdt"; + }; + }; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index be697bddfa..390ead9444 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -53,6 +53,7 @@ config TARGET_IMX8MM_VENICE config TARGET_IMX8MN_EVK bool "imx8mn LPDDR4 EVK board" + select BINMAN select IMX8MN select SUPPORT_SPL select IMX8M_LPDDR4 diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index c53dc968c8..d0e5b58902 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -25,9 +25,9 @@ CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk" CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg" CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y From 1ba917e150a3bed83a07c4d3db5e1fd1338d4878 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 6 Apr 2021 11:59:01 +0800 Subject: [PATCH 065/117] doc: imx8mn_evk: update doc after using binman Update doc after using binman to pack images Signed-off-by: Peng Fan --- doc/board/freescale/imx8mn_evk.rst | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/doc/board/freescale/imx8mn_evk.rst b/doc/board/freescale/imx8mn_evk.rst index 375e0bb761..9fbb947032 100644 --- a/doc/board/freescale/imx8mn_evk.rst +++ b/doc/board/freescale/imx8mn_evk.rst @@ -43,13 +43,14 @@ Build U-Boot $ export CROSS_COMPILE=aarch64-poky-linux- $ make imx8mn_ddr4_evk_defconfig $ export ATF_LOAD_ADDR=0x960000 - $ make flash.bin + $ make Burn the flash.bin to MicroSD card offset 32KB: .. code-block:: bash $sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc + $sudo dd if=u-boot.itb of=/dev/sd[x] bs=1024 seek=384 conv=notrunc Boot ---- From 1e4ed2d69d6e7bea8b08e2c24a9d3c0228ee1c4e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 6 Apr 2021 11:59:02 +0800 Subject: [PATCH 066/117] imx8mp-evk: switch to use binman Use binman to pack images Signed-off-by: Peng Fan --- arch/arm/dts/imx8mp-evk-u-boot.dtsi | 106 ++++++++++++++++++ arch/arm/mach-imx/imx8m/Kconfig | 1 + .../imx8mp_evk/imximage-8mp-lpddr4.cfg | 10 ++ configs/imx8mp_evk_defconfig | 4 +- 4 files changed, 119 insertions(+), 2 deletions(-) create mode 100644 board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 27075c5217..4162f41cff 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -4,6 +4,10 @@ */ / { + binman: binman { + multiple-images; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; @@ -151,3 +155,105 @@ phy-reset-duration = <15>; phy-reset-post-delay = <100>; }; + +&binman { + u-boot-spl-ddr { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; + + u-boot-spl { + align-end = <4>; + }; + + blob_1: blob-ext@1 { + filename = "lpddr4_pmu_train_1d_imem_202006.bin"; + size = <0x8000>; + }; + + blob_2: blob-ext@2 { + filename = "lpddr4_pmu_train_1d_dmem_202006.bin"; + size = <0x4000>; + }; + + blob_3: blob-ext@3 { + filename = "lpddr4_pmu_train_2d_imem_202006.bin"; + size = <0x8000>; + }; + + blob_4: blob-ext@4 { + filename = "lpddr4_pmu_train_2d_dmem_202006.bin"; + size = <0x4000>; + }; + }; + + + flash { + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x920000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; + + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load ATF before U-Boot"; + #address-cells = <1>; + fit,external-offset = ; + + images { + uboot { + description = "U-Boot (64-bit)"; + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = ; + + uboot_blob: blob-ext { + filename = "u-boot-nodtb.bin"; + }; + }; + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x970000>; + entry = <0x970000>; + + atf_blob: blob-ext { + filename = "bl31.bin"; + }; + }; + + fdt { + description = "NAME"; + type = "flat_dt"; + compression = "none"; + + uboot_fdt_blob: blob-ext { + filename = "u-boot.dtb"; + }; + }; + }; + + configurations { + default = "conf"; + + conf { + description = "NAME"; + firmware = "uboot"; + loadables = "atf"; + fdt = "fdt"; + }; + }; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 390ead9444..c27fb248d1 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -67,6 +67,7 @@ config TARGET_IMX8MN_DDR4_EVK config TARGET_IMX8MP_EVK bool "imx8mp LPDDR4 EVK board" + select BINMAN select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 diff --git a/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg b/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg new file mode 100644 index 0000000000..b2920b4908 --- /dev/null +++ b/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#define __ASSEMBLY__ + +ROM_VERSION v2 +BOOT_FROM sd +LOADER mkimage.flash.mkimage 0x920000 diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 47a52eedb9..089ec26b3c 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -22,9 +22,9 @@ CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg" CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y From 8a78e31d73d4392774b31497ae83203b27e5c37d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 6 Apr 2021 11:59:03 +0800 Subject: [PATCH 067/117] doc: imx8mp-evk: update after using binman update doc after using binman to pack images Signed-off-by: Peng Fan --- doc/board/freescale/imx8mp_evk.rst | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/doc/board/freescale/imx8mp_evk.rst b/doc/board/freescale/imx8mp_evk.rst index 796a7611d0..609a29f3eb 100644 --- a/doc/board/freescale/imx8mp_evk.rst +++ b/doc/board/freescale/imx8mp_evk.rst @@ -40,18 +40,19 @@ Build U-Boot $ export CROSS_COMPILE=aarch64-poky-linux- $ make O=build imx8mp_evk_defconfig $ cp ../imx-atf/build/imx8mp/release/bl31.bin ./build/bl31.bin - $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_202006.bin ./build/lpddr4_pmu_train_1d_dmem.bin - $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_202006.bin ./build/lpddr4_pmu_train_1d_imem.bin - $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_202006.bin ./build/lpddr4_pmu_train_2d_dmem.bin - $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_202006.bin ./build/lpddr4_pmu_train_2d_imem.bin + $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_202006.bin ./build/ + $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_202006.bin ./build/ + $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_202006.bin ./build/ + $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_202006.bin ./build/ $ export ATF_LOAD_ADDR=0x970000 - $ make O=build flash.bin + $ make O=build Burn the flash.bin to the MicroSD card at offset 32KB: .. code-block:: bash $sudo dd if=build/flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync + $sudo dd if=build/u-boot.itb of=/dev/sd[x] bs=1K seek=384 conv=notrunc; sync Boot ---- From 09d86eab149ccaa387f0061521179605a600a9c3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 25 Feb 2021 21:52:26 +0100 Subject: [PATCH 068/117] ARM: imx: Add OCRAM_S into iMX8M MMU tables The OCRAM_S is regular memory, just like the OCRAM, add it to the MMU tables so it can be used and cached. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic --- arch/arm/mach-imx/imx8m/soc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index f3b9f2ddd6..36abb2e57f 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -104,6 +104,13 @@ static struct mm_region imx8m_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* OCRAM_S */ + .virt = 0x180000UL, + .phys = 0x180000UL, + .size = 0x8000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE }, { /* TCM */ .virt = 0x7C0000UL, From 39cb85043cdbc98d10b49f0b86596043d5f8e3f8 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 1 Mar 2021 14:33:27 -0800 Subject: [PATCH 069/117] spl: fit: nand: skip bad block handling if NAND chip not fully defined commit 9f6a14c47ff9 ("spl: fit: nand: fix fit loading in case of bad blocks") added support for adjusting the image offset to account for bad blocks. However this requires nand_spl_adjust_offset() which requires fully defined specifics of the NAND chip being used may not be avialable. Allow skipping this support for drivers or configs which don't specify the NAND chip details statically with defines. Signed-off-by: Tim Harvey Reviewed-by: Tom Rini --- common/spl/spl_nand.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index d13a524597..8213836df4 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -42,11 +42,13 @@ static int spl_nand_load_image(struct spl_image_info *spl_image, static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs, ulong size, void *dst) { - ulong sector; int err; +#ifdef CONFIG_SYS_NAND_BLOCK_SIZE + ulong sector; sector = *(int *)load->priv; offs = sector + nand_spl_adjust_offset(sector, offs - sector); +#endif err = nand_spl_load_image(offs, size, dst); if (err) return 0; From aa0032f67267232c6b315b5f6e1c086c217c9aae Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 1 Mar 2021 14:33:28 -0800 Subject: [PATCH 070/117] spl: fit: nand: allow for non-page-aligned elements Add a weak nand_get_mtd function for nand drivers to provide mtd info and use this to set pagesize such that reading of non page-aligned elements can succeed. The spl_load_simple_fit already handles block block access so all we need to do is provide the nand writesize as the block length. Further cleanup of the drivers which use nand_spl_loaders.c such as am335x_spl_bch.c, atmel_nand.c, and nand_spl_simple.c could be done using info from mtd_info instead of statically defined details. Signed-off-by: Tim Harvey Reviewed-by: Tom Rini --- common/spl/spl_nand.c | 20 +++++++++++++++----- drivers/mtd/nand/raw/mxs_nand_spl.c | 5 +++++ 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 8213836df4..59f4a84a36 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -48,17 +48,27 @@ static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs, sector = *(int *)load->priv; offs = sector + nand_spl_adjust_offset(sector, offs - sector); +#else + offs *= load->bl_len; + size *= load->bl_len; #endif err = nand_spl_load_image(offs, size, dst); if (err) return 0; - return size; + return size / load->bl_len; +} + +struct mtd_info * __weak nand_get_mtd(void) +{ + return NULL; } static int spl_nand_load_element(struct spl_image_info *spl_image, int offset, struct image_header *header) { + struct mtd_info *mtd = nand_get_mtd(); + int bl_len = mtd ? mtd->writesize : 1; int err; err = nand_spl_load_image(offset, sizeof(*header), (void *)header); @@ -73,18 +83,18 @@ static int spl_nand_load_element(struct spl_image_info *spl_image, load.dev = NULL; load.priv = &offset; load.filename = NULL; - load.bl_len = 1; + load.bl_len = bl_len; load.read = spl_nand_fit_read; - return spl_load_simple_fit(spl_image, &load, offset, header); + return spl_load_simple_fit(spl_image, &load, offset / bl_len, header); } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) { struct spl_load_info load; load.dev = NULL; load.priv = NULL; load.filename = NULL; - load.bl_len = 1; + load.bl_len = bl_len; load.read = spl_nand_fit_read; - return spl_load_imx_container(spl_image, &load, offset); + return spl_load_imx_container(spl_image, &load, offset / bl_len); } else { err = spl_parse_image_header(spl_image, header); if (err) diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index 46dc29df36..17f46ae5e9 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -282,6 +282,11 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) return 0; } +struct mtd_info *nand_get_mtd(void) +{ + return mtd; +} + int nand_default_bbt(struct mtd_info *mtd) { return 0; From d331cee596d20b64dac0c3be9cafeaab9c4bda3f Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 1 Mar 2021 14:33:29 -0800 Subject: [PATCH 071/117] dt-bindings: add tda1997x and bindings Add td1997x header from Linux to be included by dts files. Signed-off-by: Tim Harvey --- include/dt-bindings/media/tda1997x.h | 74 ++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 include/dt-bindings/media/tda1997x.h diff --git a/include/dt-bindings/media/tda1997x.h b/include/dt-bindings/media/tda1997x.h new file mode 100644 index 0000000000..bd9fbd718e --- /dev/null +++ b/include/dt-bindings/media/tda1997x.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017 Gateworks Corporation + */ +#ifndef _DT_BINDINGS_MEDIA_TDA1997X_H +#define _DT_BINDINGS_MEDIA_TDA1997X_H + +/* TDA19973 36bit Video Port control registers */ +#define TDA1997X_VP36_35_32 0 +#define TDA1997X_VP36_31_28 1 +#define TDA1997X_VP36_27_24 2 +#define TDA1997X_VP36_23_20 3 +#define TDA1997X_VP36_19_16 4 +#define TDA1997X_VP36_15_12 5 +#define TDA1997X_VP36_11_08 6 +#define TDA1997X_VP36_07_04 7 +#define TDA1997X_VP36_03_00 8 + +/* TDA19971 24bit Video Port control registers */ +#define TDA1997X_VP24_V23_20 0 +#define TDA1997X_VP24_V19_16 1 +#define TDA1997X_VP24_V15_12 3 +#define TDA1997X_VP24_V11_08 4 +#define TDA1997X_VP24_V07_04 6 +#define TDA1997X_VP24_V03_00 7 + +/* Pin groups */ +#define TDA1997X_VP_OUT_EN 0x80 /* enable output group */ +#define TDA1997X_VP_HIZ 0x40 /* hi-Z output group when not used */ +#define TDA1997X_VP_SWP 0x10 /* pin-swap output group */ +#define TDA1997X_R_CR_CBCR_3_0 (0 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_R_CR_CBCR_7_4 (1 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_R_CR_CBCR_11_8 (2 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_B_CB_3_0 (3 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_B_CB_7_4 (4 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_B_CB_11_8 (5 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_G_Y_3_0 (6 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_G_Y_7_4 (7 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_G_Y_11_8 (8 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +/* pinswapped groups */ +#define TDA1997X_R_CR_CBCR_3_0_S (TDA1997X_R_CR_CBCR_3_0 | TDA1997X_VP_SWAP) +#define TDA1997X_R_CR_CBCR_7_4_S (TDA1997X_R_CR_CBCR_7_4 | TDA1997X_VP_SWAP) +#define TDA1997X_R_CR_CBCR_11_8_S (TDA1997X_R_CR_CBCR_11_8 | TDA1997X_VP_SWAP) +#define TDA1997X_B_CB_3_0_S (TDA1997X_B_CB_3_0 | TDA1997X_VP_SWAP) +#define TDA1997X_B_CB_7_4_S (TDA1997X_B_CB_7_4 | TDA1997X_VP_SWAP) +#define TDA1997X_B_CB_11_8_S (TDA1997X_B_CB_11_8 | TDA1997X_VP_SWAP) +#define TDA1997X_G_Y_3_0_S (TDA1997X_G_Y_3_0 | TDA1997X_VP_SWAP) +#define TDA1997X_G_Y_7_4_S (TDA1997X_G_Y_7_4 | TDA1997X_VP_SWAP) +#define TDA1997X_G_Y_11_8_S (TDA1997X_G_Y_11_8 | TDA1997X_VP_SWAP) + +/* Audio bus DAI format */ +#define TDA1997X_I2S16 1 /* I2S 16bit */ +#define TDA1997X_I2S32 2 /* I2S 32bit */ +#define TDA1997X_SPDIF 3 /* SPDIF */ +#define TDA1997X_OBA 4 /* One Bit Audio */ +#define TDA1997X_DST 5 /* Direct Stream Transfer */ +#define TDA1997X_I2S16_HBR 6 /* HBR straight in I2S 16bit mode */ +#define TDA1997X_I2S16_HBR_DEMUX 7 /* HBR demux in I2S 16bit mode */ +#define TDA1997X_I2S32_HBR_DEMUX 8 /* HBR demux in I2S 32bit mode */ +#define TDA1997X_SPDIF_HBR_DEMUX 9 /* HBR demux in SPDIF mode */ + +/* Audio bus channel layout */ +#define TDA1997X_LAYOUT0 0 /* 2-channel */ +#define TDA1997X_LAYOUT1 1 /* 8-channel */ + +/* Audio bus clock */ +#define TDA1997X_ACLK_16FS 0 +#define TDA1997X_ACLK_32FS 1 +#define TDA1997X_ACLK_64FS 2 +#define TDA1997X_ACLK_128FS 3 +#define TDA1997X_ACLK_256FS 4 +#define TDA1997X_ACLK_512FS 5 + +#endif /* _DT_BINDINGS_MEDIA_TDA1997X_H */ From acb9a13b50db24a6ef17f4c2bd600a0f5d9fec1f Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 1 Mar 2021 14:33:30 -0800 Subject: [PATCH 072/117] imx: ventana: add Gateworks Ventana dts Add Gateworks Ventana dts/dtsi files from Linux 5.11 in preparation for conversion to driver-model. Signed-off-by: Tim Harvey --- arch/arm/dts/Makefile | 28 + arch/arm/dts/imx6dl-gw51xx.dts | 13 + arch/arm/dts/imx6dl-gw52xx.dts | 71 ++ arch/arm/dts/imx6dl-gw53xx.dts | 71 ++ arch/arm/dts/imx6dl-gw54xx.dts | 71 ++ arch/arm/dts/imx6dl-gw551x.dts | 55 ++ arch/arm/dts/imx6dl-gw552x.dts | 14 + arch/arm/dts/imx6dl-gw553x.dts | 55 ++ arch/arm/dts/imx6dl-gw560x.dts | 55 ++ arch/arm/dts/imx6dl-gw5903.dts | 55 ++ arch/arm/dts/imx6dl-gw5904.dts | 55 ++ arch/arm/dts/imx6dl-gw5907.dts | 14 + arch/arm/dts/imx6dl-gw5910.dts | 14 + arch/arm/dts/imx6dl-gw5912.dts | 13 + arch/arm/dts/imx6dl-gw5913.dts | 14 + arch/arm/dts/imx6q-gw51xx.dts | 13 + arch/arm/dts/imx6q-gw52xx.dts | 75 ++ arch/arm/dts/imx6q-gw53xx.dts | 75 ++ arch/arm/dts/imx6q-gw54xx.dts | 177 +++++ arch/arm/dts/imx6q-gw551x.dts | 55 ++ arch/arm/dts/imx6q-gw552x.dts | 18 + arch/arm/dts/imx6q-gw553x.dts | 55 ++ arch/arm/dts/imx6q-gw560x.dts | 59 ++ arch/arm/dts/imx6q-gw5903.dts | 55 ++ arch/arm/dts/imx6q-gw5904.dts | 59 ++ arch/arm/dts/imx6q-gw5907.dts | 14 + arch/arm/dts/imx6q-gw5910.dts | 14 + arch/arm/dts/imx6q-gw5912.dts | 13 + arch/arm/dts/imx6q-gw5913.dts | 14 + arch/arm/dts/imx6qdl-gw51xx.dtsi | 637 +++++++++++++++++ arch/arm/dts/imx6qdl-gw52xx.dtsi | 780 +++++++++++++++++++++ arch/arm/dts/imx6qdl-gw53xx.dtsi | 770 ++++++++++++++++++++ arch/arm/dts/imx6qdl-gw54xx.dtsi | 864 +++++++++++++++++++++++ arch/arm/dts/imx6qdl-gw551x.dtsi | 697 ++++++++++++++++++ arch/arm/dts/imx6qdl-gw552x.dtsi | 521 ++++++++++++++ arch/arm/dts/imx6qdl-gw553x.dtsi | 737 +++++++++++++++++++ arch/arm/dts/imx6qdl-gw560x.dtsi | 934 +++++++++++++++++++++++++ arch/arm/dts/imx6qdl-gw5903.dtsi | 795 +++++++++++++++++++++ arch/arm/dts/imx6qdl-gw5904.dtsi | 812 +++++++++++++++++++++ arch/arm/dts/imx6qdl-gw5907.dtsi | 538 ++++++++++++++ arch/arm/dts/imx6qdl-gw5910.dtsi | 666 ++++++++++++++++++ arch/arm/dts/imx6qdl-gw5912.dtsi | 608 ++++++++++++++++ arch/arm/dts/imx6qdl-gw5913.dtsi | 500 +++++++++++++ board/gateworks/gw_ventana/MAINTAINERS | 48 ++ 44 files changed, 11201 insertions(+) create mode 100644 arch/arm/dts/imx6dl-gw51xx.dts create mode 100644 arch/arm/dts/imx6dl-gw52xx.dts create mode 100644 arch/arm/dts/imx6dl-gw53xx.dts create mode 100644 arch/arm/dts/imx6dl-gw54xx.dts create mode 100644 arch/arm/dts/imx6dl-gw551x.dts create mode 100644 arch/arm/dts/imx6dl-gw552x.dts create mode 100644 arch/arm/dts/imx6dl-gw553x.dts create mode 100644 arch/arm/dts/imx6dl-gw560x.dts create mode 100644 arch/arm/dts/imx6dl-gw5903.dts create mode 100644 arch/arm/dts/imx6dl-gw5904.dts create mode 100644 arch/arm/dts/imx6dl-gw5907.dts create mode 100644 arch/arm/dts/imx6dl-gw5910.dts create mode 100644 arch/arm/dts/imx6dl-gw5912.dts create mode 100644 arch/arm/dts/imx6dl-gw5913.dts create mode 100644 arch/arm/dts/imx6q-gw51xx.dts create mode 100644 arch/arm/dts/imx6q-gw52xx.dts create mode 100644 arch/arm/dts/imx6q-gw53xx.dts create mode 100644 arch/arm/dts/imx6q-gw54xx.dts create mode 100644 arch/arm/dts/imx6q-gw551x.dts create mode 100644 arch/arm/dts/imx6q-gw552x.dts create mode 100644 arch/arm/dts/imx6q-gw553x.dts create mode 100644 arch/arm/dts/imx6q-gw560x.dts create mode 100644 arch/arm/dts/imx6q-gw5903.dts create mode 100644 arch/arm/dts/imx6q-gw5904.dts create mode 100644 arch/arm/dts/imx6q-gw5907.dts create mode 100644 arch/arm/dts/imx6q-gw5910.dts create mode 100644 arch/arm/dts/imx6q-gw5912.dts create mode 100644 arch/arm/dts/imx6q-gw5913.dts create mode 100644 arch/arm/dts/imx6qdl-gw51xx.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw52xx.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw53xx.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw54xx.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw551x.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw552x.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw553x.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw560x.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw5903.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw5904.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw5907.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw5910.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw5912.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw5913.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a5e836e877..a643e45a0c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -673,6 +673,20 @@ dtb-y += \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ imx6dl-dhcom-pdk2.dtb \ + imx6dl-gw51xx.dtb \ + imx6dl-gw52xx.dtb \ + imx6dl-gw53xx.dtb \ + imx6dl-gw54xx.dtb \ + imx6dl-gw551x.dtb \ + imx6dl-gw552x.dtb \ + imx6dl-gw553x.dtb \ + imx6dl-gw560x.dtb \ + imx6dl-gw5903.dtb \ + imx6dl-gw5904.dtb \ + imx6dl-gw5907.dtb \ + imx6dl-gw5910.dtb \ + imx6dl-gw5912.dtb \ + imx6dl-gw5913.dtb \ imx6dl-hummingboard2.dtb \ imx6dl-hummingboard2-emmc-som-v15.dtb \ imx6dl-hummingboard2-som-v15.dtb \ @@ -702,6 +716,20 @@ dtb-y += \ imx6q-cubox-i-som-v15.dtb \ imx6q-dhcom-pdk2.dtb \ imx6q-display5.dtb \ + imx6q-gw51xx.dtb \ + imx6q-gw52xx.dtb \ + imx6q-gw53xx.dtb \ + imx6q-gw54xx.dtb \ + imx6q-gw551x.dtb \ + imx6q-gw552x.dtb \ + imx6q-gw553x.dtb \ + imx6q-gw560x.dtb \ + imx6q-gw5903.dtb \ + imx6q-gw5904.dtb \ + imx6q-gw5907.dtb \ + imx6q-gw5910.dtb \ + imx6q-gw5912.dtb \ + imx6q-gw5913.dtb \ imx6q-hummingboard2.dtb \ imx6q-hummingboard2-emmc-som-v15.dtb \ imx6q-hummingboard2-som-v15.dtb \ diff --git a/arch/arm/dts/imx6dl-gw51xx.dts b/arch/arm/dts/imx6dl-gw51xx.dts new file mode 100644 index 0000000000..9956d12a12 --- /dev/null +++ b/arch/arm/dts/imx6dl-gw51xx.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw51xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW51XX"; + compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6dl-gw52xx.dts b/arch/arm/dts/imx6dl-gw52xx.dts new file mode 100644 index 0000000000..9ea23dd54f --- /dev/null +++ b/arch/arm/dts/imx6dl-gw52xx.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw52xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW52XX"; + compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl"; +}; + +&i2c3 { + adv7180: camera@20 { + compatible = "adi,adv7180"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7180>; + reg = <0x20>; + powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu1_csi1_mux: endpoint { + remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; +}; + +&ipu1_csi1_from_ipu1_csi1_mux { + bus-width = <8>; +}; + +&ipu1_csi1_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; + bus-width = <8>; +}; + +&ipu1_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi1>; +}; + +&iomuxc { + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 + >; + }; + + pinctrl_ipu1_csi1: ipu1_csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 + MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 + MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 + MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-gw53xx.dts b/arch/arm/dts/imx6dl-gw53xx.dts new file mode 100644 index 0000000000..182e8194c2 --- /dev/null +++ b/arch/arm/dts/imx6dl-gw53xx.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw53xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX"; + compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl"; +}; + +&i2c3 { + adv7180: camera@20 { + compatible = "adi,adv7180"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7180>; + reg = <0x20>; + powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu1_csi1_mux: endpoint { + remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; +}; + +&ipu1_csi1_from_ipu1_csi1_mux { + bus-width = <8>; +}; + +&ipu1_csi1_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; + bus-width = <8>; +}; + +&ipu1_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi1>; +}; + +&iomuxc { + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 + >; + }; + + pinctrl_ipu1_csi1: ipu1_csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 + MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 + MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 + MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-gw54xx.dts b/arch/arm/dts/imx6dl-gw54xx.dts new file mode 100644 index 0000000000..a106c4e3e3 --- /dev/null +++ b/arch/arm/dts/imx6dl-gw54xx.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw54xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW54XX"; + compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl"; +}; + +&i2c3 { + adv7180: camera@20 { + compatible = "adi,adv7180"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7180>; + reg = <0x20>; + powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu1_csi1_mux: endpoint { + remote-endpoint = <&ipu1_csi1_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; +}; + +&ipu1_csi1_from_ipu1_csi1_mux { + bus-width = <8>; +}; + +&ipu1_csi1_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; + bus-width = <8>; +}; + +&ipu1_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi1>; +}; + +&iomuxc { + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 + >; + }; + + pinctrl_ipu1_csi1: ipu1_csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b0 + MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b0 + MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b0 + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b0 + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b0 + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b0 + MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-gw551x.dts b/arch/arm/dts/imx6dl-gw551x.dts new file mode 100644 index 0000000000..82d5f85722 --- /dev/null +++ b/arch/arm/dts/imx6dl-gw551x.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2014 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw551x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW551X"; + compatible = "gw,imx6dl-gw551x", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6dl-gw552x.dts b/arch/arm/dts/imx6dl-gw552x.dts new file mode 100644 index 0000000000..4864a36f9b --- /dev/null +++ b/arch/arm/dts/imx6dl-gw552x.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2014 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-gw552x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW552X"; + compatible = "gw,imx6dl-gw552x", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6dl-gw553x.dts b/arch/arm/dts/imx6dl-gw553x.dts new file mode 100644 index 0000000000..59b8afc36e --- /dev/null +++ b/arch/arm/dts/imx6dl-gw553x.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2016 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw553x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW553X"; + compatible = "gw,imx6dl-gw553x", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6dl-gw560x.dts b/arch/arm/dts/imx6dl-gw560x.dts new file mode 100644 index 0000000000..21bdfaf8df --- /dev/null +++ b/arch/arm/dts/imx6dl-gw560x.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw560x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW560X"; + compatible = "gw,imx6dl-gw560x", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6dl-gw5903.dts b/arch/arm/dts/imx6dl-gw5903.dts new file mode 100644 index 0000000000..103261ea93 --- /dev/null +++ b/arch/arm/dts/imx6dl-gw5903.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw5903.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Duallite/Solo GW5903"; + compatible = "gw,imx6dl-gw5903", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6dl-gw5904.dts b/arch/arm/dts/imx6dl-gw5904.dts new file mode 100644 index 0000000000..9c6d3cd3d6 --- /dev/null +++ b/arch/arm/dts/imx6dl-gw5904.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw5904.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5904"; + compatible = "gw,imx6dl-gw5904", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6dl-gw5907.dts b/arch/arm/dts/imx6dl-gw5907.dts new file mode 100644 index 0000000000..3fa2822bef --- /dev/null +++ b/arch/arm/dts/imx6dl-gw5907.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-gw5907.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5907"; + compatible = "gw,imx6dl-gw5907", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6dl-gw5910.dts b/arch/arm/dts/imx6dl-gw5910.dts new file mode 100644 index 0000000000..0d5e7e5da5 --- /dev/null +++ b/arch/arm/dts/imx6dl-gw5910.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-gw5910.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5910"; + compatible = "gw,imx6dl-gw5910", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6dl-gw5912.dts b/arch/arm/dts/imx6dl-gw5912.dts new file mode 100644 index 0000000000..5260e0142d --- /dev/null +++ b/arch/arm/dts/imx6dl-gw5912.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw5912.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5912"; + compatible = "gw,imx6dl-gw5912", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6dl-gw5913.dts b/arch/arm/dts/imx6dl-gw5913.dts new file mode 100644 index 0000000000..b74e533c8e --- /dev/null +++ b/arch/arm/dts/imx6dl-gw5913.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-gw5913.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5913"; + compatible = "gw,imx6dl-gw5913", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6q-gw51xx.dts b/arch/arm/dts/imx6q-gw51xx.dts new file mode 100644 index 0000000000..f80173458e --- /dev/null +++ b/arch/arm/dts/imx6q-gw51xx.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw51xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW51XX"; + compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q"; +}; diff --git a/arch/arm/dts/imx6q-gw52xx.dts b/arch/arm/dts/imx6q-gw52xx.dts new file mode 100644 index 0000000000..6e1c493c9c --- /dev/null +++ b/arch/arm/dts/imx6q-gw52xx.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw52xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW52XX"; + compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q"; +}; + +&i2c3 { + adv7180: camera@20 { + compatible = "adi,adv7180"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7180>; + reg = <0x20>; + powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu2_csi1_mux: endpoint { + remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; +}; + +&ipu2_csi1_from_ipu2_csi1_mux { + bus-width = <8>; +}; + +&ipu2_csi1_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; + bus-width = <8>; +}; + +&ipu2_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu2_csi1>; +}; + +&iomuxc { + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 + >; + }; + + pinctrl_ipu2_csi1: ipu2_csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 + MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 + MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 + MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 + MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 + >; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q-gw53xx.dts b/arch/arm/dts/imx6q-gw53xx.dts new file mode 100644 index 0000000000..f13df8e9c8 --- /dev/null +++ b/arch/arm/dts/imx6q-gw53xx.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw53xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW53XX"; + compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q"; +}; + +&i2c3 { + adv7180: camera@20 { + compatible = "adi,adv7180"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7180>; + reg = <0x20>; + powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu2_csi1_mux: endpoint { + remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; +}; + +&ipu2_csi1_from_ipu2_csi1_mux { + bus-width = <8>; +}; + +&ipu2_csi1_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; + bus-width = <8>; +}; + +&ipu2_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu2_csi1>; +}; + +&sata { + status = "okay"; +}; + +&iomuxc { + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 + >; + }; + + pinctrl_ipu2_csi1: ipu2_csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 + MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 + MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 + MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 + MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6q-gw54xx.dts b/arch/arm/dts/imx6q-gw54xx.dts new file mode 100644 index 0000000000..d5d46908cf --- /dev/null +++ b/arch/arm/dts/imx6q-gw54xx.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw54xx.dtsi" +#include + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX"; + compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q"; + + sound-digital { + compatible = "simple-audio-card"; + simple-audio-card,name = "tda1997x-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_codec>; + simple-audio-card,frame-master = <&sound_codec>; + + sound_cpu: simple-audio-card,cpu { + sound-dai = <&ssi2>; + }; + + sound_codec: simple-audio-card,codec { + sound-dai = <&hdmi_receiver>; + }; + }; +}; + +&i2c3 { + adv7180: camera@20 { + compatible = "adi,adv7180"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7180>; + reg = <0x20>; + powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu2_csi1_mux: endpoint { + remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; + + hdmi_receiver: hdmi-receiver@48 { + compatible = "nxp,tda19971"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tda1997x>; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + DOVDD-supply = <®_3p3v>; + AVDD-supply = <&sw4_reg>; + DVDD-supply = <&sw4_reg>; + #sound-dai-cells = <0>; + nxp,audout-format = "i2s"; + nxp,audout-layout = <0>; + nxp,audout-width = <16>; + nxp,audout-mclk-fs = <128>; + /* + * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] + * and Y[11:4] across 16bits in the same cycle + * which we map to VP[15:08]<->CSI_DATA[19:12] + */ + nxp,vidout-portcfg = + /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ + < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, + /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ + < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, + /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ + < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, + /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ + < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; + + port { + tda1997x_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <16>; + hsync-active = <1>; + vsync-active = <1>; + data-active = <1>; + }; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <16>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; + bus-width = <16>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; +}; + +&ipu2_csi1_from_ipu2_csi1_mux { + bus-width = <8>; +}; + +&ipu2_csi1_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; + bus-width = <8>; +}; + +&ipu2_csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu2_csi1>; +}; + +&sata { + status = "okay"; +}; + +&iomuxc { + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0 + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0 + >; + }; + + pinctrl_ipu1_csi0: ipu1_csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + + pinctrl_ipu2_csi1: ipu2_csi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0 + MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0 + MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0 + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0 + MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0 + MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 + >; + }; + + pinctrl_tda1997x: tda1997xgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6q-gw551x.dts b/arch/arm/dts/imx6q-gw551x.dts new file mode 100644 index 0000000000..2c7feeef1b --- /dev/null +++ b/arch/arm/dts/imx6q-gw551x.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2014 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw551x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW551X"; + compatible = "gw,imx6q-gw551x", "gw,ventana", "fsl,imx6q"; +}; diff --git a/arch/arm/dts/imx6q-gw552x.dts b/arch/arm/dts/imx6q-gw552x.dts new file mode 100644 index 0000000000..c973b73042 --- /dev/null +++ b/arch/arm/dts/imx6q-gw552x.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2014 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-gw552x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW552X"; + compatible = "gw,imx6q-gw552x", "gw,ventana", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q-gw553x.dts b/arch/arm/dts/imx6q-gw553x.dts new file mode 100644 index 0000000000..e9c224cea7 --- /dev/null +++ b/arch/arm/dts/imx6q-gw553x.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2016 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw553x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW553X"; + compatible = "gw,imx6q-gw553x", "gw,ventana", "fsl,imx6q"; +}; diff --git a/arch/arm/dts/imx6q-gw560x.dts b/arch/arm/dts/imx6q-gw560x.dts new file mode 100644 index 0000000000..735f2bbf14 --- /dev/null +++ b/arch/arm/dts/imx6q-gw560x.dts @@ -0,0 +1,59 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw560x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW560X"; + compatible = "gw,imx6q-gw560x", "gw,ventana", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q-gw5903.dts b/arch/arm/dts/imx6q-gw5903.dts new file mode 100644 index 0000000000..a182e4cb0e --- /dev/null +++ b/arch/arm/dts/imx6q-gw5903.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw5903.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW5903"; + compatible = "gw,imx6q-gw5903", "gw,ventana", "fsl,imx6q"; +}; diff --git a/arch/arm/dts/imx6q-gw5904.dts b/arch/arm/dts/imx6q-gw5904.dts new file mode 100644 index 0000000000..ca1e2ae334 --- /dev/null +++ b/arch/arm/dts/imx6q-gw5904.dts @@ -0,0 +1,59 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw5904.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW5904"; + compatible = "gw,imx6q-gw5904", "gw,ventana", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q-gw5907.dts b/arch/arm/dts/imx6q-gw5907.dts new file mode 100644 index 0000000000..b25526ef58 --- /dev/null +++ b/arch/arm/dts/imx6q-gw5907.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-gw5907.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW5907"; + compatible = "gw,imx6q-gw5907", "gw,ventana", "fsl,imx6q"; +}; diff --git a/arch/arm/dts/imx6q-gw5910.dts b/arch/arm/dts/imx6q-gw5910.dts new file mode 100644 index 0000000000..6aafa2fcee --- /dev/null +++ b/arch/arm/dts/imx6q-gw5910.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-gw5910.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW5910"; + compatible = "gw,imx6q-gw5910", "gw,ventana", "fsl,imx6q"; +}; diff --git a/arch/arm/dts/imx6q-gw5912.dts b/arch/arm/dts/imx6q-gw5912.dts new file mode 100644 index 0000000000..4dcbd943cd --- /dev/null +++ b/arch/arm/dts/imx6q-gw5912.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw5912.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW5912"; + compatible = "gw,imx6q-gw5912", "gw,ventana", "fsl,imx6q"; +}; diff --git a/arch/arm/dts/imx6q-gw5913.dts b/arch/arm/dts/imx6q-gw5913.dts new file mode 100644 index 0000000000..6f511f1665 --- /dev/null +++ b/arch/arm/dts/imx6q-gw5913.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-gw5913.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW5913"; + compatible = "gw,imx6q-gw5913", "gw,ventana", "fsl,imx6q"; +}; diff --git a/arch/arm/dts/imx6qdl-gw51xx.dtsi b/arch/arm/dts/imx6qdl-gw51xx.dtsi new file mode 100644 index 0000000000..3c04b5a4f3 --- /dev/null +++ b/arch/arm/dts/imx6qdl-gw51xx.dtsi @@ -0,0 +1,637 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + nand = &gpmi; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_an1"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_SOC (1+R1/R2 = 1.635) */ + reg_vdd_soc: sw1 { + regulator-name = "vddsoc"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ + reg_1p8v: sw2 { + regulator-name = "vdd1p8"; + regulator-min-microvolt = <1033310>; + regulator-max-microvolt = <2004000>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.635) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw4 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ + reg_2p5v: ldo2 { + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2490375>; + regulator-max-microvolt = <2490375>; + lltc,fb-voltage-divider = <487000 200000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0v: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + adv7180: camera@20 { + compatible = "adi,adv7180"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7180>; + reg = <0x20>; + powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio5>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <8>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; + bus-width = <8>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-gw52xx.dtsi b/arch/arm/dts/imx6qdl-gw52xx.dtsi new file mode 100644 index 0000000000..959d8ac2e3 --- /dev/null +++ b/arch/arm/dts/imx6qdl-gw52xx.dtsi @@ -0,0 +1,780 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + nand = &gpmi; + ssi0 = &ssi1; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_1p0v: regulator-1p0v { + compatible = "regulator-fixed"; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx6q-ventana-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + + channel@29 { + gw,mode = <1>; + reg = <0x29>; + label = "vdd_an1"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_SOC (1+R1/R2 = 1.635) */ + reg_vdd_soc: sw1 { + regulator-name = "vddsoc"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ + reg_1p8v: sw2 { + regulator-name = "vdd1p8"; + regulator-min-microvolt = <1033310>; + regulator-max-microvolt = <2004000>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.635) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw4 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ + reg_2p5v: ldo2 { + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2490375>; + regulator-max-microvolt = <2490375>; + lltc,fb-voltage-divider = <487000 200000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_AUD_1P8: Audio codec */ + reg_aud_1p8v: ldo3 { + regulator-name = "vdd1p8a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0v: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_3p3v>; + }; + + touchscreen: egalax_ts@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio7>; + interrupts = <12 2>; + wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + }; + + accel@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + no-1-8-v; /* firmware will remove if board revision supports */ + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + >; + }; + + pinctrl_ecspi3: escpi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-gw53xx.dtsi b/arch/arm/dts/imx6qdl-gw53xx.dtsi new file mode 100644 index 0000000000..8072ed47c6 --- /dev/null +++ b/arch/arm/dts/imx6qdl-gw53xx.dtsi @@ -0,0 +1,770 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + nand = &gpmi; + ssi0 = &ssi1; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_1p0v: regulator-1p0v { + compatible = "regulator-fixed"; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx6q-ventana-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + + channel@26 { + gw,mode = <1>; + reg = <0x26>; + label = "vdd_gps"; + }; + + channel@29 { + gw,mode = <1>; + reg = <0x29>; + label = "vdd_an1"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + reg = <0x3c>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_SOC (1+R1/R2 = 1.635) */ + reg_vdd_soc: sw1 { + regulator-name = "vddsoc"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ + reg_1p8v: sw2 { + regulator-name = "vdd1p8"; + regulator-min-microvolt = <1033310>; + regulator-max-microvolt = <2004000>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.635) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw4 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ + reg_2p5v: ldo2 { + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2490375>; + regulator-max-microvolt = <2490375>; + lltc,fb-voltage-divider = <487000 200000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_AUD_1P8: Audio codec */ + reg_aud_1p8v: ldo3 { + regulator-name = "vdd1p8a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0v: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_3p3v>; + }; + + touchscreen: egalax_ts@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio1>; + interrupts = <11 2>; + wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + + accel@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + no-1-8-v; /* firmware will remove if board revision supports */ + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-gw54xx.dtsi b/arch/arm/dts/imx6qdl-gw54xx.dtsi new file mode 100644 index 0000000000..8c9bcdd398 --- /dev/null +++ b/arch/arm/dts/imx6qdl-gw54xx.dtsi @@ -0,0 +1,864 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Gateworks Corporation + */ + +#include +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + nand = &gpmi; + ssi0 = &ssi1; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p0v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + sound-analog { + compatible = "fsl,imx6q-ventana-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */ + status = "okay"; + + ssi2 { + fsl,audmux-port = <1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + aud5 { + fsl,audmux-port = <4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(1)>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + + channel@26 { + gw,mode = <1>; + reg = <0x26>; + label = "vdd_gps"; + }; + }; + + fan-controller@2c { + compatible = "gw,gsc-fan"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2c>; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <&sw4_reg>; + VDDIO-supply = <®_3p3v>; + }; + + touchscreen: egalax_ts@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio7>; + interrupts = <12 2>; + wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + }; + + accel@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */ + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default", "state_dio"; + pinctrl-0 = <&pinctrl_pwm4_backlight>; + pinctrl-1 = <&pinctrl_pwm4_dio>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + no-1-8-v; /* firmware will remove if board revision supports */ + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_ecspi2: escpi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4_backlight: pwm4grpbacklight { + fsl,pins = < + /* LVDS_PWM J6.5 */ + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4_dio: pwm4grpdio { + fsl,pins = < + /* DIO3 J16.4 */ + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-gw551x.dtsi b/arch/arm/dts/imx6qdl-gw551x.dtsi new file mode 100644 index 0000000000..e5d803d023 --- /dev/null +++ b/arch/arm/dts/imx6qdl-gw551x.dtsi @@ -0,0 +1,697 @@ +/* + * Copyright 2014 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + nand = &gpmi; + ssi0 = &ssi1; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + sound-digital { + compatible = "simple-audio-card"; + simple-audio-card,name = "tda1997x-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_codec>; + simple-audio-card,frame-master = <&sound_codec>; + + sound_cpu: simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + sound_codec: simple-audio-card,codec { + sound-dai = <&hdmi_receiver>; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */ + status = "okay"; + + ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + aud5 { + fsl,audmux-port = <4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(0)>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8a"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0b"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_SOC (1+R1/R2 = 1.635) */ + reg_vdd_soc: sw1 { + regulator-name = "vddsoc"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw2 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.635) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_3P3 (1+R1/R2 = 1.281) */ + reg_3p3: sw4 { + regulator-name = "vdd3p3"; + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <3647000>; + lltc,fb-voltage-divider = <200000 56200>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8a (1+R1/R2 = 2.505): HDMI In core */ + reg_1p8a: ldo2 { + regulator-name = "vdd1p8a"; + regulator-min-microvolt = <1816125>; + regulator-max-microvolt = <1816125>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8b: HDMI In analog */ + reg_1p8b: ldo3 { + regulator-name = "vdd1p8b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + gpio_exp: pca9555@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; + + hdmi_receiver: hdmi-receiver@48 { + compatible = "nxp,tda19971"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tda1997x>; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + DOVDD-supply = <®_3p3>; + AVDD-supply = <®_1p8b>; + DVDD-supply = <®_1p8a>; + #sound-dai-cells = <0>; + nxp,audout-format = "i2s"; + nxp,audout-layout = <0>; + nxp,audout-width = <16>; + nxp,audout-mclk-fs = <128>; + /* + * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] + * and Y[11:4] across 16bits in the same cycle + * which we map to VP[15:08]<->CSI_DATA[19:12] + */ + nxp,vidout-portcfg = + /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ + < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, + /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ + < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, + /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ + < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, + /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ + < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; + + port { + tda1997x_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <16>; + hsync-active = <1>; + vsync-active = <1>; + data-active = <1>; + }; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <16>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; + bus-width = <16>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0 + MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1_csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_tda1997x: tda1997xgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-gw552x.dtsi b/arch/arm/dts/imx6qdl-gw552x.dtsi new file mode 100644 index 0000000000..290a607fed --- /dev/null +++ b/arch/arm/dts/imx6qdl-gw552x.dtsi @@ -0,0 +1,521 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2014 Gateworks Corporation + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + nand = &gpmi; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + reg_1p0v: regulator-1p0v { + compatible = "regulator-fixed"; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_SOC (1+R1/R2 = 1.635) */ + reg_vdd_soc: sw1 { + regulator-name = "vddsoc"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */ + reg_1p8v: sw2 { + regulator-name = "vdd1p8"; + regulator-min-microvolt = <1033310>; + regulator-max-microvolt = <2004000>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.635) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw4 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ + reg_2p5v: ldo2 { + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2490375>; + regulator-max-microvolt = <2490375>; + lltc,fb-voltage-divider = <487000 200000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0v: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; }; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_5p0v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-gw553x.dtsi b/arch/arm/dts/imx6qdl-gw553x.dtsi new file mode 100644 index 0000000000..c15b9cc63b --- /dev/null +++ b/arch/arm/dts/imx6qdl-gw553x.dtsi @@ -0,0 +1,737 @@ +/* + * Copyright 2016 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + nand = &gpmi; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + stdout-path = &uart2; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8a"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0b"; + }; + + channel@26 { + gw,mode = <1>; + reg = <0x26>; + label = "vdd_an1"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + magn@1c { + compatible = "st,lsm9ds1-magn"; + reg = <0x1c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + }; + + imu@6a { + compatible = "st,lsm9ds1-imu"; + reg = <0x6a>; + st,drdy-int-pin = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imu>; + interrupt-parent = <&gpio7>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + }; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_SOC (1+R1/R2 = 1.635) */ + reg_vdd_soc: sw1 { + regulator-name = "vddsoc"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw2 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.635) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_3P3 (1+R1/R2 = 1.281) */ + reg_3p3v: sw4 { + regulator-name = "vdd3p3"; + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <3647000>; + lltc,fb-voltage-divider = <200000 56200>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */ + reg_1p8a: ldo2 { + regulator-name = "vdd1p8a"; + regulator-min-microvolt = <1816125>; + regulator-max-microvolt = <1816125>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8b: microSD VDD_1P8 */ + reg_1p8b: ldo3 { + regulator-name = "vdd1p8b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0v: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + adv7180: camera@20 { + compatible = "adi,adv7180"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7180>; + reg = <0x20>; + powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio5>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + + port { + adv7180_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <8>; + }; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <8>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; + bus-width = <8>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_adv7180: adv7180grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_imu: imugrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + + pinctrl_mag: maggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-gw560x.dtsi b/arch/arm/dts/imx6qdl-gw560x.dtsi new file mode 100644 index 0000000000..093a219a77 --- /dev/null +++ b/arch/arm/dts/imx6qdl-gw560x.dtsi @@ -0,0 +1,934 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + ssi0 = &ssi1; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + stdout-path = &uart2; + }; + + backlight-display { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <100>; + }; + + backlight-keypad { + compatible = "gpio-backlight"; + gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; + default-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_12p0v: regulator-12p0v { + compatible = "regulator-fixed"; + regulator-name = "12P0V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_1p4v: regulator-vddsoc { + compatible = "regulator-fixed"; + regulator-name = "vdd_soc"; + regulator-min-microvolt = <1400000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx6q-ventana-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "sgtl5000-audio"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_an1"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + + channel@26 { + gw,mode = <1>; + reg = <0x26>; + label = "vdd_gps"; + }; + + channel@29 { + gw,mode = <1>; + reg = <0x29>; + label = "vdd_an2"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + ds1672: rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_3p3v>; + }; + + magn@1c { + compatible = "st,lsm9ds1-magn"; + reg = <0x1c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; + }; + + tca8418: keypad@34 { + compatible = "ti,tca8418"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_keypad>; + reg = <0x34>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0) + MATRIX_KEY(0x00, 0x00, BTN_1) + MATRIX_KEY(0x01, 0x01, BTN_2) + MATRIX_KEY(0x01, 0x00, BTN_3) + MATRIX_KEY(0x02, 0x00, BTN_4) + MATRIX_KEY(0x00, 0x03, BTN_5) + MATRIX_KEY(0x00, 0x02, BTN_6) + MATRIX_KEY(0x01, 0x03, BTN_7) + MATRIX_KEY(0x01, 0x02, BTN_8) + MATRIX_KEY(0x02, 0x02, BTN_9) + >; + keypad,num-rows = <4>; + keypad,num-columns = <4>; + }; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x3c>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw2 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.931) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <796551>; + regulator-max-microvolt = <1544827>; + lltc,fb-voltage-divider = <243000 261000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + linux,phandle = <®_vdd_arm>; + }; + + /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ + reg_1p8v: sw4 { + regulator-name = "vdd1p8"; + regulator-min-microvolt = <1033310>; + regulator-max-microvolt = <2004000>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */ + reg_1p0v: ldo2 { + regulator-name = "vdd1p0"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1050000>; + lltc,fb-voltage-divider = <78700 200000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_AUD_1P8: Audio codec */ + reg_aud_1p8v: ldo3 { + regulator-name = "vdd1p8a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0v: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + imu@6a { + compatible = "st,lsm9ds1-imu"; + reg = <0x6a>; + st,drdy-int-pin = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imu>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + egalax_ts: touchscreen@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio5>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + }; +}; + +&ldb { + fsl,dual-channel; + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + /* AUD4 */ + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + /* AUD6 */ + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 + >; + }; + + pinctrl_ecspi3: escpi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ + >; + }; + + pinctrl_flexcan: flexcangrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x4001b0b0 /* DIOI2C_DIS# */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0001b0b0 /* LVDS_TOUCH_IRQ# */ + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */ + >; + }; + + pinctrl_imu: imugrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0 + >; + }; + + pinctrl_keypad: keypadgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */ + >; + }; + + pinctrl_mag: maggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* USBHUB_RST# */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x170f9 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x170f9 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x170f9 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-gw5903.dtsi b/arch/arm/dts/imx6qdl-gw5903.dtsi new file mode 100644 index 0000000000..e1c8dd233c --- /dev/null +++ b/arch/arm/dts/imx6qdl-gw5903.dtsi @@ -0,0 +1,795 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +/ { + chosen { + stdout-path = &uart2; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <100>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 30 0>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_12p0: regulator-12p0v { + compatible = "regulator-fixed"; + regulator-name = "12P0V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx-audio-tlv320"; + model = "imx-tlv320"; + ssi-controller = <&ssi1>; + audio-codec = <&tlv320aic3105>; + /* routing of sink, source */ + audio-routing = + /* TLV320 LINE1L pin <-> Mic Jack connector */ + "LINE1L", "Mic Jack", + /* board Headphone Jack <-> HPOUT */ + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "Mic Jack", "Mic Bias"; + mux-int-port = <1>; + mux-ext-port = <6>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_an1"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + dts1672: rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + reg = <0x3c>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */ + reg_1p8v: sw1 { + regulator-name = "vdd1p8"; + regulator-min-microvolt = <1033310>; + regulator-max-microvolt = <2004000>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw2 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.635) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + linux,phandle = <®_vdd_arm>; + }; + + /* VDD_SOC (1+R1/R2 = 1.635) */ + reg_vdd_soc: sw4 { + regulator-name = "vddsoc"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + linux,phandle = <®_vdd_soc>; + }; + + /* VDD_1P0 (1+R1/R2 = 1.38): */ + reg_1p0v: ldo2 { + regulator-name = "vdd1p0"; + regulator-min-microvolt = <1002777>; + regulator-max-microvolt = <1002777>; + lltc,fb-voltage-divider = <100000 261000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0v: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + tlv320aic3105: codec@18 { + compatible = "ti,tlv320aic3x"; + reg = <0x18>; + reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + clocks = <&clks IMX6QDL_CLK_CKO>; + ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */ + /* Regulators */ + DRVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <®_1p8v>; + }; + + accelerometer@1d { + compatible = "fsl,mma8451"; + reg = <0x1d>; + interrupt-parent = <&gpio7>; + interrupts = <11 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT2"; + }; + + /* headphone detect */ + ts3a227e@3b { + compatible = "ti,ts3a227e"; + reg = <0x3b>; + interrupt-parent = <&gpio5>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + ti,micbias = <4>; /* 2.5V micbias */ + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: g101evn010 { + clock-frequency = <68930000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_200mhz>; + vmmc-supply = <®_3p3v>; + non-removable; + bus-width = <4>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + max-frequency = <100000000>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + non-removable; + vmmc-supply = <®_3p3v>; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* MCK */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 /* PHY_EN */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + /* I2C3 */ + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + + /* Headphone Detect */ + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0001b0b0 /* HPDET_IRQ# */ + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0001b0b0 /* HPDET_MIC# */ + + /* Codec */ + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0001b0b0 /* CODEC_RST# */ + + /* Touch Controller */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* TOUCH_IRQ# */ + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b0b0 /* TOUCH_RST */ + + /* Stow Sensor */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b0b0 /* ACCEL_IRQ2 */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b0b0 /* ACCEL_IRQ1 */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* TXEN */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x4001b0b0 /* PWR_EN */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x4001b0b0 /* EMMY_EN */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x4001b0b0 /* EMMY_CFG1# */ + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x4001b0b0 /* EMMY_CFG2# */ + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001b0b0 /* EMMY_BTWAKE# */ + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001b0b0 /* EMMY_WFWAKE# */ + + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x17059 /* CD */ + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170b9 /* CD */ + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170f9 /* CD */ + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-gw5904.dtsi b/arch/arm/dts/imx6qdl-gw5904.dtsi new file mode 100644 index 0000000000..3cd2e717c1 --- /dev/null +++ b/arch/arm/dts/imx6qdl-gw5904.dtsi @@ -0,0 +1,812 @@ +/* + * Copyright 2017 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + stdout-path = &uart2; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + }; + + reg_1p0v: regulator-1p0v { + compatible = "regulator-fixed"; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "marvell,mv88e6085"; + reg = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&fec>; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_an1"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + dts1672: rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + magn@1c { + compatible = "st,lsm9ds1-magn"; + reg = <0x1c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; + }; + + ltc3676: pmic@3c { + compatible = "lltc,ltc3676"; + reg = <0x3c>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + regulators { + /* VDD_SOC (1+R1/R2 = 1.635) */ + reg_vdd_soc: sw1 { + regulator-name = "vddsoc"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */ + reg_1p8v: sw2 { + regulator-name = "vdd1p8"; + regulator-min-microvolt = <1033310>; + regulator-max-microvolt = <2004000>; + lltc,fb-voltage-divider = <301000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_ARM (1+R1/R2 = 1.635) */ + reg_vdd_arm: sw3 { + regulator-name = "vddarm"; + regulator-min-microvolt = <674400>; + regulator-max-microvolt = <1308000>; + lltc,fb-voltage-divider = <127000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_DDR (1+R1/R2 = 2.105) */ + reg_vdd_ddr: sw4 { + regulator-name = "vddddr"; + regulator-min-microvolt = <868310>; + regulator-max-microvolt = <1684000>; + lltc,fb-voltage-divider = <221000 200000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ + reg_2p5v: ldo2 { + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2490375>; + regulator-max-microvolt = <2490375>; + lltc,fb-voltage-divider = <487000 200000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_HIGH (1+R1/R2 = 4.17) */ + reg_3p0v: ldo4 { + regulator-name = "vdd3p0"; + regulator-min-microvolt = <3023250>; + regulator-max-microvolt = <3023250>; + lltc,fb-voltage-divider = <634000 200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + imu@6a { + compatible = "st,lsm9ds1-imu"; + reg = <0x6a>; + st,drdy-int-pin = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imu>; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + egalax_ts: touchscreen@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + non-removable; + vmmc-supply = <®_3p3v>; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_imu: imugrp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 + >; + }; + + pinctrl_mag: maggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* PMIC_IRQ# */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-gw5907.dtsi b/arch/arm/dts/imx6qdl-gw5907.dtsi new file mode 100644 index 0000000000..21c68a55bc --- /dev/null +++ b/arch/arm/dts/imx6qdl-gw5907.dtsi @@ -0,0 +1,538 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + nand = &gpmi; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + stdout-path = &uart2; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_an1"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + adc@48 { + compatible = "ti,ads1015"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <0>; + ti,datarate = <5>; + }; + + channel@5 { + reg = <5>; + ti,gain = <0>; + ti,datarate = <5>; + }; + + channel@6 { + reg = <6>; + ti,gain = <0>; + ti,datarate = <5>; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-gw5910.dtsi b/arch/arm/dts/imx6qdl-gw5910.dtsi new file mode 100644 index 0000000000..ed4e222599 --- /dev/null +++ b/arch/arm/dts/imx6qdl-gw5910.dtsi @@ -0,0 +1,666 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + }; + + chosen { + stdout-path = &uart2; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_wl: regulator-wl { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wl>; + compatible = "regulator-fixed"; + regulator-name = "wl"; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <3>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vdd_vin"; + gw,voltage-divider-ohms = <22100 1000>; + gw,voltage-offset-microvolt = <800000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vdd_5p0"; + gw,voltage-divider-ohms = <22100 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_2p5"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_3p0"; + }; + + channel@8e { + gw,mode = <2>; + reg = <0x8e>; + label = "vdd_arm"; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_soc"; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_1p5"; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_1p8"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_1p0"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@9c { + gw,mode = <2>; + reg = <0x9c>; + label = "vdd_an1"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + accel@19 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + compatible = "st,lis2de12"; + reg = <0x19>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio7>; + interrupts = <13 0>; + interrupt-names = "INT1"; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +/* off-board RS232 */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* serial console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* cc1352 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +/* Sterling-LWB Bluetooth */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; +}; + +/* GPS */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_5p0v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +/* Sterling-LWB SDIO WiFi */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_wl>; + non-removable; + bus-width = <4>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_accel: accelmuxgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 + >; + }; + + pinctrl_bten: btengrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 + >; + }; + + pinctrl_ecspi3: escpi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_wl: regwlgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */ + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */ + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */ + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */ + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */ + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */ + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-gw5912.dtsi b/arch/arm/dts/imx6qdl-gw5912.dtsi new file mode 100644 index 0000000000..797f160249 --- /dev/null +++ b/arch/arm/dts/imx6qdl-gw5912.dtsi @@ -0,0 +1,608 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + nand = &gpmi; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + stdout-path = &uart2; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_vbus: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + + fan-controller@a { + compatible = "gw,gsc-fan"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0a>; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + accel@19 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + compatible = "st,lis2de12"; + reg = <0x19>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio7>; + interrupts = <13 0>; + interrupt-names = "INT1"; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */ + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + no-1-8-v; /* firmware will remove if board revision supports */ + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_accel: accelmuxgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + >; + }; + + pinctrl_ecspi2: escpi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-gw5913.dtsi b/arch/arm/dts/imx6qdl-gw5913.dtsi new file mode 100644 index 0000000000..4cd7d290f5 --- /dev/null +++ b/arch/arm/dts/imx6qdl-gw5913.dtsi @@ -0,0 +1,500 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Gateworks Corporation + */ + +#include +#include +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + nand = &gpmi; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + stdout-path = &uart2; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <3>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vdd_vin"; + gw,voltage-divider-ohms = <22100 1000>; + gw,voltage-offset-microvolt = <800000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vdd_5p0"; + gw,voltage-divider-ohms = <22100 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_2p5"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_arm"; + }; + + channel@8e { + gw,mode = <2>; + reg = <0x8e>; + label = "vdd_soc"; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_1p5"; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_1p0"; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_3p0"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_an1"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/board/gateworks/gw_ventana/MAINTAINERS b/board/gateworks/gw_ventana/MAINTAINERS index 265ddac1c0..1619d23c87 100644 --- a/board/gateworks/gw_ventana/MAINTAINERS +++ b/board/gateworks/gw_ventana/MAINTAINERS @@ -6,3 +6,51 @@ F: include/configs/gw_ventana.h F: configs/gwventana_nand_defconfig F: configs/gwventana_emmc_defconfig F: configs/gwventana_gw5904_defconfig +F: arch/arm/dts/imx6dl-gw51xx.dts +F: arch/arm/dts/imx6dl-gw52xx.dts +F: arch/arm/dts/imx6dl-gw53xx.dts +F: arch/arm/dts/imx6dl-gw54xx.dts +F: arch/arm/dts/imx6dl-gw551x.dts +F: arch/arm/dts/imx6dl-gw552x.dts +F: arch/arm/dts/imx6dl-gw553x.dts +F: arch/arm/dts/imx6dl-gw560x.dts +F: arch/arm/dts/imx6dl-gw5903.dts +F: arch/arm/dts/imx6dl-gw5904.dts +F: arch/arm/dts/imx6dl-gw5905.dts +F: arch/arm/dts/imx6dl-gw5907.dts +F: arch/arm/dts/imx6dl-gw5910.dts +F: arch/arm/dts/imx6dl-gw5912.dts +F: arch/arm/dts/imx6dl-gw5913.dts +F: arch/arm/dts/imx6qdl-gw51xx.dtsi +F: arch/arm/dts/imx6qdl-gw52xx.dtsi +F: arch/arm/dts/imx6qdl-gw53xx.dtsi +F: arch/arm/dts/imx6qdl-gw54xx.dtsi +F: arch/arm/dts/imx6qdl-gw551x.dtsi +F: arch/arm/dts/imx6qdl-gw552x.dtsi +F: arch/arm/dts/imx6qdl-gw553x.dtsi +F: arch/arm/dts/imx6qdl-gw560x.dtsi +F: arch/arm/dts/imx6qdl-gw5903.dtsi +F: arch/arm/dts/imx6qdl-gw5904.dtsi +F: arch/arm/dts/imx6qdl-gw5905.dtsi +F: arch/arm/dts/imx6qdl-gw5907.dtsi +F: arch/arm/dts/imx6qdl-gw5910.dtsi +F: arch/arm/dts/imx6qdl-gw5912.dtsi +F: arch/arm/dts/imx6qdl-gw5913.dtsi +F: arch/arm/dts/imx6q-gw51xx.dts +F: arch/arm/dts/imx6q-gw52xx.dts +F: arch/arm/dts/imx6q-gw53xx.dts +F: arch/arm/dts/imx6q-gw5400-a.dts +F: arch/arm/dts/imx6q-gw54xx.dts +F: arch/arm/dts/imx6q-gw551x.dts +F: arch/arm/dts/imx6q-gw552x.dts +F: arch/arm/dts/imx6q-gw553x.dts +F: arch/arm/dts/imx6q-gw560x.dts +F: arch/arm/dts/imx6q-gw5901.dts +F: arch/arm/dts/imx6q-gw5902.dts +F: arch/arm/dts/imx6q-gw5903.dts +F: arch/arm/dts/imx6q-gw5904.dts +F: arch/arm/dts/imx6q-gw5905.dts +F: arch/arm/dts/imx6q-gw5907.dts +F: arch/arm/dts/imx6q-gw5910.dts +F: arch/arm/dts/imx6q-gw5912.dts +F: arch/arm/dts/imx6q-gw5913.dts From 13acc63e840a0349009d0f8382e04ae39e50c3d5 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 1 Mar 2021 14:33:31 -0800 Subject: [PATCH 073/117] arm: dts: imx6qdl-gw*: add dr_mode prop to dt to avoid error The fsl-usb dt bindings in Linux default dr_mode to 'host' for backward compatibility however U-Boot prints an error if this property does not exist. Declare it in the Gateworks Ventana device-trees to avoid the error. Signed-off-by: Tim Harvey --- arch/arm/dts/imx6qdl-gw51xx.dtsi | 1 + arch/arm/dts/imx6qdl-gw52xx.dtsi | 1 + arch/arm/dts/imx6qdl-gw53xx.dtsi | 1 + arch/arm/dts/imx6qdl-gw54xx.dtsi | 1 + arch/arm/dts/imx6qdl-gw551x.dtsi | 1 + arch/arm/dts/imx6qdl-gw552x.dtsi | 1 + arch/arm/dts/imx6qdl-gw553x.dtsi | 1 + arch/arm/dts/imx6qdl-gw560x.dtsi | 1 + arch/arm/dts/imx6qdl-gw5903.dtsi | 1 + arch/arm/dts/imx6qdl-gw5904.dtsi | 1 + arch/arm/dts/imx6qdl-gw5907.dtsi | 1 + arch/arm/dts/imx6qdl-gw5910.dtsi | 1 + arch/arm/dts/imx6qdl-gw5913.dtsi | 1 + 13 files changed, 13 insertions(+) diff --git a/arch/arm/dts/imx6qdl-gw51xx.dtsi b/arch/arm/dts/imx6qdl-gw51xx.dtsi index 3c04b5a4f3..2a21c6731e 100644 --- a/arch/arm/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw51xx.dtsi @@ -450,6 +450,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; + dr_mode = "otg"; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw52xx.dtsi b/arch/arm/dts/imx6qdl-gw52xx.dtsi index 959d8ac2e3..de54b7c217 100644 --- a/arch/arm/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw52xx.dtsi @@ -544,6 +544,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; + dr_mode = "otg"; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw53xx.dtsi b/arch/arm/dts/imx6qdl-gw53xx.dtsi index 8072ed47c6..64bb88dc74 100644 --- a/arch/arm/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw53xx.dtsi @@ -541,6 +541,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; + dr_mode = "otg"; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw54xx.dtsi b/arch/arm/dts/imx6qdl-gw54xx.dtsi index 8c9bcdd398..56d090ec0f 100644 --- a/arch/arm/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw54xx.dtsi @@ -611,6 +611,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; + dr_mode = "otg"; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw551x.dtsi b/arch/arm/dts/imx6qdl-gw551x.dtsi index e5d803d023..1bb586cbd5 100644 --- a/arch/arm/dts/imx6qdl-gw551x.dtsi +++ b/arch/arm/dts/imx6qdl-gw551x.dtsi @@ -536,6 +536,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; + dr_mode = "otg"; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw552x.dtsi b/arch/arm/dts/imx6qdl-gw552x.dtsi index 290a607fed..5462907f12 100644 --- a/arch/arm/dts/imx6qdl-gw552x.dtsi +++ b/arch/arm/dts/imx6qdl-gw552x.dtsi @@ -402,6 +402,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; + dr_mode = "otg"; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw553x.dtsi b/arch/arm/dts/imx6qdl-gw553x.dtsi index c15b9cc63b..b6965f25da 100644 --- a/arch/arm/dts/imx6qdl-gw553x.dtsi +++ b/arch/arm/dts/imx6qdl-gw553x.dtsi @@ -509,6 +509,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; + dr_mode = "otg"; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw560x.dtsi b/arch/arm/dts/imx6qdl-gw560x.dtsi index 093a219a77..d5468fb260 100644 --- a/arch/arm/dts/imx6qdl-gw560x.dtsi +++ b/arch/arm/dts/imx6qdl-gw560x.dtsi @@ -656,6 +656,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; + dr_mode = "otg"; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5903.dtsi b/arch/arm/dts/imx6qdl-gw5903.dtsi index e1c8dd233c..78f9ec90b7 100644 --- a/arch/arm/dts/imx6qdl-gw5903.dtsi +++ b/arch/arm/dts/imx6qdl-gw5903.dtsi @@ -531,6 +531,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; + dr_mode = "host"; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5904.dtsi b/arch/arm/dts/imx6qdl-gw5904.dtsi index 3cd2e717c1..52b255b726 100644 --- a/arch/arm/dts/imx6qdl-gw5904.dtsi +++ b/arch/arm/dts/imx6qdl-gw5904.dtsi @@ -583,6 +583,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; + dr_mode = "otg"; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5907.dtsi b/arch/arm/dts/imx6qdl-gw5907.dtsi index 21c68a55bc..c8b29246b7 100644 --- a/arch/arm/dts/imx6qdl-gw5907.dtsi +++ b/arch/arm/dts/imx6qdl-gw5907.dtsi @@ -378,6 +378,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; + dr_mode = "otg"; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5910.dtsi b/arch/arm/dts/imx6qdl-gw5910.dtsi index ed4e222599..56d0c4ff6c 100644 --- a/arch/arm/dts/imx6qdl-gw5910.dtsi +++ b/arch/arm/dts/imx6qdl-gw5910.dtsi @@ -398,6 +398,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; + dr_mode = "host"; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5913.dtsi b/arch/arm/dts/imx6qdl-gw5913.dtsi index 4cd7d290f5..9fae4cccd7 100644 --- a/arch/arm/dts/imx6qdl-gw5913.dtsi +++ b/arch/arm/dts/imx6qdl-gw5913.dtsi @@ -343,6 +343,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; + dr_mode = "host"; status = "okay"; }; From d863d054397a5aa5e9698c180b4a898b415267c7 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 1 Mar 2021 14:33:32 -0800 Subject: [PATCH 074/117] imx: ventana: convert U-Boot to OF_CONTROL using FIT image In preparation for dm conversion convert to OF_CONTROL by adding FIT image support and multi dtb. Add a board_fit_config_name_match to match the dtb based off of EEPROM model. Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/gsc.c | 88 +++++++++++++++++++++ board/gateworks/gw_ventana/gsc.h | 1 + board/gateworks/gw_ventana/gw_ventana.c | 20 ++++- board/gateworks/gw_ventana/gw_ventana_spl.c | 10 ++- configs/gwventana_emmc_defconfig | 10 ++- configs/gwventana_gw5904_defconfig | 10 ++- configs/gwventana_nand_defconfig | 10 ++- 7 files changed, 144 insertions(+), 5 deletions(-) diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c index bcb6bca346..ffed6b5fc8 100644 --- a/board/gateworks/gw_ventana/gsc.c +++ b/board/gateworks/gw_ventana/gsc.c @@ -14,6 +14,8 @@ #include #include +#include + #include "ventana_eeprom.h" #include "gsc.h" @@ -179,6 +181,92 @@ int gsc_boot_wd_disable(void) return 1; } +/* determine BOM revision from model */ +int get_bom_rev(const char *str) +{ + int rev_bom = 0; + int i; + + for (i = strlen(str) - 1; i > 0; i--) { + if (str[i] == '-') + break; + if (str[i] >= '1' && str[i] <= '9') { + rev_bom = str[i] - '0'; + break; + } + } + return rev_bom; +} + +/* determine PCB revision from model */ +char get_pcb_rev(const char *str) +{ + char rev_pcb = 'A'; + int i; + + for (i = strlen(str) - 1; i > 0; i--) { + if (str[i] == '-') + break; + if (str[i] >= 'A') { + rev_pcb = str[i]; + break; + } + } + return rev_pcb; +} + +/* + * get dt name based on model and detail level: + */ +const char *gsc_get_dtb_name(int level, char *buf, int sz) +{ + const char *model = (const char *)ventana_info.model; + const char *pre = is_mx6dq() ? "imx6q-" : "imx6dl-"; + int modelno, rev_pcb, rev_bom; + + /* a few board models are dt equivalents to other models */ + if (strncasecmp(model, "gw5906", 6) == 0) + model = "gw552x-d"; + else if (strncasecmp(model, "gw5908", 6) == 0) + model = "gw53xx-f"; + else if (strncasecmp(model, "gw5905", 6) == 0) + model = "gw5904-a"; + + modelno = ((model[2] - '0') * 1000) + + ((model[3] - '0') * 100) + + ((model[4] - '0') * 10) + + (model[5] - '0'); + rev_pcb = tolower(get_pcb_rev(model)); + rev_bom = get_bom_rev(model); + + /* compare model/rev/bom in order of most specific to least */ + snprintf(buf, sz, "%s%04d", pre, modelno); + switch (level) { + case 0: /* full model first (ie gw5400-a1) */ + if (rev_bom) { + snprintf(buf, sz, "%sgw%04d-%c%d", pre, modelno, rev_pcb, rev_bom); + break; + } + fallthrough; + case 1: /* don't care about bom rev (ie gw5400-a) */ + snprintf(buf, sz, "%sgw%04d-%c", pre, modelno, rev_pcb); + break; + case 2: /* don't care about the pcb rev (ie gw5400) */ + snprintf(buf, sz, "%sgw%04d", pre, modelno); + break; + case 3: /* look for generic model (ie gw540x) */ + snprintf(buf, sz, "%sgw%03dx", pre, modelno / 10); + break; + case 4: /* look for more generic model (ie gw54xx) */ + snprintf(buf, sz, "%sgw%02dxx", pre, modelno / 100); + break; + default: /* give up */ + return NULL; + } + + return buf; +} + #if defined(CONFIG_CMD_GSC) && !defined(CONFIG_SPL_BUILD) static int do_gsc_sleep(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/board/gateworks/gw_ventana/gsc.h b/board/gateworks/gw_ventana/gsc.h index 6dcaafadf3..29d375b3a7 100644 --- a/board/gateworks/gw_ventana/gsc.h +++ b/board/gateworks/gw_ventana/gsc.h @@ -67,5 +67,6 @@ int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len); int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len); int gsc_info(int verbose); int gsc_boot_wd_disable(void); +const char *gsc_get_dtb_name(int level, char *buf, int sz); #endif diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 71de80c1b9..fb745cccee 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -56,7 +56,6 @@ DECLARE_GLOBAL_DATA_PTR; * read it once. */ struct ventana_board_info ventana_info; - static int board_type; /* ENET */ @@ -677,6 +676,25 @@ int board_init(void) return 0; } +int board_fit_config_name_match(const char *name) +{ + static char init; + const char *dtb; + char buf[32]; + int i = 0; + + do { + dtb = gsc_get_dtb_name(i++, buf, sizeof(buf)); + if (dtb && !strcmp(dtb, name)) { + if (!init++) + printf("DTB: %s\n", name); + return 0; + } + } while (dtb); + + return -1; +} + #if defined(CONFIG_DISPLAY_BOARDINFO_LATE) /* * called during late init (after relocation and after board_init()) diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index e0e4bac161..a4f64395a1 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -731,8 +731,16 @@ void board_boot_order(u32 *spl_boot_list) /* its our chance to print info about boot device */ void spl_board_init(void) { + u32 boot_device; + int board_type; + /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */ - u32 boot_device = spl_boot_device(); + boot_device = spl_boot_device(); + + /* read eeprom again now that we have gd */ + board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); + if (board_type == GW_UNKNOWN) + hang(); switch (boot_device) { case BOOT_DEVICE_MMC1: diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 41e190bf1e..453c80dd4c 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -18,8 +18,12 @@ CONFIG_SPL_STACK_R_ADDR=0x18000000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xD1400 CONFIG_CMD_HDMIDETECT=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +# CONFIG_LEGACY_IMAGE_FORMAT is not set CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" @@ -31,6 +35,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_DMA=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y @@ -62,6 +67,9 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:16m(uboot),1m(env),-(rootfs)" CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_OF_LIST="imx6q-gw51xx imx6dl-gw51xx imx6q-gw52xx imx6dl-gw52xx imx6q-gw53xx imx6dl-gw53xx imx6q-gw54xx imx6dl-gw54xx imx6q-gw551x imx6dl-gw551x imx6q-gw552x imx6dl-gw552x imx6q-gw553x imx6dl-gw553x imx6q-gw560x imx6dl-gw560x imx6q-gw5903 imx6dl-gw5903 imx6q-gw5904 imx6dl-gw5904 imx6q-gw5907 imx6dl-gw5907 imx6q-gw5910 imx6dl-gw5910 imx6q-gw5912 imx6dl-gw5912 imx6q-gw5913 imx6dl-gw5913" +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y @@ -79,6 +87,7 @@ CONFIG_PHYLIB=y CONFIG_E1000=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y @@ -107,5 +116,4 @@ CONFIG_DM_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_VIDEO_IPUV3=y -CONFIG_OF_LIBFDT=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 66b0441978..4dc636637f 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -18,8 +18,12 @@ CONFIG_SPL_STACK_R_ADDR=0x18000000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xD1400 CONFIG_CMD_HDMIDETECT=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +# CONFIG_LEGACY_IMAGE_FORMAT is not set CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" @@ -31,6 +35,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_DMA=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y @@ -62,6 +67,9 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:16m(uboot),1m(env),-(rootfs)" CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_OF_LIST="imx6q-gw51xx imx6dl-gw51xx imx6q-gw52xx imx6dl-gw52xx imx6q-gw53xx imx6dl-gw53xx imx6q-gw54xx imx6dl-gw54xx imx6q-gw551x imx6dl-gw551x imx6q-gw552x imx6dl-gw552x imx6q-gw553x imx6dl-gw553x imx6q-gw560x imx6dl-gw560x imx6q-gw5903 imx6dl-gw5903 imx6q-gw5904 imx6dl-gw5904 imx6q-gw5907 imx6dl-gw5907 imx6q-gw5910 imx6dl-gw5910 imx6q-gw5912 imx6dl-gw5912 imx6q-gw5913 imx6dl-gw5913" +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y @@ -83,6 +91,7 @@ CONFIG_MV88E61XX_FIXED_PORTS=0x0 CONFIG_E1000=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y @@ -111,5 +120,4 @@ CONFIG_DM_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_VIDEO_IPUV3=y -CONFIG_OF_LIBFDT=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 9022f350d1..bd84340308 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -18,8 +18,12 @@ CONFIG_SPL_STACK_R_ADDR=0x18000000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x1080000 CONFIG_CMD_HDMIDETECT=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +# CONFIG_LEGACY_IMAGE_FORMAT is not set CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" @@ -31,6 +35,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_DMA=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y @@ -65,6 +70,9 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:16m(uboot),1m(env),-(rootfs)" CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_OF_LIST="imx6q-gw51xx imx6dl-gw51xx imx6q-gw52xx imx6dl-gw52xx imx6q-gw53xx imx6dl-gw53xx imx6q-gw54xx imx6dl-gw54xx imx6q-gw551x imx6dl-gw551x imx6q-gw552x imx6dl-gw552x imx6q-gw553x imx6dl-gw553x imx6q-gw560x imx6dl-gw560x imx6q-gw5903 imx6dl-gw5903 imx6q-gw5904 imx6dl-gw5904 imx6q-gw5907 imx6dl-gw5907 imx6q-gw5910 imx6dl-gw5910 imx6q-gw5912 imx6dl-gw5912 imx6q-gw5913 imx6dl-gw5913" +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y @@ -83,6 +91,7 @@ CONFIG_PHYLIB=y CONFIG_E1000=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y @@ -111,5 +120,4 @@ CONFIG_DM_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_VIDEO_IPUV3=y -CONFIG_OF_LIBFDT=y CONFIG_FDT_FIXUP_PARTITIONS=y From ee025c13b29e58007f8cfc822b100ce6f085e8cd Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 1 Mar 2021 14:33:33 -0800 Subject: [PATCH 075/117] imx: ventana: add pinctrl and remove unneeded UART init and config Once the IMX6 pinctrl driver is added UART is fully using driver mode so we no longer need to config and initialize it. Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/gw_ventana.c | 12 ------------ configs/gwventana_emmc_defconfig | 2 ++ configs/gwventana_gw5904_defconfig | 2 ++ configs/gwventana_nand_defconfig | 2 ++ 4 files changed, 6 insertions(+), 12 deletions(-) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index fb745cccee..0fbbfb8346 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -628,8 +627,6 @@ void get_board_serial(struct tag_serialnr *serialnr) int board_early_init_f(void) { - setup_iomux_uart(); - #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif @@ -1389,12 +1386,3 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } #endif /* CONFIG_OF_BOARD_SETUP */ - -static struct mxc_serial_plat ventana_mxc_serial_plat = { - .reg = (struct mxc_uart *)UART2_BASE, -}; - -U_BOOT_DRVINFO(ventana_serial) = { - .name = "serial_mxc", - .plat = &ventana_mxc_serial_plat, -}; diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 453c80dd4c..433de5ece3 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -87,6 +87,8 @@ CONFIG_PHYLIB=y CONFIG_E1000=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 4dc636637f..4fd734e260 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -91,6 +91,8 @@ CONFIG_MV88E61XX_FIXED_PORTS=0x0 CONFIG_E1000=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index bd84340308..5d8126e977 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -91,6 +91,8 @@ CONFIG_PHYLIB=y CONFIG_E1000=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y From 72c46327f03f61b8801f7e28463329b9f7231947 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 1 Mar 2021 14:33:34 -0800 Subject: [PATCH 076/117] imx: ventana: enable dm support for USB Enable dm support for USB (which also requires dm support for fixed regulators used for vbus enable) and remove usb iomux which is no longer needed. We can remove the handling of otgpwr_en gpio as this is defined in dt as usbotg vbus-supply but we need to keep the handling of USB_HUB_RST# for boards that have a USB HUB as that isn't defined in the dt's currently. Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/common.c | 17 ----------------- board/gateworks/gw_ventana/common.h | 1 - board/gateworks/gw_ventana/gw_ventana.c | 22 ++++------------------ configs/gwventana_emmc_defconfig | 3 +++ configs/gwventana_gw5904_defconfig | 3 +++ configs/gwventana_nand_defconfig | 3 +++ include/configs/gw_ventana.h | 1 - 7 files changed, 13 insertions(+), 37 deletions(-) diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c index 14f45bf07d..4627a156fe 100644 --- a/board/gateworks/gw_ventana/common.c +++ b/board/gateworks/gw_ventana/common.c @@ -970,7 +970,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .rs485en = IMX_GPIO_NR(3, 24), .dioi2c_en = IMX_GPIO_NR(4, 5), .pcie_sson = IMX_GPIO_NR(1, 20), - .otgpwr_en = IMX_GPIO_NR(3, 22), .mmc_cd = IMX_GPIO_NR(7, 0), }, @@ -990,7 +989,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .gps_shdn = IMX_GPIO_NR(1, 2), .vidin_en = IMX_GPIO_NR(5, 20), .wdis = IMX_GPIO_NR(7, 12), - .otgpwr_en = IMX_GPIO_NR(3, 22), .nand = true, }, @@ -1014,7 +1012,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .wdis = IMX_GPIO_NR(7, 12), .msata_en = GP_MSATA_SEL, .rs232_en = GP_RS232_EN, - .otgpwr_en = IMX_GPIO_NR(3, 22), .vsel_pin = IMX_GPIO_NR(6, 14), .mmc_cd = IMX_GPIO_NR(7, 0), .nand = true, @@ -1039,7 +1036,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .wdis = IMX_GPIO_NR(7, 12), .msata_en = GP_MSATA_SEL, .rs232_en = GP_RS232_EN, - .otgpwr_en = IMX_GPIO_NR(3, 22), .vsel_pin = IMX_GPIO_NR(6, 14), .mmc_cd = IMX_GPIO_NR(7, 0), .nand = true, @@ -1066,7 +1062,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .wdis = IMX_GPIO_NR(5, 17), .msata_en = GP_MSATA_SEL, .rs232_en = GP_RS232_EN, - .otgpwr_en = IMX_GPIO_NR(3, 22), .vsel_pin = IMX_GPIO_NR(6, 14), .mmc_cd = IMX_GPIO_NR(7, 0), .nand = true, @@ -1117,7 +1112,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .pcie_rst = IMX_GPIO_NR(1, 0), .vidin_en = IMX_GPIO_NR(5, 20), .wdis = IMX_GPIO_NR(7, 12), - .otgpwr_en = IMX_GPIO_NR(3, 22), .vsel_pin = IMX_GPIO_NR(6, 14), .mmc_cd = IMX_GPIO_NR(7, 0), .nand = true, @@ -1140,7 +1134,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .rs232_en = GP_RS232_EN, .vidin_en = IMX_GPIO_NR(3, 31), .wdis = IMX_GPIO_NR(7, 12), - .otgpwr_en = IMX_GPIO_NR(4, 15), .mmc_cd = IMX_GPIO_NR(7, 0), }, @@ -1166,7 +1159,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { }, .pcie_rst = IMX_GPIO_NR(1, 0), .rs232_en = GP_RS232_EN, - .otgpwr_en = IMX_GPIO_NR(3, 23), .nand = true, }, @@ -1179,7 +1171,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .leds = { IMX_GPIO_NR(6, 14), }, - .otgpwr_en = IMX_GPIO_NR(4, 15), .mmc_cd = IMX_GPIO_NR(6, 11), }, @@ -1197,7 +1188,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .pcie_rst = IMX_GPIO_NR(1, 0), .mezz_pwren = IMX_GPIO_NR(2, 19), .mezz_irq = IMX_GPIO_NR(2, 18), - .otgpwr_en = IMX_GPIO_NR(3, 22), }, /* GW5905 */ @@ -1279,7 +1269,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .pcie_rst = IMX_GPIO_NR(1, 0), .mezz_pwren = IMX_GPIO_NR(2, 19), .mezz_irq = IMX_GPIO_NR(2, 18), - .otgpwr_en = IMX_GPIO_NR(3, 22), }, }; @@ -1382,12 +1371,6 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info) gpio_direction_output(gpio_cfg[board].wdis, 1); } - /* OTG power off */ - if (gpio_cfg[board].otgpwr_en) { - gpio_request(gpio_cfg[board].otgpwr_en, "usbotg_pwr"); - gpio_direction_output(gpio_cfg[board].otgpwr_en, 0); - } - /* sense vselect pin to see if we support uhs-i */ if (gpio_cfg[board].vsel_pin) { gpio_request(gpio_cfg[board].vsel_pin, "sd3_vselect"); diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h index 5cec01c838..d73850c5b9 100644 --- a/board/gateworks/gw_ventana/common.h +++ b/board/gateworks/gw_ventana/common.h @@ -75,7 +75,6 @@ struct ventana { int wdis; int msata_en; int rs232_en; - int otgpwr_en; int vsel_pin; int mmc_cd; /* various features */ diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 0fbbfb8346..50bb202a72 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -142,18 +142,14 @@ static void setup_iomux_enet(int gpio) } #ifdef CONFIG_USB_EHCI_MX6 -static iomux_v3_cfg_t const usb_pads[] = { - IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG), - IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG), - /* OTG PWR */ - IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG), -}; - +/* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */ int board_ehci_hcd_init(int port) { int gpio; - SETUP_IOMUX_PADS(usb_pads); + /* USB HUB is always on P1 */ + if (port == 0) + return 0; /* Reset USB HUB */ switch (board_type) { @@ -178,16 +174,6 @@ int board_ehci_hcd_init(int port) return 0; } - -int board_ehci_power(int port, int on) -{ - /* enable OTG VBUS */ - if (!port && board_type < GW_UNKNOWN) { - if (gpio_cfg[board_type].otgpwr_en) - gpio_set_value(gpio_cfg[board_type].otgpwr_en, on); - } - return 0; -} #endif /* CONFIG_USB_EHCI_MX6 */ #ifdef CONFIG_MXC_SPI diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 433de5ece3..696f49ca8a 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -89,12 +89,15 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 4fd734e260..0e697017b1 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -93,12 +93,15 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 5d8126e977..9b204c7263 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -93,12 +93,15 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 7c8abda1d2..1d68abda59 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -100,7 +100,6 @@ #define CONFIG_ARP_TIMEOUT 200UL /* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 From 19a387f85d3643ec052903223bfdcffe0ab227a6 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 1 Mar 2021 14:33:35 -0800 Subject: [PATCH 077/117] imx: ventana: enable dm support for MMC and SATA Enable driver model support for MMC and SATA. Note that DM_MMC requires aliases for your mmc devices so they are added to the dts. Linux does not support enumerating mmc devices by alias so these are not present in the Linux dts. Note that we still need board_mmc_init() and board_mmc_getcd() for not DM SPL to support MMC. Signed-off-by: Tim Harvey --- arch/arm/dts/imx6qdl-gw52xx.dtsi | 1 + arch/arm/dts/imx6qdl-gw53xx.dtsi | 1 + arch/arm/dts/imx6qdl-gw54xx.dtsi | 1 + arch/arm/dts/imx6qdl-gw560x.dtsi | 2 ++ arch/arm/dts/imx6qdl-gw5904.dtsi | 1 + arch/arm/dts/imx6qdl-gw5910.dtsi | 1 + arch/arm/dts/imx6qdl-gw5912.dtsi | 1 + board/gateworks/gw_ventana/gw_ventana.c | 5 ----- configs/gwventana_emmc_defconfig | 2 ++ configs/gwventana_gw5904_defconfig | 2 ++ configs/gwventana_nand_defconfig | 2 ++ 11 files changed, 14 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/imx6qdl-gw52xx.dtsi b/arch/arm/dts/imx6qdl-gw52xx.dtsi index de54b7c217..6eedf8d40d 100644 --- a/arch/arm/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw52xx.dtsi @@ -13,6 +13,7 @@ led0 = &led0; led1 = &led1; led2 = &led2; + mmc0 = &usdhc3; nand = &gpmi; ssi0 = &ssi1; usb0 = &usbh1; diff --git a/arch/arm/dts/imx6qdl-gw53xx.dtsi b/arch/arm/dts/imx6qdl-gw53xx.dtsi index 64bb88dc74..9deec7e352 100644 --- a/arch/arm/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw53xx.dtsi @@ -13,6 +13,7 @@ led0 = &led0; led1 = &led1; led2 = &led2; + mmc0 = &usdhc3; nand = &gpmi; ssi0 = &ssi1; usb0 = &usbh1; diff --git a/arch/arm/dts/imx6qdl-gw54xx.dtsi b/arch/arm/dts/imx6qdl-gw54xx.dtsi index 56d090ec0f..a30ba4848e 100644 --- a/arch/arm/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw54xx.dtsi @@ -14,6 +14,7 @@ led0 = &led0; led1 = &led1; led2 = &led2; + mmc0 = &usdhc3; nand = &gpmi; ssi0 = &ssi1; usb0 = &usbh1; diff --git a/arch/arm/dts/imx6qdl-gw560x.dtsi b/arch/arm/dts/imx6qdl-gw560x.dtsi index d5468fb260..0786b0d546 100644 --- a/arch/arm/dts/imx6qdl-gw560x.dtsi +++ b/arch/arm/dts/imx6qdl-gw560x.dtsi @@ -55,6 +55,8 @@ led0 = &led0; led1 = &led1; led2 = &led2; + mmc0 = &usdhc2; + mmc1 = &usdhc3; ssi0 = &ssi1; usb0 = &usbh1; usb1 = &usbotg; diff --git a/arch/arm/dts/imx6qdl-gw5904.dtsi b/arch/arm/dts/imx6qdl-gw5904.dtsi index 52b255b726..5b7bd56932 100644 --- a/arch/arm/dts/imx6qdl-gw5904.dtsi +++ b/arch/arm/dts/imx6qdl-gw5904.dtsi @@ -55,6 +55,7 @@ led0 = &led0; led1 = &led1; led2 = &led2; + mmc0 = &usdhc3; usb0 = &usbh1; usb1 = &usbotg; }; diff --git a/arch/arm/dts/imx6qdl-gw5910.dtsi b/arch/arm/dts/imx6qdl-gw5910.dtsi index 56d0c4ff6c..248e077a56 100644 --- a/arch/arm/dts/imx6qdl-gw5910.dtsi +++ b/arch/arm/dts/imx6qdl-gw5910.dtsi @@ -13,6 +13,7 @@ led0 = &led0; led1 = &led1; led2 = &led2; + mmc0 = &usdhc3; }; chosen { diff --git a/arch/arm/dts/imx6qdl-gw5912.dtsi b/arch/arm/dts/imx6qdl-gw5912.dtsi index 797f160249..7593872c07 100644 --- a/arch/arm/dts/imx6qdl-gw5912.dtsi +++ b/arch/arm/dts/imx6qdl-gw5912.dtsi @@ -13,6 +13,7 @@ led0 = &led0; led1 = &led1; led2 = &led2; + mmc0 = &usdhc3; nand = &gpmi; usb0 = &usbh1; usb1 = &usbotg; diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 50bb202a72..7be4555d4b 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -650,10 +649,6 @@ int board_init(void) setup_ventana_i2c(1); setup_ventana_i2c(2); -#ifdef CONFIG_SATA - setup_sata(); -#endif - setup_iomux_gpio(board_type, &ventana_info); return 0; diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 696f49ca8a..d383a85f8b 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xD1400 CONFIG_CMD_HDMIDETECT=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx" +CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y @@ -79,6 +80,7 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 0e697017b1..b6ef9e6f8a 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xD1400 CONFIG_CMD_HDMIDETECT=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx" +CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y @@ -79,6 +80,7 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 9b204c7263..533d31af9f 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x1080000 CONFIG_CMD_HDMIDETECT=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx" +CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y @@ -81,6 +82,7 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y From 777f333c375ae461f543a3612f420c17cc353b19 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 1 Mar 2021 14:33:36 -0800 Subject: [PATCH 078/117] imx: ventana: enable dm for MTD and NAND Enable driver model for MTD and NAND support allowing us to remove the iomux, init, and most of the static configuration. Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/gw_ventana.c | 52 ------------------------- configs/gwventana_nand_defconfig | 2 + include/configs/gw_ventana.h | 14 +------ 3 files changed, 4 insertions(+), 64 deletions(-) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 7be4555d4b..43a8ab6a16 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -80,54 +80,6 @@ static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG), }; -#ifdef CONFIG_CMD_NAND -static iomux_v3_cfg_t const nfc_pads[] = { - IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static void setup_gpmi_nand(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - /* config gpmi nand iomux */ - SETUP_IOMUX_PADS(nfc_pads); - - /* config gpmi and bch clock to 100 MHz */ - clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, - MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | - MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); - - /* enable gpmi and bch clock gating */ - setbits_le32(&mxc_ccm->CCGR4, - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); - - /* enable apbh clock gating */ - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); -} -#endif - static void setup_iomux_enet(int gpio) { SETUP_IOMUX_PADS(enet_pads); @@ -639,10 +591,6 @@ int board_init(void) setup_ventana_i2c(0); board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); -#ifdef CONFIG_CMD_NAND - if (gpio_cfg[board_type].nand) - setup_gpmi_nand(); -#endif #ifdef CONFIG_MXC_SPI setup_spi(); #endif diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 533d31af9f..ea5ed052b5 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -87,8 +87,10 @@ CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y +CONFIG_DM_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y CONFIG_PHYLIB=y CONFIG_E1000=y CONFIG_MII=y diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 1d68abda59..5754b6aef0 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -35,18 +35,8 @@ /* Serial */ #define CONFIG_MXC_UART_BASE UART2_BASE -#if !defined(CONFIG_SPI_FLASH) && defined(CONFIG_SPL_NAND_SUPPORT) -/* Enable NAND support */ -#ifdef CONFIG_CMD_NAND - #define CONFIG_SYS_MAX_NAND_DEVICE 1 - #define CONFIG_SYS_NAND_BASE 0x40000000 - #define CONFIG_SYS_NAND_5_ADDR_CYCLE - #define CONFIG_SYS_NAND_ONFI_DETECTION - - /* DMA stuff, needed for GPMI/MXS NAND support */ -#endif - -#endif /* CONFIG_SPI_FLASH */ +/* NAND */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* I2C Configs */ #define CONFIG_SYS_I2C From ca3ac1e32a3e881a89a7335107d5056e233f2963 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 1 Mar 2021 14:33:37 -0800 Subject: [PATCH 079/117] imx: ventana: enable dm for SPI Enable driver model for SPI which allows us to remove the iomux and init. Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/gw_ventana.c | 27 ------------------------- configs/gwventana_emmc_defconfig | 3 +++ configs/gwventana_gw5904_defconfig | 3 +++ configs/gwventana_nand_defconfig | 3 +++ 4 files changed, 9 insertions(+), 27 deletions(-) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 43a8ab6a16..5237f2dac4 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -41,7 +40,6 @@ #include #include #include -#include #include "gsc.h" #include "common.h" @@ -127,28 +125,6 @@ int board_ehci_hcd_init(int port) } #endif /* CONFIG_USB_EHCI_MX6 */ -#ifdef CONFIG_MXC_SPI -iomux_v3_cfg_t const ecspi1_pads[] = { - /* SS1 */ - IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), -}; - -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1; -} - -static void setup_spi(void) -{ - gpio_request(IMX_GPIO_NR(3, 19), "spi_cs"); - gpio_direction_output(IMX_GPIO_NR(3, 19), 1); - SETUP_IOMUX_PADS(ecspi1_pads); -} -#endif - /* configure eth0 PHY board-specific LED behavior */ int board_phy_config(struct phy_device *phydev) { @@ -591,9 +567,6 @@ int board_init(void) setup_ventana_i2c(0); board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); -#ifdef CONFIG_MXC_SPI - setup_spi(); -#endif setup_ventana_i2c(1); setup_ventana_i2c(2); diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index d383a85f8b..d5270c5232 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -96,6 +96,9 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index b6ef9e6f8a..091bf30c3b 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -100,6 +100,9 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index ea5ed052b5..0ccd3e9dfd 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -102,6 +102,9 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_USB=y From aeee33d6e0b637fd9d16aff570aa95c625afe9eb Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 4 Mar 2021 14:09:34 -0300 Subject: [PATCH 080/117] MAINTAINERS: Use my personal e-mail address Use my personal e-mail address for U-Boot related work. Signed-off-by: Fabio Estevam --- board/freescale/mx28evk/MAINTAINERS | 2 +- board/freescale/mx6sabreauto/MAINTAINERS | 2 +- board/freescale/mx6sabresd/MAINTAINERS | 2 +- board/freescale/mx6slevk/MAINTAINERS | 2 +- board/freescale/mx6sxsabreauto/MAINTAINERS | 2 +- board/freescale/mx6sxsabresd/MAINTAINERS | 2 +- board/solidrun/mx6cuboxi/MAINTAINERS | 2 +- board/technexion/pico-imx6ul/MAINTAINERS | 2 +- board/udoo/MAINTAINERS | 2 +- board/wandboard/MAINTAINERS | 2 +- board/warp7/MAINTAINERS | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/board/freescale/mx28evk/MAINTAINERS b/board/freescale/mx28evk/MAINTAINERS index a98a70558a..597118d3f6 100644 --- a/board/freescale/mx28evk/MAINTAINERS +++ b/board/freescale/mx28evk/MAINTAINERS @@ -1,5 +1,5 @@ MX28EVK BOARD -M: Fabio Estevam +M: Fabio Estevam S: Maintained F: board/freescale/mx28evk/ F: include/configs/mx28evk.h diff --git a/board/freescale/mx6sabreauto/MAINTAINERS b/board/freescale/mx6sabreauto/MAINTAINERS index a89f05a829..6179d672c3 100644 --- a/board/freescale/mx6sabreauto/MAINTAINERS +++ b/board/freescale/mx6sabreauto/MAINTAINERS @@ -1,5 +1,5 @@ MX6SABREAUTO BOARD -M: Fabio Estevam +M: Fabio Estevam M: Peng Fan S: Maintained F: board/freescale/mx6sabreauto/ diff --git a/board/freescale/mx6sabresd/MAINTAINERS b/board/freescale/mx6sabresd/MAINTAINERS index 95752619e7..5e256ef163 100644 --- a/board/freescale/mx6sabresd/MAINTAINERS +++ b/board/freescale/mx6sabresd/MAINTAINERS @@ -1,5 +1,5 @@ MX6SABRESD BOARD -M: Fabio Estevam +M: Fabio Estevam S: Maintained F: board/freescale/mx6sabresd/ F: include/configs/mx6sabresd.h diff --git a/board/freescale/mx6slevk/MAINTAINERS b/board/freescale/mx6slevk/MAINTAINERS index be2f3d5b37..ae87fe472b 100644 --- a/board/freescale/mx6slevk/MAINTAINERS +++ b/board/freescale/mx6slevk/MAINTAINERS @@ -1,5 +1,5 @@ MX6SLEVK BOARD -M: Fabio Estevam +M: Fabio Estevam M: Peng Fan S: Maintained F: board/freescale/mx6slevk/ diff --git a/board/freescale/mx6sxsabreauto/MAINTAINERS b/board/freescale/mx6sxsabreauto/MAINTAINERS index 6f2ff44e78..692bbd9767 100644 --- a/board/freescale/mx6sxsabreauto/MAINTAINERS +++ b/board/freescale/mx6sxsabreauto/MAINTAINERS @@ -1,5 +1,5 @@ MX6SXSABREAUTO BOARD -M: Fabio Estevam +M: Fabio Estevam S: Maintained F: board/freescale/mx6sxsabreauto/ F: include/configs/mx6sxsabreauto.h diff --git a/board/freescale/mx6sxsabresd/MAINTAINERS b/board/freescale/mx6sxsabresd/MAINTAINERS index a56d252edb..b3c8b56f1f 100644 --- a/board/freescale/mx6sxsabresd/MAINTAINERS +++ b/board/freescale/mx6sxsabresd/MAINTAINERS @@ -1,5 +1,5 @@ MX6SXSABRESD BOARD -M: Fabio Estevam +M: Fabio Estevam S: Maintained F: board/freescale/mx6sxsabresd/ F: include/configs/mx6sxsabresd.h diff --git a/board/solidrun/mx6cuboxi/MAINTAINERS b/board/solidrun/mx6cuboxi/MAINTAINERS index bd098b479f..0558521667 100644 --- a/board/solidrun/mx6cuboxi/MAINTAINERS +++ b/board/solidrun/mx6cuboxi/MAINTAINERS @@ -1,6 +1,6 @@ MX6CUBOXI BOARD M: Baruch Siach -M: Fabio Estevam +M: Fabio Estevam S: Maintained F: board/solidrun/mx6cuboxi/ F: include/configs/mx6cuboxi.h diff --git a/board/technexion/pico-imx6ul/MAINTAINERS b/board/technexion/pico-imx6ul/MAINTAINERS index e9b5a97090..f94a011eef 100644 --- a/board/technexion/pico-imx6ul/MAINTAINERS +++ b/board/technexion/pico-imx6ul/MAINTAINERS @@ -1,6 +1,6 @@ TechNexion PICO-IMX6UL board M: Richard Hu -M: Fabio Estevam +M: Fabio Estevam S: Maintained F: board/technexion/pico-imx6ul/ F: include/configs/pico-imx6ul.h diff --git a/board/udoo/MAINTAINERS b/board/udoo/MAINTAINERS index b05243c429..195882b4c0 100644 --- a/board/udoo/MAINTAINERS +++ b/board/udoo/MAINTAINERS @@ -1,5 +1,5 @@ UDOO BOARD -M: Fabio Estevam +M: Fabio Estevam S: Maintained F: board/udoo/ F: include/configs/udoo.h diff --git a/board/wandboard/MAINTAINERS b/board/wandboard/MAINTAINERS index 00a31a9346..3c2a06cf09 100644 --- a/board/wandboard/MAINTAINERS +++ b/board/wandboard/MAINTAINERS @@ -1,5 +1,5 @@ WANDBOARD BOARD -M: Fabio Estevam +M: Fabio Estevam S: Maintained F: arch/arm/dts/imx6qdl-wandboard.dtsi F: arch/arm/dts/imx6qdl-wandboard-revb1.dtsi diff --git a/board/warp7/MAINTAINERS b/board/warp7/MAINTAINERS index 55f8c815d4..ebb21f81ad 100644 --- a/board/warp7/MAINTAINERS +++ b/board/warp7/MAINTAINERS @@ -1,5 +1,5 @@ WARP7 BOARD -M: Fabio Estevam +M: Fabio Estevam S: Maintained F: board/warp7/ F: include/configs/warp7.h From bb32c2a617673ff14970399e5519de0400614baf Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 8 Mar 2021 13:52:35 -0800 Subject: [PATCH 081/117] board: gateworks: venice: fix gsc_get_dev use dm_i2c_probe instead of i2c_get_chip which appears to be more reliable. Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam --- board/gateworks/venice/gsc.c | 27 ++++++++------------------- 1 file changed, 8 insertions(+), 19 deletions(-) diff --git a/board/gateworks/venice/gsc.c b/board/gateworks/venice/gsc.c index ad3f8d95d9..d2490e6063 100644 --- a/board/gateworks/venice/gsc.c +++ b/board/gateworks/venice/gsc.c @@ -125,29 +125,18 @@ enum { static struct udevice *gsc_get_dev(int busno, int slave) { - struct udevice *dev; + static const char * const i2c[] = { "i2c@30a20000", "i2c@30a30000" }; + struct udevice *dev, *bus; int ret; -#if (IS_ENABLED(CONFIG_SPL_BUILD)) - ret = i2c_get_chip_for_busnum(busno + 1, slave, 1, &dev); + ret = uclass_get_device_by_name(UCLASS_I2C, i2c[busno - 1], &bus); + if (ret) { + printf("GSC : failed I2C%d probe: %d\n", busno, ret); + return NULL; + } + ret = dm_i2c_probe(bus, slave, 0, &dev); if (ret) return NULL; -#else - struct udevice *bus; - - busno--; - - ret = uclass_get_device_by_seq(UCLASS_I2C, busno, &bus); - if (ret) { - printf("i2c%d: no bus %d\n", busno + 1, ret); - return NULL; - } - ret = i2c_get_chip(bus, slave, 1, &dev); - if (ret) { - printf("i2c%d@0x%02x: no chip %d\n", busno + 1, slave, ret); - return NULL; - } -#endif return dev; } From 72b3732d24f12b2279f93c05e6eb74452b2b284a Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 8 Mar 2021 13:52:36 -0800 Subject: [PATCH 082/117] board: gateworks: venice: increase CONFIG_SYS_SPL_MALLOC_SIZE commit 03f1f78a9b44 ("spl: fit: Prefer a malloc()'d buffer for loading images")' changed the way buffer allocation worked for SPL to a more flexible method. For venice this caused breakage that is resolved by increasing the size of CONFIG_SYS_SPL_MALLOC_SIZE as the current FIT slighly exceeds 512KiB. Additionally remove the unnecessary comment on CONFIG_SPL_BSS_MAX_SIZE and CONFIG_SYS_SPL_MALLOC_SIZE as the size is obvious from the define. Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam --- include/configs/imx8mm_venice.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index a406e91c84..91669255e1 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -19,9 +19,9 @@ #ifdef CONFIG_SPL_BUILD #define CONFIG_SPL_STACK 0x920000 #define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_1M /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x930000 From 3470b45abadb2a6517a59a846a08d9f75d1f8166 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Thu, 11 Mar 2021 22:00:34 +0200 Subject: [PATCH 083/117] colibri_imx6: adjust boot order Remove duplicate of mmc0, set this boot order: 1) SD 2) eMMC 3) USB 4) DHCP boot Fixes: 0e15165bc4e0 ("colibri_imx6: boot env configuration updates") Signed-off-by: Igor Opaniuk Signed-off-by: Oleksandr Suvorov --- include/configs/colibri_imx6.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index c014d6b2d5..5f5e201b4c 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -72,7 +72,6 @@ #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ From fdbf0e51ff29a185d5091aa1d175aa5851402b5b Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Thu, 11 Mar 2021 22:00:35 +0200 Subject: [PATCH 084/117] colibri_imx6ull/imx7: add missing tdxargs variable All the other boards have tdxargs specified for setting manual kernel command-line arguments. Add them also to NAND-based boards. Signed-off-by: Philippe Schenker Signed-off-by: Oleksandr Suvorov --- include/configs/colibri-imx6ull.h | 2 +- include/configs/colibri_imx7.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 2827c171c9..22ee2ba03e 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -63,7 +63,7 @@ "ubi.fm_autoconvert=1\0" \ "ubiboot=run setup; " \ "setenv bootargs ${defargs} ${ubiargs} " \ - "${setupargs} ${vidargs}; echo Booting from NAND...; " \ + "${setupargs} ${vidargs} ${tdxargs}; echo Booting from NAND...; " \ "ubi part ubi &&" \ "ubi read ${kernel_addr_r} kernel && " \ "ubi read ${fdt_addr_r} dtb && " \ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 85dd891055..2fffaa39c0 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -110,7 +110,7 @@ "ubi.fm_autoconvert=1\0" \ "ubiboot=run setup; " \ "setenv bootargs ${defargs} ${ubiargs} " \ - "${setupargs} ${vidargs}; echo Booting from NAND...; " \ + "${setupargs} ${vidargs} ${tdxargs}; echo Booting from NAND...; " \ "ubi part ubi && run m4boot && " \ "ubi read ${kernel_addr_r} kernel && " \ "ubi read ${fdt_addr_r} dtb && " \ From 54398740ca8c222888a97ea0b9f4f2a53450c5fc Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Thu, 11 Mar 2021 22:00:36 +0200 Subject: [PATCH 085/117] apalis/colibri_imx6: remove video= settings Since Toradex provides the full set of overlays for Linux kernel for display interfaces for both Apalis iMX6Q and Colibri iMX6DL modules, the video= settings are obsolete. Remove them. Signed-off-by: Oleksandr Suvorov --- include/configs/apalis_imx6.h | 5 +---- include/configs/colibri_imx6.h | 3 +-- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 0e81ef94d3..12de0105c6 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -163,10 +163,7 @@ "source ${loadaddr}\0" \ "splashpos=m,m\0" \ "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ - "vidargs=mxc_hdmi.only_cea=1 " \ - "video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24 " \ - "video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off " \ - "fbmem=32M\0 " + "vidargs=mxc_hdmi.only_cea=1 fbmem=32M\0" /* Miscellaneous configurable options */ #undef CONFIG_SYS_CBSIZE diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 5f5e201b4c..804a144a03 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -143,8 +143,7 @@ "source ${loadaddr}\0" \ "splashpos=m,m\0" \ "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ - "vidargs=video=mxcfb0:dev=lcd,640x480M@60,if=RGB666 " \ - "video=mxcfb1:off fbmem=8M\0 " + "vidargs=fbmem=8M\0" /* Miscellaneous configurable options */ #undef CONFIG_SYS_CBSIZE From f5c2c3705bd1ea42abe1e4e3b4b7661512c97c0b Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Thu, 11 Mar 2021 22:00:37 +0200 Subject: [PATCH 086/117] board: toradex: apalis-imx8x: fix build instructions Fix an URL for downloading the SCFW binary for an Apalis iMX8X and improve u-boot image build instructions. Signed-off-by: Oleksandr Suvorov --- doc/board/toradex/apalix-imx8x.rst | 33 ++++++++++++++++-------------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/doc/board/toradex/apalix-imx8x.rst b/doc/board/toradex/apalix-imx8x.rst index ce7dde8d00..efa7e0c72e 100644 --- a/doc/board/toradex/apalix-imx8x.rst +++ b/doc/board/toradex/apalix-imx8x.rst @@ -1,43 +1,46 @@ .. SPDX-License-Identifier: GPL-2.0+ -Apalis iMX8X V1.1A Module +Apalis iMX8X V1.1A Module (SoC NXP i.MX8QXP RevB) ========================== Quick Start ----------- -- Build the ARM trusted firmware binary -- Get scfw_tcm.bin and ahab-container.img +- Get and Build the ARM trusted firmware +- Get System Controller firmware +- Get SECO container - Build U-Boot - Load U-Boot binary using uuu - Flash U-Boot binary into the eMMC - Boot +Note: builddir is U-Boot build directory (source directory for in-tree builds) + Get and Build the ARM Trusted Firmware -------------------------------------- .. code-block:: bash - $ git clone -b toradex_imx_5.4.24_2.1.0 http://git.toradex.com/cgit/imx-atf.git - $ cd imx-atf/ - $ make PLAT=imx8qx bl31 + $ cd $(builddir) + $ git clone -b toradex_imx_5.4.70_2.3.0 http://git.toradex.com/cgit/imx-atf.git + $ make PLAT=imx8qx bl31 -C imx-atf + $ cp imx-atf/build/imx8qx/release/bl31.bin $(builddir) -Get scfw_tcm.bin and ahab-container.img +Get System Controller firmware --------------------------------------- .. code-block:: bash - $ wget https://github.com/toradex/i.MX-System-Controller-Firmware/blob/master/src/scfw_export_mx8qx_b0/build_mx8qx_b0/mx8qx-apalis-scfw-tcm.bin - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.6.3.bin - $ chmod +x imx-seco-3.6.3.bin - $ ./imx-seco-3.6.3.bin + $ wget https://github.com/toradex/i.MX-System-Controller-Firmware/raw/master/src/scfw_export_mx8qx_b0/build_mx8qx_b0/mx8qx-apalis-scfw-tcm.bin -Copy the following binaries to the U-Boot folder: +Get SECO container +--------------------------------------- .. code-block:: bash - $ cp imx-atf/build/imx8qx/release/bl31.bin . - $ cp imx-seco-3.6.3/firmware/seco/mx8qxb0-ahab-container.img mx8qx-ahab-container.imx8_defconfig + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.7.4.bin + $ sh imx-seco-3.7.4.bin + $ cp imx-seco-3.7.4/firmware/seco/mx8qxb0-ahab-container.img $(builddir)/mx8qx-ahab-container.img Build U-Boot ------------ @@ -58,7 +61,7 @@ to your host and execute uuu: .. code-block:: bash - sudo ./uuu u-boot/u-boot-dtb.imx + sudo ./uuu $(builddir)/u-boot-dtb.imx Flash the U-Boot Binary into the eMMC ------------------------------------- From bfa0d04e86507ed41bc86ece7a0ee6224a0bd3d8 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Thu, 1 Apr 2021 22:17:05 +0100 Subject: [PATCH 087/117] ARM: board: usbarmory: Import the usbarmory dts file Import the iMX53 based usbarmory dts files from Linux 5.12-rc1 Signed-off-by: Peter Robinson Cc: Andrej Rosano Cc: Fabio Estevam Cc: Stefano Babic Reviewed-by: Fabio Estevam --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx53-usbarmory.dts | 225 +++++++++++++++++++++++++++++++ 2 files changed, 227 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx53-usbarmory.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a643e45a0c..694eaa59ab 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -662,7 +662,8 @@ dtb-$(CONFIG_MX51) += \ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \ imx53-qsb.dtb \ imx53-kp.dtb \ - imx53-m53menlo.dtb + imx53-m53menlo.dtb \ + imx53-usbarmory.dtb ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),) dtb-y += \ diff --git a/arch/arm/dts/imx53-usbarmory.dts b/arch/arm/dts/imx53-usbarmory.dts new file mode 100644 index 0000000000..f34993a490 --- /dev/null +++ b/arch/arm/dts/imx53-usbarmory.dts @@ -0,0 +1,225 @@ +/* + * USB armory MkI device tree file + * https://inversepath.com/usbarmory + * + * Copyright (C) 2015, Inverse Path + * Andrej Rosano + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx53.dtsi" + +/ { + model = "Inverse Path USB armory"; + compatible = "inversepath,imx53-usbarmory", "fsl,imx53"; +}; + +/ { + chosen { + stdout-path = &uart1; + }; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + user { + label = "LED"; + gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +/* + * Not every i.MX53 P/N supports clock > 800MHz. + * As USB armory does not mount a specific P/N set a safe clock upper limit. + */ +&cpu0 { + operating-points = < + /* kHz */ + 166666 850000 + 400000 900000 + 800000 1050000 + >; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + status = "okay"; +}; + +&iomuxc { + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_i2c1_pmic: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0x80 + MX53_PAD_EIM_D28__I2C1_SDA 0x80 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX53_PAD_DISP0_DAT6__GPIO4_27 0x1e4 + >; + }; + + /* + * UART mode pin header configuration + * 3 - GPIO5[26], pull-down 100K + * 4 - GPIO5[27], pull-down 100K + * 5 - TX, pull-up 100K + * 6 - RX, pull-up 100K + * 7 - GPIO5[30], pull-down 100K + */ + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_CSI0_DAT8__GPIO5_26 0xc0 + MX53_PAD_CSI0_DAT9__GPIO5_27 0xc0 + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 + MX53_PAD_CSI0_DAT12__GPIO5_30 0xc0 + >; + }; +}; + +&i2c1 { + pinctrl-0 = <&pinctrl_i2c1_pmic>; + status = "okay"; + + ltc3589: pmic@34 { + compatible = "lltc,ltc3589-2"; + reg = <0x34>; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <591930>; + regulator-max-microvolt = <1224671>; + lltc,fb-voltage-divider = <100000 158000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <704123>; + regulator-max-microvolt = <1456803>; + lltc,fb-voltage-divider = <180000 191000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1341250>; + regulator-max-microvolt = <2775000>; + lltc,fb-voltage-divider = <270000 100000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + bb_out_reg: bb-out { + regulator-min-microvolt = <3387341>; + regulator-max-microvolt = <3387341>; + lltc,fb-voltage-divider = <511000 158000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-min-microvolt = <1306329>; + regulator-max-microvolt = <1306329>; + lltc,fb-voltage-divider = <100000 158000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-min-microvolt = <704123>; + regulator-max-microvolt = <1456806>; + lltc,fb-voltage-divider = <180000 191000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3200000>; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; From f980299004f3fffcc0462d0a1fcb644cecca95fe Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Thu, 1 Apr 2021 22:17:06 +0100 Subject: [PATCH 088/117] ARM: board: usbarmory: Convert to OF_CONTROL and DM Convert usbarmory to OF_CONTROL and DM for gpio, pin usb support on the i.MX53 based usbarmory. Signed-off-by: Peter Robinson Cc: Andrej Rosano Cc: Fabio Estevam Cc: Stefano Babic --- configs/usbarmory_defconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig index e1128e5d6a..39fe860e59 100644 --- a/configs/usbarmory_defconfig +++ b/configs/usbarmory_defconfig @@ -2,11 +2,13 @@ CONFIG_ARM=y CONFIG_ARCH_MX5=y CONFIG_SYS_TEXT_BASE=0x77800000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx53-usbarmory" CONFIG_SYS_MEMTEST_START=0x70000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x60000 CONFIG_TARGET_USBARMORY=y +CONFIG_OF_CONTROL=y # CONFIG_CMD_BMODE is not set CONFIG_DISTRO_DEFAULTS=y # CONFIG_USE_BOOTCOMMAND is not set @@ -14,13 +16,22 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_FUSE=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_DM_GPIO=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_MXC_UART=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX5=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_MX5=y CONFIG_OF_LIBFDT=y From a5f8cc3301240a04ba2e382752f3da55ef4dce40 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 2 Apr 2021 22:17:17 -0500 Subject: [PATCH 089/117] arm: dts: imx8mn, imx8mn-beacon: Sync dts files with Kernel 5.12-rc5 There have been a few updates including flexspi, so it's necessary to re-sync. Signed-off-by: Adam Ford --- arch/arm/dts/imx8mn-beacon-baseboard.dtsi | 71 +++++++++++++++++++++++ arch/arm/dts/imx8mn-beacon-som.dtsi | 63 +++++++++++++++++++- arch/arm/dts/imx8mn.dtsi | 46 ++++++++++++--- 3 files changed, 172 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi index 49bff19a78..376ca8ff72 100644 --- a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi +++ b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi @@ -34,6 +34,15 @@ }; }; + reg_audio: regulator-audio { + compatible = "regulator-fixed"; + regulator-name = "3v3_aud"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "vsd_3v3"; @@ -53,6 +62,20 @@ gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + sound { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8962>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + }; }; &ecspi2 { @@ -98,6 +121,44 @@ interrupt-parent = <&gpio4>; interrupts = <27 IRQ_TYPE_LEVEL_LOW>; }; + + wm8962: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; + clock-names = "xclk"; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; }; &snvs_pwrkey { @@ -177,6 +238,16 @@ >; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 diff --git a/arch/arm/dts/imx8mn-beacon-som.dtsi b/arch/arm/dts/imx8mn-beacon-som.dtsi index 52a50d97e0..de2cd0e320 100644 --- a/arch/arm/dts/imx8mn-beacon-som.dtsi +++ b/arch/arm/dts/imx8mn-beacon-som.dtsi @@ -4,6 +4,12 @@ */ / { + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + spi0 = &flexspi; + }; + usdhc1_pwrseq: usdhc1_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -36,11 +42,39 @@ cpu-supply = <&buck2_reg>; }; +/* DDR controller is running LPDDR at 800MHz which requires 0.95V */ +&a53_opp_table { + opp-1200000000 { + opp-microvolt = <950000>; + }; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; + phy-supply = <&buck6_reg>; phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; fsl,magic-packet; status = "okay"; @@ -56,6 +90,22 @@ }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -184,7 +234,7 @@ reg = <0x50>; }; - rtc@51 { + rtc: rtc@51 { compatible = "nxp,pcf85263"; reg = <0x51>; }; @@ -285,6 +335,17 @@ >; }; + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi index ee17902304..16ea500895 100644 --- a/arch/arm/dts/imx8mn.dtsi +++ b/arch/arm/dts/imx8mn.dtsi @@ -241,10 +241,12 @@ }; soc@0 { - compatible = "simple-bus"; + compatible = "fsl,imx8mn-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + nvmem-cells = <&imx8mn_uid>; + nvmem-cell-names = "soc_unique_id"; aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -253,7 +255,7 @@ #size-cells = <1>; ranges; - spba: bus@30000000 { + spba: spba-bus@30000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -531,9 +533,17 @@ #address-cells = <1>; #size-cells = <1>; + imx8mn_uid: unique-id@410 { + reg = <0x4 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + fec_mac_address: mac-address@90 { + reg = <0x90 6>; + }; }; anatop: anatop@30360000 { @@ -581,7 +591,9 @@ <&clk IMX8MN_CLK_NOC>, <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, - <&clk IMX8MN_SYS_PLL3>; + <&clk IMX8MN_SYS_PLL3>, + <&clk IMX8MN_AUDIO_PLL1>, + <&clk IMX8MN_AUDIO_PLL2>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, <&clk IMX8MN_ARM_PLL_OUT>, <&clk IMX8MN_SYS_PLL3_OUT>, @@ -589,7 +601,9 @@ assigned-clock-rates = <0>, <0>, <0>, <400000000>, <400000000>, - <600000000>; + <600000000>, + <393216000>, + <361267200>; }; src: reset-controller@30390000 { @@ -875,6 +889,19 @@ status = "disabled"; }; + flexspi: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, + <&clk IMX8MN_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + status = "disabled"; + }; + sdma1: dma-controller@30bd0000 { compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; reg = <0x30bd0000 0x10000>; @@ -903,13 +930,18 @@ assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, <&clk IMX8MN_CLK_ENET_TIMER>, <&clk IMX8MN_CLK_ENET_REF>, - <&clk IMX8MN_CLK_ENET_TIMER>; + <&clk IMX8MN_CLK_ENET_PHY_REF>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, <&clk IMX8MN_SYS_PLL2_100M>, - <&clk IMX8MN_SYS_PLL2_125M>; - assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + <&clk IMX8MN_SYS_PLL2_125M>, + <&clk IMX8MN_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + nvmem-cells = <&fec_mac_address>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + fsl,stop-mode = <&gpr 0x10 3>; status = "disabled"; }; From 8166bb24288ef97c1c5692ac950e357c4ec8d71d Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 2 Apr 2021 22:17:18 -0500 Subject: [PATCH 090/117] configs: imx8mn_beacon: Enable QSPI Support There is a QSPI chip connected to the FSPI. Enable the defconfig to support it. Signed-off-by: Adam Ford --- configs/imx8mn_beacon_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index d6a3385d8d..567a6e5e1e 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -49,6 +49,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -90,11 +91,14 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y @@ -116,6 +120,7 @@ CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_DM_THERMAL=y From 45dae4a3c717a3ecff0997000b0dbbd3d81d6d00 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Sun, 4 Apr 2021 20:21:33 +0200 Subject: [PATCH 091/117] board: freescale: imxrt1020-evk: fix console is not enabled while init dram While initializing dram in spl_dram_init(), mdelay() is called that in order calls get_ticks() that verifies if timer exists, if doesn't, it throws a panic(), but since preloader_console_init() has still not been called those panic()s will fail. This doesn't help debugging, so let's setup console before calling spl_dram_init() by moving it after spl_dram_init(). Signed-off-by: Giulio Benetti --- board/freescale/imxrt1020-evk/imxrt1020-evk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/imxrt1020-evk/imxrt1020-evk.c b/board/freescale/imxrt1020-evk/imxrt1020-evk.c index 35241acd22..479e66bddc 100644 --- a/board/freescale/imxrt1020-evk/imxrt1020-evk.c +++ b/board/freescale/imxrt1020-evk/imxrt1020-evk.c @@ -60,8 +60,8 @@ int spl_dram_init(void) void spl_board_init(void) { - spl_dram_init(); preloader_console_init(); + spl_dram_init(); arch_cpu_init(); /* to configure mpu for sdram rw permissions */ } From eeb47ee474876310bd345bc6b51185addc70a112 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Sun, 4 Apr 2021 20:21:34 +0200 Subject: [PATCH 092/117] board: freescale: imxrt1050-evk: fix console is not enabled while init dram While initializing dram in spl_dram_init(), mdelay() is called that in order calls get_ticks() that verifies if timer exists, if doesn't, it throws a panic(), but since preloader_console_init() has still not been called those panic()s will fail. This doesn't help debugging, so let's setup console before calling spl_dram_init() by moving it after spl_dram_init(). Signed-off-by: Giulio Benetti --- board/freescale/imxrt1050-evk/imxrt1050-evk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c b/board/freescale/imxrt1050-evk/imxrt1050-evk.c index b8d852f097..eb492390db 100644 --- a/board/freescale/imxrt1050-evk/imxrt1050-evk.c +++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.c @@ -60,8 +60,8 @@ int spl_dram_init(void) void spl_board_init(void) { - spl_dram_init(); preloader_console_init(); + spl_dram_init(); arch_cpu_init(); /* to configure mpu for sdram rw permissions */ } From 6bd8845ad40d7aa71d63d783221bdf50d9922179 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Sun, 4 Apr 2021 20:21:35 +0200 Subject: [PATCH 093/117] board: st: stm32f746-disco: fix console is not enabled while init dram While initializing dram in spl_dram_init(), mdelay() is called that in order calls get_ticks() that verifies if timer exists, if doesn't, it throws a panic(), but since preloader_console_init() has still not been called those panic()s will fail. This doesn't help debugging, so let's setup console before calling spl_dram_init() by moving it after spl_dram_init(). Signed-off-by: Giulio Benetti --- board/st/stm32f746-disco/stm32f746-disco.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 143cc6e1ea..efa38a0e26 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -69,8 +69,8 @@ int spl_dram_init(void) } void spl_board_init(void) { - spl_dram_init(); preloader_console_init(); + spl_dram_init(); arch_cpu_init(); /* to configure mpu for sdram rw permissions */ } u32 spl_boot_device(void) From ebea3e0f9ad78f0596a5f4bc38a5220582596746 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 2 Apr 2021 15:52:26 +0100 Subject: [PATCH 094/117] ARM: embestmx6boards: Import the marsboard/riotboard. dts files Import the iMX6 based marsboard and riotboard. dts files from Linux 5.12-rc1 Signed-off-by: Peter Robinson Cc: Fabio Estevam Cc: Stefano Babic Reviewed-by: Fabio Estevam --- arch/arm/dts/Makefile | 2 + arch/arm/dts/imx6dl-riotboard.dts | 594 ++++++++++++++++++++++++++++++ arch/arm/dts/imx6q-marsboard.dts | 417 +++++++++++++++++++++ 3 files changed, 1013 insertions(+) create mode 100644 arch/arm/dts/imx6dl-riotboard.dts create mode 100644 arch/arm/dts/imx6q-marsboard.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 694eaa59ab..48079ddc99 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -702,6 +702,7 @@ dtb-y += \ imx6dl-mamoj.dtb \ imx6dl-nitrogen6x.dtb \ imx6dl-pico.dtb \ + imx6dl-riotboard.dtb \ imx6dl-sabreauto.dtb \ imx6dl-sabresd.dtb \ imx6dl-wandboard-revd1.dtb \ @@ -742,6 +743,7 @@ dtb-y += \ imx6q-icore-rqs.dtb \ imx6q-kp.dtb \ imx6q-logicpd.dtb \ + imx6q-marsboard.dtb \ imx6q-mba6a.dtb \ imx6q-mba6b.dtb \ imx6q-mccmon6.dtb\ diff --git a/arch/arm/dts/imx6dl-riotboard.dts b/arch/arm/dts/imx6dl-riotboard.dts new file mode 100644 index 0000000000..065d3ab0f5 --- /dev/null +++ b/arch/arm/dts/imx6dl-riotboard.dts @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2014 Iain Paton + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include + +/ { + model = "RIoTboard i.MX6S"; + compatible = "riot,imx6s-riotboard", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + led0: user1 { + label = "user1"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6-riotboard-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&clks { + fsl,pmic-stby-poweroff; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Atheros AR8035 PHY */ + rgmii_phy: ethernet-phy@4 { + reg = <4>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <1000>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL", + "I2C3_SDA", "I2C4_SCL", + "I2C4_SDA", "", "", "", "", "", "", "", + "", "PWM3", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "USB_OTG_VBUS", "", + "UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", + "UART5_TXD", "UART5_RXD", "", "", "", "", "", "", + "GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "", + "CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO", + "CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27", + "CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31"; +}; + +&gpio5 { + gpio-line-names = + "", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06", + "GPIO5_07", + "GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO", + "CSPI2_CS0", "CSPI2_CLK", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio7 { + gpio-line-names = + "SD3_CD", "SD3_WP", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + pmic: pf0100@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + interrupt-parent = <&gpio5>; + interrupts = <16 8>; + fsl,pmic-stby-poweroff; + + regulators { + reg_vddcore: sw1ab { /* VDDARM_IN */ + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_vddsoc: sw1c { /* VDDSOC_IN */ + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_gen_3v3: sw2 { /* VDDHIGH_IN */ + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */ + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */ + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_ddr_vtt: sw4 { /* MIPI conn */ + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_5v_600mA: swbst { /* not used */ + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */ + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { /* VREF_DDR */ + regulator-boot-on; + regulator-always-on; + }; + + reg_vgen1_1v5: vgen1 { /* not used */ + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + reg_vgen2_1v2_eth: vgen2 { /* pcie ? */ + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + reg_vgen3_2v8: vgen3 { /* not used */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clocks = <&clks 116>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx6-riotboard { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */ + MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */ + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */ + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */ + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */ + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */ + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */ + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */ + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */ + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */ + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */ + >; + }; + }; +}; diff --git a/arch/arm/dts/imx6q-marsboard.dts b/arch/arm/dts/imx6q-marsboard.dts new file mode 100644 index 0000000000..05ee283882 --- /dev/null +++ b/arch/arm/dts/imx6q-marsboard.dts @@ -0,0 +1,417 @@ +/* + * Copyright (C) 2016 Sergio Prado (sergio.prado@e-labworks.com) + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include + +/ { + model = "Embest MarS Board i.MX6Dual"; + compatible = "embest,imx6q-marsboard", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + user1 { + label = "imx6:green:user1"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + user2 { + label = "imx6:green:user2"; + gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; + status = "okay"; + + m25p80@0 { + compatible = "microchip,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Atheros AR8035 PHY */ + rgmii_phy: ethernet-phy@4 { + reg = <4>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <1000>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_3p3v>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +&iomuxc { + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000b1 /* CS0 */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 + /* AR8035 pin strapping: IO voltage: pull up */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + /* AR8035 pin strapping: PHYADDR#0: pull down */ + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 + /* AR8035 pin strapping: PHYADDR#1: pull down */ + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 + /* AR8035 pin strapping: MODE#1: pull up */ + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + /* AR8035 pin strapping: MODE#3: pull up */ + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + /* AR8035 pin strapping: MODE#0: pull down */ + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 + /* GPIO16 -> AR8035 25MHz */ + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + /* RGMII_nRST */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 + /* AR8035 interrupt */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* LED1 */ + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* LED2 */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* USB OTG POWER ENABLE */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* WP */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17009 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10009 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17009 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17009 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17009 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17009 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17009 + >; + }; +}; From b5c6019dfc696ac7597e1de9b5b07bdf409eb51c Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 2 Apr 2021 15:52:27 +0100 Subject: [PATCH 095/117] ARM: marsboard: Enable OF_CONTROL and DM gpio/pin control MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable OF_CONTROL and DM for gpio and pin control support on the i.MX6Q based embestmx6boards marsboard. Signed-off-by: Peter Robinson Cc: "Eric Bénard" Cc: Fabio Estevam Cc: Stefano Babic --- configs/marsboard_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index d2bd9c46d2..4d15f0432e 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -2,11 +2,13 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6q-marsboard" CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x2000 CONFIG_MX6Q=y CONFIG_TARGET_EMBESTMX6BOARDS=y +CONFIG_OF_CONTROL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,DDR_MB=1024" CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" @@ -17,6 +19,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y @@ -25,8 +28,11 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y +CONFIG_DM_GPIO=y CONFIG_BOUNCE_BUFFER=y CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 From f3bd944817210f4a2792a8ab8366a8423503851e Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 2 Apr 2021 15:52:28 +0100 Subject: [PATCH 096/117] ARM: embestmx6boards: merge the riotboard's configs together MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It doesn't make much sense to have two separate configs for the riotboard so let's merge the SPL config into the main one for less duplication. Signed-off-by: Peter Robinson Cc: "Eric Bénard" Cc: Fabio Estevam Cc: Stefano Babic --- configs/riotboard_defconfig | 14 ++++++- configs/riotboard_spl_defconfig | 70 --------------------------------- 2 files changed, 13 insertions(+), 71 deletions(-) delete mode 100644 configs/riotboard_spl_defconfig diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index b652057d74..074c0d5b44 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -1,18 +1,29 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x60000 CONFIG_MX6S=y CONFIG_TARGET_EMBESTMX6BOARDS=y +CONFIG_SPL_TEXT_BASE=0x00908000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,DDR_MB=1024" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,SPL,DDR_MB=1024" CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_OS_BOOT=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -57,3 +68,4 @@ CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_RLE8=y CONFIG_BMP_16BPP=y CONFIG_OF_LIBFDT=y +CONFIG_SPL_OF_LIBFDT=y diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig deleted file mode 100644 index 95549ff5b7..0000000000 --- a/configs/riotboard_spl_defconfig +++ /dev/null @@ -1,70 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 -CONFIG_MX6S=y -CONFIG_TARGET_EMBESTMX6BOARDS=y -CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,SPL,DDR_MB=1024" -CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_RAW_IMAGE_SUPPORT=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_OS_BOOT=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 -CONFIG_DM=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_USDHC=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHY_ATHEROS=y -CONFIG_MII=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_THERMAL=y -CONFIG_USB=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_DM_VIDEO=y -# CONFIG_BACKLIGHT is not set -# CONFIG_CMD_VIDCONSOLE is not set -# CONFIG_VIDEO_BPP8 is not set -# CONFIG_VIDEO_BPP32 is not set -# CONFIG_VIDEO_ANSI is not set -CONFIG_SYS_WHITE_ON_BLACK=y -# CONFIG_PANEL is not set -CONFIG_VIDEO_IPUV3=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_BMP_16BPP=y -CONFIG_OF_LIBFDT=y -CONFIG_SPL_OF_LIBFDT=y From 10ce58c0814df5873b17b94669017f7f4080f33a Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 2 Apr 2021 15:52:29 +0100 Subject: [PATCH 097/117] ARM: riotboard: Enable OF_CONTROL and DM gpio/pin control MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable OF_CONTROL and DM for gpio and pin control support on the i.MX6D based riotboard. Signed-off-by: Peter Robinson Cc: "Eric Bénard" Cc: Fabio Estevam Cc: Stefano Babic --- configs/riotboard_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 074c0d5b44..0284f86405 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -5,10 +5,12 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-riotboard" CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x60000 CONFIG_MX6S=y CONFIG_TARGET_EMBESTMX6BOARDS=y +CONFIG_OF_CONTROL=y CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y @@ -27,6 +29,7 @@ CONFIG_SPL_OS_BOOT=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y @@ -36,9 +39,12 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_DM=y +CONFIG_DM_GPIO=y CONFIG_BOUNCE_BUFFER=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 From c32d240f70c207828171c4f8a55f07db7cc677d8 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 2 Apr 2021 15:52:30 +0100 Subject: [PATCH 098/117] ARM: embestmx6boards: convert the mars/riot boards to DM_MMC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Convert the two Embest boards to use DM MMC. Signed-off-by: Peter Robinson Cc: "Eric Bénard" Cc: Fabio Estevam Cc: Stefano Babic --- arch/arm/dts/imx6dl-riotboard-u-boot.dtsi | 8 ++ arch/arm/dts/imx6q-marsboard-u-boot.dtsi | 8 ++ board/embest/mx6boards/mx6boards.c | 137 ---------------------- configs/marsboard_defconfig | 1 + configs/riotboard_defconfig | 1 + 5 files changed, 18 insertions(+), 137 deletions(-) create mode 100644 arch/arm/dts/imx6dl-riotboard-u-boot.dtsi create mode 100644 arch/arm/dts/imx6q-marsboard-u-boot.dtsi diff --git a/arch/arm/dts/imx6dl-riotboard-u-boot.dtsi b/arch/arm/dts/imx6dl-riotboard-u-boot.dtsi new file mode 100644 index 0000000000..e51cd24d7e --- /dev/null +++ b/arch/arm/dts/imx6dl-riotboard-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/ { + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc3; + }; +}; diff --git a/arch/arm/dts/imx6q-marsboard-u-boot.dtsi b/arch/arm/dts/imx6q-marsboard-u-boot.dtsi new file mode 100644 index 0000000000..e51cd24d7e --- /dev/null +++ b/arch/arm/dts/imx6q-marsboard-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/ { + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc3; + }; +}; diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c index 65b3942e39..c3bbcff0cf 100644 --- a/board/embest/mx6boards/mx6boards.c +++ b/board/embest/mx6boards/mx6boards.c @@ -31,8 +31,6 @@ #include #include #include -#include -#include #include #include #include @@ -150,141 +148,6 @@ int board_phy_config(struct phy_device *phydev) return 0; } -iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ - MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -iomux_v3_cfg_t const riotboard_usdhc3_pads[] = { - MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ - MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - /* eMMC RST */ - MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg usdhc_cfg[3] = { - {USDHC2_BASE_ADDR}, - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) -#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - if (board_type == BOARD_IS_RIOTBOARD) - ret = !gpio_get_value(USDHC3_CD_GPIO); - else if (board_type == BOARD_IS_MARSBOARD) - ret = 1; /* eMMC/uSDHC3 is always present */ - break; - case USDHC4_BASE_ADDR: - ret = 1; /* eMMC/uSDHC4 is always present */ - break; - } - - return ret; -} - -int board_mmc_init(struct bd_info *bis) -{ - int ret; - int i; - - /* - * According to the board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * ** RiOTboard : - * mmc0 SDCard slot (bottom) - * mmc1 uSDCard slot (top) - * mmc2 eMMC - * ** MarSBoard : - * mmc0 uSDCard slot (bottom) - * mmc1 eMMC - */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - usdhc_cfg[0].max_bus_width = 4; - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - if (board_type == BOARD_IS_RIOTBOARD) { - imx_iomux_v3_setup_multiple_pads( - riotboard_usdhc3_pads, - ARRAY_SIZE(riotboard_usdhc3_pads)); - gpio_direction_input(USDHC3_CD_GPIO); - } else { - gpio_direction_output(IMX_GPIO_NR(7, 8) , 0); - udelay(250); - gpio_set_value(IMX_GPIO_NR(7, 8), 1); - } - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[1].max_bus_width = 4; - break; - case 2: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - usdhc_cfg[2].max_bus_width = 4; - gpio_direction_output(IMX_GPIO_NR(6, 8) , 0); - udelay(250); - gpio_set_value(IMX_GPIO_NR(6, 8), 1); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} -#endif - #ifdef CONFIG_MXC_SPI iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index 4d15f0432e..63fc60a884 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -30,6 +30,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 0284f86405..4f86a08e78 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -42,6 +42,7 @@ CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_BOUNCE_BUFFER=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y From ed3b1d9c8ce78a6875696f5b6ce42765a75ea36b Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 2 Apr 2021 15:52:31 +0100 Subject: [PATCH 099/117] ARM: embestmx6boards: convert mars/riot boards to DM_USB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Convert the marsboard/riotboard to use DM_USB. Signed-off-by: Peter Robinson Cc: "Eric Bénard" Cc: Fabio Estevam Cc: Stefano Babic --- configs/marsboard_defconfig | 1 + configs/riotboard_defconfig | 1 + include/configs/embestmx6boards.h | 1 - 3 files changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index 63fc60a884..3e7b8ef0f5 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -47,6 +47,7 @@ CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_DM_VIDEO=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 4f86a08e78..1e5dc39318 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -59,6 +59,7 @@ CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_DM_VIDEO=y diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index ff3a849a14..c49d4dc0e4 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -29,7 +29,6 @@ #define CONFIG_SYS_I2C_SPEED 100000 /* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 From 2668e2821365358d1010448b91fb6691e9e79700 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 2 Apr 2021 15:52:32 +0100 Subject: [PATCH 100/117] ARM: embestmx6boards: convert mars/riot boards to DM_ETH MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Convert the boards to use DM_ETH. Signed-off-by: Peter Robinson Cc: "Eric Bénard" Cc: Fabio Estevam Cc: Stefano Babic --- board/embest/mx6boards/mx6boards.c | 26 +------------------------- configs/marsboard_defconfig | 2 ++ configs/riotboard_defconfig | 2 ++ include/configs/embestmx6boards.h | 6 ------ 4 files changed, 5 insertions(+), 31 deletions(-) diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c index c3bbcff0cf..dda8502c6f 100644 --- a/board/embest/mx6boards/mx6boards.c +++ b/board/embest/mx6boards/mx6boards.c @@ -91,24 +91,6 @@ static void setup_iomux_uart(void) } iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - /* GPIO16 -> AR8035 25MHz */ - MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), /* AR8035 PHY Reset */ MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), /* AR8035 PHY Interrupt */ @@ -376,13 +358,6 @@ int overwrite_console(void) return 1; } -int board_eth_init(struct bd_info *bis) -{ - setup_iomux_enet(); - - return cpu_eth_init(bis); -} - int board_early_init_f(void) { u32 cputype = cpu_type(get_cpu_rev()); @@ -460,6 +435,7 @@ int board_late_init(void) else if (board_type == BOARD_IS_RIOTBOARD) add_board_boot_modes(marsboard_boot_modes); #endif + setup_iomux_enet(); return 0; } diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index 3e7b8ef0f5..2759c291da 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -40,6 +40,8 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_SPI=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 1e5dc39318..12af407400 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -52,6 +52,8 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_SPI=y diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index c49d4dc0e4..a29eec00ae 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -36,12 +36,6 @@ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 4 - #define CONFIG_ARP_TIMEOUT 200UL /* Physical Memory Map */ From 05cd77611f5ad1e6cde60d42a3be557f5868dce1 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 2 Apr 2021 15:52:33 +0100 Subject: [PATCH 101/117] ARM: embestmx6boards: convert the mars/riot boards to DM SPI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable DM_SPI and DM_SPI_FLASH on the mars/riot boards. Signed-off-by: Peter Robinson Cc: "Eric Bénard" Cc: Fabio Estevam Cc: Stefano Babic --- configs/marsboard_defconfig | 2 ++ configs/riotboard_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index 2759c291da..551d09bece 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -34,6 +34,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 @@ -45,6 +46,7 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 12af407400..d41b4ba070 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -46,6 +46,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 @@ -57,6 +58,7 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y From f3c4e3d81c05ce9e1f2257ef6e48643adf8a4f66 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 2 Apr 2021 17:52:47 +0100 Subject: [PATCH 102/117] ARM: board: udoo: Import UDOO dts files Import the i.MX6 based UDOO dts files from Linux 5.12-rc1. Signed-off-by: Peter Robinson Cc: Fabio Estevam Cc: Stefano Babic Reviewed-by: Fabio Estevam --- arch/arm/dts/Makefile | 2 + arch/arm/dts/imx6dl-udoo.dts | 14 ++ arch/arm/dts/imx6q-udoo.dts | 18 ++ arch/arm/dts/imx6qdl-udoo.dtsi | 324 +++++++++++++++++++++++++++++++++ 4 files changed, 358 insertions(+) create mode 100644 arch/arm/dts/imx6dl-udoo.dts create mode 100644 arch/arm/dts/imx6q-udoo.dts create mode 100644 arch/arm/dts/imx6qdl-udoo.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 48079ddc99..d994ac8374 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -702,6 +702,7 @@ dtb-y += \ imx6dl-mamoj.dtb \ imx6dl-nitrogen6x.dtb \ imx6dl-pico.dtb \ + imx6dl-udoo.dtb \ imx6dl-riotboard.dtb \ imx6dl-sabreauto.dtb \ imx6dl-sabresd.dtb \ @@ -751,6 +752,7 @@ dtb-y += \ imx6q-novena.dtb \ imx6q-pico.dtb \ imx6q-phytec-mira-rdk-nand.dtb \ + imx6q-udoo.dtb \ imx6q-sabreauto.dtb \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ diff --git a/arch/arm/dts/imx6dl-udoo.dts b/arch/arm/dts/imx6dl-udoo.dts new file mode 100644 index 0000000000..d871cac171 --- /dev/null +++ b/arch/arm/dts/imx6dl-udoo.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-udoo.dtsi" + +/ { + model = "Udoo i.MX6 Dual-lite Board"; + compatible = "udoo,imx6dl-udoo", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6q-udoo.dts b/arch/arm/dts/imx6q-udoo.dts new file mode 100644 index 0000000000..52e9f4a211 --- /dev/null +++ b/arch/arm/dts/imx6q-udoo.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-udoo.dtsi" + +/ { + model = "Udoo i.MX6 Quad Board"; + compatible = "udoo,imx6q-udoo", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6qdl-udoo.dtsi b/arch/arm/dts/imx6qdl-udoo.dtsi new file mode 100644 index 0000000000..d07d8f8345 --- /dev/null +++ b/arch/arm/dts/imx6qdl-udoo.dtsi @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ + +/ { + aliases { + backlight = &backlight; + panelchan = &panelchan; + panel7 = &panel7; + touchscreenp7 = &touchscreenp7; + }; + + chosen { + stdout-path = &uart2; + }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpio1 4 0>; + default-on; + status = "disabled"; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio2 4 0>; + pinctrl-0 = <&pinctrl_power_off>; + pinctrl-names = "default"; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + panel7: panel7 { + /* + * in reality it is a -20t (parallel) model, + * but with LVDS bridge chip attached, + * so it is equivalent to -19t model in drive + * characteristics + */ + compatible = "urt,umsh-8596md-19t"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel>; + power-supply = <®_panel>; + backlight = <&backlight>; + status = "disabled"; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_h1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */ + gpio = <&gpio7 12 0>; + }; + + reg_panel: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "lcd_panel"; + enable-active-high; + gpio = <&gpio1 2 0>; + }; + }; + + sound { + compatible = "fsl,imx6q-udoo-ac97", + "fsl,imx-audio-ac97"; + model = "fsl,imx6q-udoo-ac97"; + audio-cpu = <&ssi1>; + audio-routing = + "RX", "Mic Jack", + "Headphone Jack", "TX"; + mux-int-port = <1>; + mux-ext-port = <6>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touchscreenp7: touchscreenp7@55 { + compatible = "sitronix,st1232"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreenp7>; + reg = <0x55>; + interrupt-parent = <&gpio1>; + interrupts = <13 8>; + gpios = <&gpio1 15 0>; + status = "disabled"; + }; +}; + +&iomuxc { + imx6q-udoo { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x70 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x70 + >; + }; + + pinctrl_power_off: poweroffgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30 + >; + }; + + pinctrl_touchscreenp7: touchscreenp7grp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x70 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh: usbhgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 + >; + }; + + pinctrl_usbotg: usbotg { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x17059 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_ac97_running: ac97running { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x1b0b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + + pinctrl_ac97_warm_reset: ac97warmreset { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + + pinctrl_ac97_reset: ac97reset { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + }; +}; + +&ldb { + status = "okay"; + + panelchan: lvds-channel@0 { + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh>; + vbus-supply = <®_usb_h1_vbus>; + clocks = <&clks IMX6QDL_CLK_CKO>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + status = "okay"; +}; + +&audmux { + status = "okay"; +}; + +&ssi1 { + cell-index = <0>; + fsl,mode = "ac97-slave"; + pinctrl-names = "ac97-running", "ac97-reset", "ac97-warm-reset"; + pinctrl-0 = <&pinctrl_ac97_running>; + pinctrl-1 = <&pinctrl_ac97_reset>; + pinctrl-2 = <&pinctrl_ac97_warm_reset>; + ac97-gpios = <&gpio4 19 0 &gpio4 18 0 &gpio2 30 0>; + status = "okay"; +}; From 999f6bf50dae5a0b8892ca5d61e0842c9af126bd Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 2 Apr 2021 17:52:48 +0100 Subject: [PATCH 103/117] ARM: imx: udoo: Enable OF_CONTROL and DM gpio/pin control Enable OF_CONTROL and DM for gpio and pin control support on the i.MX6 based Udoo boards. Signed-off-by: Peter Robinson Cc: Fabio Estevam Cc: Stefano Babic --- configs/udoo_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig index f72b9645da..bcc88356ce 100644 --- a/configs/udoo_defconfig +++ b/configs/udoo_defconfig @@ -5,10 +5,13 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6q-udoo" +CONFIG_OF_LIST="imx6q-udoo imx6dl-udoo" CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x60000 CONFIG_MX6QDL=y CONFIG_TARGET_UDOO=y +CONFIG_OF_CONTROL=y CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y @@ -24,6 +27,7 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_SATA=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y @@ -32,9 +36,12 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y +CONFIG_DM_GPIO=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y CONFIG_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y From 41a6890d3dc2d8279e04893e696f006e4d3625ce Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 2 Apr 2021 17:52:49 +0100 Subject: [PATCH 104/117] ARM: imx: udoo: drop MTD config The UDOO doesn't have any MTD storage so drop the config. Signed-off-by: Peter Robinson Cc: Fabio Estevam Cc: Stefano Babic --- configs/udoo_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig index bcc88356ce..deec4bc82f 100644 --- a/configs/udoo_defconfig +++ b/configs/udoo_defconfig @@ -42,7 +42,6 @@ CONFIG_DWC_AHSATA=y CONFIG_FSL_USDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y -CONFIG_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y From 2d0401b1182e70234a184d73da57f5745f1c0598 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 2 Apr 2021 17:52:50 +0100 Subject: [PATCH 105/117] ARM: imx: udoo: Convert block devices to DM Enable DM block, DM MMC and DM SATA support on iMX6 Udoo convert board code to match the DM support. Signed-off-by: Peter Robinson Cc: Fabio Estevam Cc: Stefano Babic --- arch/arm/dts/imx6qdl-udoo-u-boot.dtsi | 7 +++++++ board/udoo/udoo.c | 30 --------------------------- configs/udoo_defconfig | 3 +++ include/configs/udoo.h | 6 ------ 4 files changed, 10 insertions(+), 36 deletions(-) create mode 100644 arch/arm/dts/imx6qdl-udoo-u-boot.dtsi diff --git a/arch/arm/dts/imx6qdl-udoo-u-boot.dtsi b/arch/arm/dts/imx6qdl-udoo-u-boot.dtsi new file mode 100644 index 0000000000..749791a13f --- /dev/null +++ b/arch/arm/dts/imx6qdl-udoo-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/ { + aliases { + mmc0 = &usdhc3; + }; +}; diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index d83f23dd35..c1acc25a9d 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -19,8 +19,6 @@ #include #include #include -#include -#include #include #include #include @@ -56,15 +54,6 @@ static iomux_v3_cfg_t const uart2_pads[] = { IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; -static iomux_v3_cfg_t const usdhc3_pads[] = { - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19), @@ -176,13 +165,6 @@ static void setup_iomux_wdog(void) gpio_direction_input(WDT_TRG); } -static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; /* Always present */ -} - int board_eth_init(struct bd_info *bis) { uint32_t base = IMX_FEC_BASE; @@ -217,15 +199,6 @@ free_bus: return ret; } -int board_mmc_init(struct bd_info *bis) -{ - SETUP_IOMUX_PADS(usdhc3_pads); - usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg.max_bus_width = 4; - - return fsl_esdhc_initialize(bis, &usdhc_cfg); -} - int board_early_init_f(void) { setup_iomux_wdog(); @@ -248,9 +221,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; -#ifdef CONFIG_SATA - setup_sata(); -#endif return 0; } diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig index deec4bc82f..2735f02af3 100644 --- a/configs/udoo_defconfig +++ b/configs/udoo_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 @@ -38,8 +39,10 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_MMC=y CONFIG_DWC_AHSATA=y CONFIG_FSL_USDHC=y +CONFIG_DM_SCSI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_PHYLIB=y diff --git a/include/configs/udoo.h b/include/configs/udoo.h index b4fbf8c638..25f40074c5 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -21,13 +21,7 @@ #define CONFIG_MXC_UART_BASE UART2_BASE /* SATA Configs */ - -#ifdef CONFIG_CMD_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 -#endif /* Network support */ From dec7755c442ff84358704a5566e4ae908afecf13 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 2 Apr 2021 17:52:51 +0100 Subject: [PATCH 106/117] ARM: imx: udoo: convert to DM_ETH Convert the UDOO board to use DM_ETH. Signed-off-by: Peter Robinson Cc: Fabio Estevam Cc: Stefano Babic --- board/udoo/udoo.c | 75 ++---------------------------------------- configs/udoo_defconfig | 2 ++ include/configs/udoo.h | 8 ----- 3 files changed, 4 insertions(+), 81 deletions(-) diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index c1acc25a9d..5c49388cbf 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -88,45 +88,8 @@ int mx6_rgmii_rework(struct phy_device *phydev) return 0; } -static iomux_v3_cfg_t const enet_pads1[] = { - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - /* RGMII reset */ - IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)), - /* Ethernet power supply */ - IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), - /* pin 32 - 1 - (MODE0) all */ - IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), - /* pin 31 - 1 - (MODE1) all */ - IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)), - /* pin 28 - 1 - (MODE2) all */ - IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), - /* pin 27 - 1 - (MODE3) all */ - IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), - /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const enet_pads2[] = { - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), -}; - static void setup_iomux_enet(void) { - SETUP_IOMUX_PADS(enet_pads1); - udelay(20); gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */ gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */ @@ -148,8 +111,6 @@ static void setup_iomux_enet(void) gpio_free(IMX_GPIO_NR(6, 27)); gpio_free(IMX_GPIO_NR(6, 28)); gpio_free(IMX_GPIO_NR(6, 29)); - - SETUP_IOMUX_PADS(enet_pads2); } static void setup_iomux_uart(void) @@ -165,40 +126,6 @@ static void setup_iomux_wdog(void) gpio_direction_input(WDT_TRG); } -int board_eth_init(struct bd_info *bis) -{ - uint32_t base = IMX_FEC_BASE; - struct mii_dev *bus = NULL; - struct phy_device *phydev = NULL; - int ret; - - setup_iomux_enet(); - -#ifdef CONFIG_FEC_MXC - bus = fec_get_miibus(base, -1); - if (!bus) - return -EINVAL; - /* scan phy 4,5,6,7 */ - phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); - - if (!phydev) { - ret = -EINVAL; - goto free_bus; - } - printf("using phy at %d\n", phydev->addr); - ret = fec_probe(bis, -1, base, bus, phydev); - if (ret) - goto free_phydev; -#endif - return 0; - -free_phydev: - free(phydev); -free_bus: - free(bus); - return ret; -} - int board_early_init_f(void) { setup_iomux_wdog(); @@ -232,6 +159,8 @@ int board_late_init(void) else env_set("board_rev", "MX6DL"); #endif + setup_iomux_enet(); + return 0; } diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig index 2735f02af3..064d545e34 100644 --- a/configs/udoo_defconfig +++ b/configs/udoo_defconfig @@ -48,6 +48,8 @@ CONFIG_PINCTRL_IMX6=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 25f40074c5..298369373a 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -23,14 +23,6 @@ /* SATA Configs */ #define CONFIG_LBA48 -/* Network support */ - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 6 - /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 From 63756575b42b8b4fb3f59cbbf0cedf03331bc2d2 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Wed, 3 Mar 2021 17:05:46 +0800 Subject: [PATCH 107/117] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the card clock output. After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support"), we meet SD3.0 card can't work at UHS mode, mmc_switch_voltage() fail because the second mmc_wait_dat0 return -ETIMEDOUT. According to SD spec, during voltage switch, need to gate off/on the card clock. If not set the FRC_SDCLK_ON, after CMD11, hardware will gate off the card clock automatically, so card do not detect the clock off/on behavior, so will draw the data0 line low until next command. Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support") Tested-by: Tim Harvey Signed-off-by: Haibo Chen --- drivers/mmc/fsl_esdhc_imx.c | 29 +++++++++++++++++++++-------- include/fsl_esdhc_imx.h | 2 ++ 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 09a5cd61e3..420bd25918 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -660,7 +660,10 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) clk = (pre_div << 8) | (div << 4); #ifdef CONFIG_FSL_USDHC - esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); + esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (ret) + pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n"); #else esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); #endif @@ -672,7 +675,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n"); #ifdef CONFIG_FSL_USDHC - esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); + esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); #else esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); #endif @@ -727,8 +730,14 @@ static void esdhc_set_strobe_dll(struct mmc *mmc) struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); struct fsl_esdhc *regs = priv->esdhc_regs; u32 val; + u32 tmp; + int ret; if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) { + esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (ret) + pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n"); esdhc_write32(®s->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET); /* @@ -746,6 +755,7 @@ static void esdhc_set_strobe_dll(struct mmc *mmc) pr_warn("HS400 strobe DLL status REF not lock!\n"); if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK)) pr_warn("HS400 strobe DLL status SLV not lock!\n"); + esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); } } @@ -969,14 +979,18 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) #ifdef MMC_SUPPORTS_TUNING if (mmc->clk_disable) { #ifdef CONFIG_FSL_USDHC - esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); + u32 tmp; + + esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (ret) + pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n"); #else esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); #endif } else { #ifdef CONFIG_FSL_USDHC - esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | - VENDORSPEC_CKEN); + esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); #else esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); #endif @@ -1052,7 +1066,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) #ifndef CONFIG_FSL_USDHC esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); #else - esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); + esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); #endif /* Set the initial clock speed */ @@ -1190,8 +1204,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, esdhc_write32(®s->autoc12err, 0); esdhc_write32(®s->clktunectrlstatus, 0); #else - esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | - VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); + esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); #endif if (priv->vs18_enable) diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h index 45ed635a77..b092034464 100644 --- a/include/fsl_esdhc_imx.h +++ b/include/fsl_esdhc_imx.h @@ -39,6 +39,7 @@ #define VENDORSPEC_HCKEN 0x00001000 #define VENDORSPEC_IPGEN 0x00000800 #define VENDORSPEC_INIT 0x20007809 +#define VENDORSPEC_FRC_SDCLK_ON 0x00000100 #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) @@ -96,6 +97,7 @@ #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) #define PRSSTAT_BWEN (0x00000400) +#define PRSSTAT_SDOFF (0x00000080) #define PRSSTAT_SDSTB (0X00000008) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002) From 123526e4a491aa823b7edeadb97060e909f20452 Mon Sep 17 00:00:00 2001 From: Trevor Woerner Date: Mon, 22 Mar 2021 11:31:28 -0400 Subject: [PATCH 108/117] mx23_olinuxino: enable device tree Add the dts file for the Olimex Olinuxino from the linux kernel, and enable its use in this machine's defconfig. Signed-off-by: Trevor Woerner --- arch/arm/dts/Makefile | 3 + arch/arm/dts/imx23-olinuxino.dts | 131 +++++++++++++++++++++++++++++++ configs/mx23_olinuxino_defconfig | 3 +- 3 files changed, 136 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx23-olinuxino.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d994ac8374..4df1f037e1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -653,6 +653,9 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ dtb-$(CONFIG_MX23) += \ imx23-evk.dtb +dtb-$(CONFIG_TARGET_MX23_OLINUXINO) += \ + imx23-olinuxino.dtb + dtb-$(CONFIG_MX28) += \ imx28-xea.dtb diff --git a/arch/arm/dts/imx23-olinuxino.dts b/arch/arm/dts/imx23-olinuxino.dts new file mode 100644 index 0000000000..0729e72f22 --- /dev/null +++ b/arch/arm/dts/imx23-olinuxino.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ + +/dts-v1/; +#include +#include "imx23.dtsi" + +/ { + model = "i.MX23 Olinuxino Low Cost Board"; + compatible = "olimex,imx23-olinuxino", "fsl,imx23"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x04000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: spi@80010000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; + bus-width = <4>; + broken-cd; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_GPMI_ALE__GPIO_0_17 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_pin_gpio2_1: led_gpio2_1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_SSP1_DETECT__GPIO_2_1 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + }; + + ssp1: spi@80034000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx23-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + }; + }; + + apbx@80040000 { + lradc@80050000 { + status = "okay"; + }; + + i2c: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_b>; + status = "okay"; + }; + + duart: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + auart0: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; + }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + dr_mode = "host"; + vbus-supply = <®_usb0_vbus>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb0_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */ + gpio = <&gpio0 17 0>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_gpio2_1>; + + user { + label = "green"; + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig index 0da54c9e76..2bf6818ee3 100644 --- a/configs/mx23_olinuxino_defconfig +++ b/configs/mx23_olinuxino_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_TEXT_BASE=0x00001000 CONFIG_TARGET_MX23_OLINUXINO=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx23-olinuxino" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y @@ -24,6 +25,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -44,4 +46,3 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_OF_LIBFDT=y From 52bbcc340a5fbdaa46e26253c67d84b7af8f654e Mon Sep 17 00:00:00 2001 From: Trevor Woerner Date: Mon, 22 Mar 2021 11:31:29 -0400 Subject: [PATCH 109/117] mx23_olinuxino: convert MMC to driver model Convert the Olimex Olinuxino board's support for MMC to driver model following Fabio Estevam's excellent example from: commit: 23013aa9619881290dbeb6217f1fab863869050e: mx23evk: Convert to driver model Signed-off-by: Trevor Woerner --- arch/arm/dts/imx23-olinuxino-u-boot.dtsi | 5 +++++ board/olimex/mx23_olinuxino/mx23_olinuxino.c | 12 ------------ configs/mx23_olinuxino_defconfig | 4 +++- 3 files changed, 8 insertions(+), 13 deletions(-) create mode 100644 arch/arm/dts/imx23-olinuxino-u-boot.dtsi diff --git a/arch/arm/dts/imx23-olinuxino-u-boot.dtsi b/arch/arm/dts/imx23-olinuxino-u-boot.dtsi new file mode 100644 index 0000000000..dee8433696 --- /dev/null +++ b/arch/arm/dts/imx23-olinuxino-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&ssp0 { + non-removable; +}; diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index d1e189cbb6..bdd5fcd76a 100644 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c @@ -57,18 +57,6 @@ int dram_init(void) return mxs_dram_init(); } -#ifdef CONFIG_CMD_MMC -static int mx23_olx_mmc_cd(int id) -{ - return 1; /* Card always present */ -} - -int board_mmc_init(struct bd_info *bis) -{ - return mxsmmc_initialize(bis, 0, NULL, mx23_olx_mmc_cd); -} -#endif - int board_init(void) { /* Adress of boot parameters */ diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig index 2bf6818ee3..680611cd01 100644 --- a/configs/mx23_olinuxino_defconfig +++ b/configs/mx23_olinuxino_defconfig @@ -12,6 +12,7 @@ CONFIG_TARGET_MX23_OLINUXINO=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_DEFAULT_DEVICE_TREE="imx23-olinuxino" +# CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y @@ -30,6 +31,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y +CONFIG_DM=y CONFIG_MXS_GPIO=y CONFIG_LED_STATUS=y CONFIG_LED_STATUS_GPIO=y @@ -39,10 +41,10 @@ CONFIG_LED_STATUS_STATE=2 CONFIG_LED_STATUS_BOOT_ENABLE=y CONFIG_LED_STATUS_BOOT=0 CONFIG_LED_STATUS_CMD=y +CONFIG_DM_MMC=y CONFIG_MMC_MXS=y CONFIG_CONS_INDEX=0 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y From 3da9630b8c4c7dc61090ef43b7be4aaadf7e735b Mon Sep 17 00:00:00 2001 From: Niel Fourie Date: Mon, 22 Mar 2021 14:05:11 +0100 Subject: [PATCH 110/117] ARM: pcm058: Match mainline Linux NAND ECC layout/behaviour Enabled "fsl,legacy-bch-geometry" in U-Boot device tree overlay to match the legacy BCH geometry layout, which mainline Linux applies when "fsl,use-minimum-ecc" is not specified in the device tree. Reinstated SYS_NAND_ONFI_DETECTION, which when disabled, masked the mismatch on SOMs with Winbond NAND flash chips. Signed-off-by: Niel Fourie --- arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi | 4 ++++ include/configs/pcm058.h | 1 + 2 files changed, 5 insertions(+) diff --git a/arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi b/arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi index 8555be1696..5a64f86b11 100644 --- a/arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi +++ b/arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi @@ -40,3 +40,7 @@ &m25p80 { u-boot,dm-spl; }; + +&gpmi { + fsl,legacy-bch-geometry; +}; diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 4f03699117..bc48e80949 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -19,6 +19,7 @@ /* Enable NAND support */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR From 59e3d1bd4992b38b118887397632bf4d3568baaf Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 25 Mar 2021 01:20:48 +0100 Subject: [PATCH 111/117] doc: imx: psb: Document usage of SRC_GPR10 PERSIST_SECONDARY_BOOT for A/B switching Document SRC_GPR10 PERSIST_SECONDARY_BOOT functionality. This is useful for reliable bootloader A/B updates, as it permits switching between two copies of bootloader at different offsets of the same storage. The switch happens in case one copy is corrupted OR can be enforced by user. This functionality is present at least since i.MX53, however is poorly documented in all known SoC datasheets, hence this document aims to clarify the usage, currently on i.MX7D and i.MX8MM. Signed-off-by: Marek Vasut # Original MX7D work, this document Signed-off-by: Igor Opaniuk # All the MX8M work Cc: Christoph Niedermaier Cc: Fabio Estevam Cc: Harald Seiler Cc: Igor Opaniuk Cc: Jan Kiszka Cc: Ludwig Zenz Cc: Marcel Ziswiler Cc: Peng Fan Cc: Stefano Babic Cc: Ye Li Cc: uboot-imx Reviewed-by: Peng Fan --- doc/imx/index.rst | 9 +++ doc/imx/misc/index.rst | 9 +++ doc/imx/misc/psb.rst | 174 +++++++++++++++++++++++++++++++++++++++++ doc/index.rst | 11 +++ 4 files changed, 203 insertions(+) create mode 100644 doc/imx/index.rst create mode 100644 doc/imx/misc/index.rst create mode 100644 doc/imx/misc/psb.rst diff --git a/doc/imx/index.rst b/doc/imx/index.rst new file mode 100644 index 0000000000..b225b1d183 --- /dev/null +++ b/doc/imx/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +NXP i.MX Machine-specific doc +============================= + +.. toctree:: + :maxdepth: 2 + + misc/index diff --git a/doc/imx/misc/index.rst b/doc/imx/misc/index.rst new file mode 100644 index 0000000000..85fbdb6588 --- /dev/null +++ b/doc/imx/misc/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Miscellaneous +============= + +.. toctree:: + :maxdepth: 2 + + psb diff --git a/doc/imx/misc/psb.rst b/doc/imx/misc/psb.rst new file mode 100644 index 0000000000..4d6f001b74 --- /dev/null +++ b/doc/imx/misc/psb.rst @@ -0,0 +1,174 @@ +i.MX7D/i.MX8MM SRC_GPR10 PERSIST_SECONDARY_BOOT for bootloader A/B switching +============================================================================ + +Introduction +------------ +Since at least iMX53 until iMX8MM, it is possible to have two copies of +bootloader in SD/eMMC and switch between them. The switch is triggered +either by the BootROM in case the bootloader image is faulty OR can be +enforced by the user. + +Operation +--------- + #. Upon Power-On Reset (POR) + + - SRC_GPR10 bit PERSIST_SECONDARY_BOOT is set to 0 + - BootROM attempts to start bootloader A-copy + + - if A-copy valid + + - BootROM starts A-copy + - END + + - if A-copy NOT valid + + - BootROM sets SRC_GPR10 bit PERSIST_SECONDARY_BOOT to 1 + - BootROM triggers WARM reset, GOTO 1) + - END + + #. Upon COLD Reset + + - GOTO 1) + - END + + #. Upon WARM Reset + + - SRC_GPR10 bit PERSIST_SECONDARY_BOOT is retained + + - if SRC_GPR10 bit PERSIST_SECONDARY_BOOT is 0 + + - BootROM attempts to start bootloader A-copy + + - if A-copy valid + + - BootROM starts A-copy + - END + + - if A-copy NOT valid + + - BootROM sets SRC_GPR10 bit PERSIST_SECONDARY_BOOT to 1 + - BootROM triggers WARM reset. GOTO 1.3) + - END + + - if SRC_GPR10 bit PERSIST_SECONDARY_BOOT is 1 + + - BootROM attempts to start bootloader B-copy + + - if B-copy valid + + - BootROM starts B-copy + - END + + - if B-copy NOT valid + - System hangs + - END + +Setup +----- +The bootloader A-copy must be placed at predetermined offset in SD/eMMC. The +bootloader B-copy area offset is determined by an offset stored in Secondary +Image Table (SIT). The SIT must be placed at predetermined offset in SD/eMMC. + +The following table contains offset of SIT, bootloader A-copy and recommended +bootloader B-copy offset. The offsets are in 512 Byte sector units (that is +offset 0x1 means 512 Bytes from the start of SD/eMMC card data partition). +For details on the addition of two numbers in recommended B-copy offset, see +SIT format below. + ++----------+--------------------+-----------------------+-----------------------------+ +| SoC | SIT offset (fixed) | A-copy offset (fixed) | B-copy offset (recommended) | ++----------+--------------------+-----------------------+-----------------------------+ +| iMX7D | 0x1 | 0x2 | 0x800+0x2 | ++----------+--------------------+-----------------------+-----------------------------+ +| iMX8MM | 0x41 | 0x42 | 0x1000+0x42 | ++----------+--------------------+-----------------------+-----------------------------+ + +SIT format +~~~~~~~~~~ +SIT is a 20 byte long structure containing of 5 32-bit words. Those encode +bootloader B-copy area offset (called "firstSectorNumber"), magic value +(called "tag") that is always 0x00112233, and three unused words set to 0. +SIT is documented in [1] and [2]. Example SIT are below:: + + $ hexdump -vC sit-mx7d.bin + 00000000 00 00 00 00 + 00000004 00 00 00 00 + 00000008 33 22 11 00 <--- This is the "tag" + 0000000c 00 08 00 00 <--- This is the "firstSectorNumber" + 00000010 00 00 00 00 + + $ hexdump -vC sit-mx8mm.bin + 00000000 00 00 00 00 + 00000004 00 00 00 00 + 00000008 33 22 11 00 <--- This is the "tag" + 0000000c 00 10 00 00 <--- This is the "firstSectorNumber" + 00000010 00 00 00 00 + +B-copy area offset ("firstSectorNumber") is offset, in units of 512 Byte +sectors, that is added to the start of boot media when switching between +A-copy and B-copy. For A-copy, this offset is 0x0. For B-copy, this offset +is determined by SIT (e.g. if firstSectorNumber is 0x1000 as it is above +in sit-mx8mm.bin, then the B-copy offset is 0x1000 sectors = 2 MiB). + +Bootloader A-copy (e.g. u-boot.imx or flash.bin) is placed at fixed offset +from A-copy area offset (e.g. 0x2 sectors from sector 0x0 for iMX7D, which +means u-boot.imx A-copy must be written to sector 0x2). + +The same applies to bootloader B-copy, which is placed at fixed offset from +B-copy area offset determined by SIT (e.g. 0x2 sectors from sector 0x800 [see +sit-mx7d.bin example above, this can be changed in SIT firstSectorNumber] for +iMX7D, which means u-boot.imx B-copy must be written to sector 0x802) + +**WARNING:** +B-copy area offset ("firstSectorNumber") is NOT equal to bootloader +(image, which is u-boot.imx or flash.bin) B-copy offset. + +To generate SIT, use for example the following bourne shell printf command:: + +$ printf '\x0\x0\x0\x0\x0\x0\x0\x0\x33\x22\x11\x00\x00\x08\x00\x00\x0\x0\x0\x0' > sit-mx7d.bin +$ printf '\x0\x0\x0\x0\x0\x0\x0\x0\x33\x22\x11\x00\x00\x10\x00\x00\x0\x0\x0\x0' > sit-mx8mm.bin + +Write bootloader A/B copy and SIT to SD/eMMC +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Examples of writing SIT and two copies of bootloader to SD or eMMC: + +- iMX8MM, SD card at /dev/sdX, Linux command line + :: + + $ dd if=sit-mx8mm.bin of=/dev/sdX bs=512 seek=65 + $ dd if=flash.bin of=/dev/sdX bs=512 seek=66 + $ dd if=flash.bin of=/dev/sdX bs=512 seek=4162 + +- iMX8MM, eMMC 1 data partition, U-Boot command line + :: + + => mmc partconf 1 0 0 0 + + => dhcp ${loadaddr} sit-mx8mm.bin + => mmc dev 1 + => mmc write ${loadaddr} 0x41 0x1 + + => dhcp ${loadaddr} flash.bin + => setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt + => mmc dev 1 + => mmc write ${loadaddr} 0x42 ${blkcnt} + => mmc write ${loadaddr} 0x1042 ${blkcnt} + +WARM reset into B-copy using WDT +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To perform a reboot into B-copy, the PERSIST_SECONDARY_BOOT must be set +in SRC_GPR0 register. Example on iMX8MM:: + + => mw 0x30390098 0x40000000 + +A WARM reset can be triggered using WDT as follows:: + + => mw.w 0x30280000 0x25 + +References +---------- + +.. [1] i.MX 7Dual Applications Processor Reference Manual, Rev. 1, 01/2018 ; section 6.6.5.3.5 Redundant boot support for expansion device +.. [2] i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020 ; section 6.1.5.4.5 Redundant boot support for expansion device diff --git a/doc/index.rst b/doc/index.rst index 02de1d4684..8066fcbfc0 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -64,6 +64,17 @@ implementation. arch/index +Machine-specific doc +-------------------- + +These books provide programming details about machine-specific +implementation. + +.. toctree:: + :maxdepth: 2 + + imx/index + Board-specific doc ------------------ From 50ab3bde308972fab3cf1ee29c292d139601c6c4 Mon Sep 17 00:00:00 2001 From: Yuichiro Goto Date: Mon, 29 Mar 2021 09:14:02 +0900 Subject: [PATCH 112/117] imx: imx6ull: fix pinmux sel_input value for uart5 pins sel_input value for the following uart5 pins is different between i.MX6UL and i.MX6ULL: MX6_PAD_UART5_TX_DATA__UART5_DTE_RX MX6_PAD_UART5_RX_DATA__UART5_DCE_RX MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS MX6_PAD_CSI_DATA02__UART5_DCE_RTS As sel_input value for the second one is fixed by the previous commit, fix the rest. Signed-off-by: Yuichiro Goto --- arch/arm/include/asm/arch-mx6/mx6ull_pins.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h index de4a1abc27..842d0caa64 100644 --- a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h @@ -326,7 +326,7 @@ enum { MX6_PAD_UART5_TX_DATA__UART5_DCE_TX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0000, 0, 0), - MX6_PAD_UART5_TX_DATA__UART5_DTE_RX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 4, 0), + MX6_PAD_UART5_TX_DATA__UART5_DTE_RX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 6, 0), MX6_PAD_UART5_TX_DATA__ENET2_CRS = IOMUX_PAD(0x0348, 0x00BC, 1, 0x0000, 0, 0), MX6_PAD_UART5_TX_DATA__I2C2_SCL = IOMUX_PAD(0x0348, 0x00BC, IOMUX_CONFIG_SION | 2, 0x05AC, 2, 0), MX6_PAD_UART5_TX_DATA__CSI_DATA14 = IOMUX_PAD(0x0348, 0x00BC, 3, 0x04FC, 0, 0), @@ -363,7 +363,7 @@ enum { MX6_PAD_ENET1_RX_DATA1__USDHC2_LCTL = IOMUX_PAD(0x0354, 0x00C8, 8, 0x0000, 0, 0), MX6_PAD_ENET1_RX_EN__ENET1_RX_EN = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 3, 0), + MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 5, 0), MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0), MX6_PAD_ENET1_RX_EN__CSI_DATA18 = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0), MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0), @@ -373,7 +373,7 @@ enum { MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0), MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 4, 0), + MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 6, 0), MX6_PAD_ENET1_TX_DATA0__CSI_DATA19 = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0), MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0), MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03 = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0), @@ -1012,7 +1012,7 @@ enum { MX6_PAD_CSI_DATA02__EIM_AD02 = IOMUX_PAD(0x0478, 0x01EC, 4, 0x0000, 0, 0), MX6_PAD_CSI_DATA02__GPIO4_IO23 = IOMUX_PAD(0x0478, 0x01EC, 5, 0x0000, 0, 0), MX6_PAD_CSI_DATA02__SAI1_RX_SYNC = IOMUX_PAD(0x0478, 0x01EC, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA02__UART5_DCE_RTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 5, 0), + MX6_PAD_CSI_DATA02__UART5_DCE_RTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 7, 0), MX6_PAD_CSI_DATA02__UART5_DTE_CTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0000, 0, 0), MX6_PAD_CSI_DATA03__CSI_DATA05 = IOMUX_PAD(0x047C, 0x01F0, 0, 0x04CC, 0, 0), From ba7e5dbf383b7094a3e65241660864c4fe78e20d Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 16 Mar 2021 21:46:39 +0100 Subject: [PATCH 113/117] imx6: icorem6: chmod 644 enigcam.bmp Bitmap files should not be executable. Signed-off-by: Heinrich Schuchardt Reviewed-by: Michael Trimarchi --- tools/logos/engicam.bmp | Bin 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 tools/logos/engicam.bmp diff --git a/tools/logos/engicam.bmp b/tools/logos/engicam.bmp old mode 100755 new mode 100644 From 1e595a81d9bc0d6fd30e3ba17e3f8a9278a381f8 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Mon, 22 Mar 2021 18:55:37 +0800 Subject: [PATCH 114/117] mmc: fsl_esdhc_imx: remove redundant cmd11 related code. Common code already handle the voltage switch sequence based on spec, so remove the redundant voltage switch code. Signed-off-by: Haibo Chen --- drivers/mmc/fsl_esdhc_imx.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 420bd25918..93fd934379 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -521,15 +521,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, goto out; } - /* Switch voltage to 1.8V if CMD11 succeeded */ - if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { - esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); - - printf("Run CMD11 1.8V switch\n"); - /* Sleep for 5 ms - max time for card to switch to 1.8V */ - udelay(5000); - } - /* Workaround for ESDHC errata ENGcm03648 */ if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { int timeout = 50000; From 8974ff1a60365dedf1192632f5e0c21680d49dbc Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Mon, 22 Mar 2021 18:55:38 +0800 Subject: [PATCH 115/117] mmc: fsl_esdhc_imx: add extra delay for IO voltage switch if necessary Some board like imx8mm-evkb, IO voltage switch from 3.3v to 1.8v need around 18ms, common code only delay 10ms, so need to delay extra 8ms. Otherwise voltage switch will timeout when wait for data0 line. This IO voltage switch time depends on board design, depend on the PMIC and capacitance. imx8mm-evkb board use PCA9450(PMIC) and 10uF capacitance. Signed-off-by: Haibo Chen --- arch/arm/dts/imx8mm-evk-u-boot.dtsi | 1 + drivers/mmc/fsl_esdhc_imx.c | 12 ++++++++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index 495bef3d38..3701557dec 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -113,6 +113,7 @@ u-boot,dm-spl; sd-uhs-sdr104; sd-uhs-ddr50; + fsl,signal-voltage-switch-extra-delay-ms = <8>; }; &usdhc3 { diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 93fd934379..a4675838e5 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -146,6 +146,7 @@ struct esdhc_soc_data { * @start_tuning_tap: the start point for tuning in tuning_ctrl register * @strobe_dll_delay_target: settings in strobe_dllctrl * @signal_voltage: indicating the current voltage + * @signal_voltage_switch_extra_delay_ms: extra delay for IO voltage switch * @cd_gpio: gpio for card detection * @wp_gpio: gpio for write protection */ @@ -170,6 +171,7 @@ struct fsl_esdhc_priv { u32 tuning_start_tap; u32 strobe_dll_delay_target; u32 signal_voltage; + u32 signal_voltage_switch_extra_delay_ms; #if CONFIG_IS_ENABLED(DM_REGULATOR) struct udevice *vqmmc_dev; struct udevice *vmmc_dev; @@ -836,6 +838,14 @@ static int esdhc_set_voltage(struct mmc *mmc) } #endif esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); + /* + * some board like imx8mm-evk need about 18ms to switch + * the IO voltage from 3.3v to 1.8v, common code only + * delay 10ms, so need to delay extra time to make sure + * the IO voltage change to 1.8v. + */ + if (priv->signal_voltage_switch_extra_delay_ms) + mdelay(priv->signal_voltage_switch_extra_delay_ms); if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT) return 0; @@ -1450,6 +1460,8 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev) val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target", ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT); priv->strobe_dll_delay_target = val; + val = fdtdec_get_int(fdt, node, "fsl,signal-voltage-switch-extra-delay-ms", 0); + priv->signal_voltage_switch_extra_delay_ms = val; if (dev_read_bool(dev, "broken-cd")) priv->broken_cd = 1; From c174c0623b02d7ae0965fd089934a490a95294c3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 5 Mar 2021 19:11:49 -0300 Subject: [PATCH 116/117] pico-imx6ul: Pass the PMIC I2C address in pmic_get() Pass "pfuze3000@8" in pmic_get() so that the PMIC node can be found in the devicetree. Signed-off-by: Fabio Estevam Reviewed-by: Jaehoon Chung --- board/technexion/pico-imx6ul/pico-imx6ul.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/technexion/pico-imx6ul/pico-imx6ul.c b/board/technexion/pico-imx6ul/pico-imx6ul.c index 62a54d0c8e..682c88dee7 100644 --- a/board/technexion/pico-imx6ul/pico-imx6ul.c +++ b/board/technexion/pico-imx6ul/pico-imx6ul.c @@ -159,7 +159,7 @@ int power_init_board(void) struct udevice *dev; int ret, dev_id, rev_id; - ret = pmic_get("pfuze3000", &dev); + ret = pmic_get("pfuze3000@8", &dev); if (ret == -ENODEV) return 0; if (ret != 0) From 2fc93e5bafdae7cf6373479e054e9f3943fde23c Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Thu, 11 Mar 2021 18:18:07 +0100 Subject: [PATCH 117/117] imx: bootaux fix elf loading This reverts the arch/arm/mach-imx/imx_bootaux.c changes of commit 805b3cac1e0c. The loader function name was changed so that it does not clash with the generically available function in lib/elf.c. imx-bootaux loads an elf file linked for an auxilary core. Thus the loader function requires address translation from the auxilary core's address space to where those are mapped into U-Boot's address space. So the elf loader is specific and must not be replaced with a generic loader which doesn't provide the address translation functionality. Fixes commit 805b3cac1e0c ("lib: elf: Move the generic elf loading/validating functions to lib") Signed-off-by: Max Krummenacher Acked-by: Oleksandr Suvorov --- arch/arm/mach-imx/imx_bootaux.c | 67 ++++++++++++++++++++++++++++++++- 1 file changed, 66 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index e1fc4b3e19..30fb45d48c 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -14,6 +14,71 @@ #include #include +#ifndef CONFIG_IMX8M +const __weak struct rproc_att hostmap[] = { }; + +static const struct rproc_att *get_host_mapping(unsigned long auxcore) +{ + const struct rproc_att *mmap = hostmap; + + while (mmap && mmap->size) { + if (mmap->da <= auxcore && + mmap->da + mmap->size > auxcore) + return mmap; + mmap++; + } + + return NULL; +} + +/* + * A very simple elf loader for the auxilary core, assumes the image + * is valid, returns the entry point address. + * Translates load addresses in the elf file to the U-Boot address space. + */ +static unsigned long load_elf_image_m_core_phdr(unsigned long addr) +{ + Elf32_Ehdr *ehdr; /* ELF header structure pointer */ + Elf32_Phdr *phdr; /* Program header structure pointer */ + int i; + + ehdr = (Elf32_Ehdr *)addr; + phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff); + + /* Load each program header */ + for (i = 0; i < ehdr->e_phnum; ++i, ++phdr) { + const struct rproc_att *mmap = get_host_mapping(phdr->p_paddr); + void *dst, *src; + + if (phdr->p_type != PT_LOAD) + continue; + + if (!mmap) { + printf("Invalid aux core address: %08x", + phdr->p_paddr); + return 0; + } + + dst = (void *)(phdr->p_paddr - mmap->da) + mmap->sa; + src = (void *)addr + phdr->p_offset; + + debug("Loading phdr %i to 0x%p (%i bytes)\n", + i, dst, phdr->p_filesz); + + if (phdr->p_filesz) + memcpy(dst, src, phdr->p_filesz); + if (phdr->p_filesz != phdr->p_memsz) + memset(dst + phdr->p_filesz, 0x00, + phdr->p_memsz - phdr->p_filesz); + flush_cache((unsigned long)dst & + ~(CONFIG_SYS_CACHELINE_SIZE - 1), + ALIGN(phdr->p_filesz, CONFIG_SYS_CACHELINE_SIZE)); + } + + return ehdr->e_entry; +} +#endif + int arch_auxiliary_core_up(u32 core_id, ulong addr) { ulong stack, pc; @@ -31,7 +96,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) */ if (valid_elf_image(addr)) { stack = 0x0; - pc = load_elf_image_phdr(addr); + pc = load_elf_image_m_core_phdr(addr); if (!pc) return CMD_RET_FAILURE;