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Merge with git+ssh://sr@pollux.denx.org/home/sr/git/u-boot/denx/.git

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This commit is contained in:
Stefan Roese 2007-01-16 15:49:14 +01:00
commit a195ff95ac
29 changed files with 3423 additions and 20 deletions
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103
CHANGELOG
View File

@ -1,3 +1,90 @@
commit 5a5c56986a9ccf71642c8b6374eb18487b15fecd
Author: Stefan Roese <sr@denx.de>
Date: Mon Jan 15 09:46:29 2007 +0100
[PATCH] Fix 440SPe rev B detection from previous patch
Signed-off-by: Stefan Roese <sr@denx.de>
commit a443d31410c571ee8f970da819a44d698fdd6b1f
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Sun Jan 14 13:35:31 2007 +0100
[FIX] correct I2C Writes for the LM81 Sensor.
Signed-off-by: Heiko Schocher <hs@denx.de>
commit 0bba5452835f19a61204edcda3a58112fd8e2208
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Sat Jan 13 11:17:10 2007 +0100
Undo commit 3033ebb2: reset command does not take any arguments
Haiying Wang's modification to the reset command was broken, undo it.
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 95981778cff0038fd9941044d6a3eda810e33258
Author: Stefan Roese <sr@denx.de>
Date: Sat Jan 13 08:01:03 2007 +0100
[PATCH] Update 440SP(e) cpu revisions
Also display enabled/disabled RAID 6 support for 440SP/440SPe PPC's.
Signed-off-by: Stefan Roese <sr@denx.de>
commit 77ddc5b9afb325262fd88752ba430a1dded1f0c7
Author: Stefan Roese <sr@denx.de>
Date: Sat Jan 13 07:59:56 2007 +0100
[PATCH] Update Yellowstone (440GR) to display board rev and PCI bus speed
Now the board revision and the current PCI bus speed are printed after
the board message.
Also the EBC initialising is now done via defines in the board config
file.
Signed-off-by: Stefan Roese <sr@denx.de>
commit 36adff362c2c0141ff8a810d42a7e478f779130f
Author: Stefan Roese <sr@denx.de>
Date: Sat Jan 13 07:59:19 2007 +0100
[PATCH] Update Yosemite (440EP) to display board rev and PCI bus speed
Now the board revision and the current PCI bus speed are printed after
the board message.
Also the EBC initialising is now done via defines in the board config
file.
Signed-off-by: Stefan Roese <sr@denx.de>
commit e0b9ea8c8a294de6a5350ae638879d24b5b709d6
Author: Stefan Roese <sr@denx.de>
Date: Sat Jan 13 07:57:51 2007 +0100
[PATCH] Update Sequoia (440EPx) to display board rev and PCI bus speed
Now the board revision and the current PCI bus speed are printed after
the board message.
Signed-off-by: Stefan Roese <sr@denx.de>
commit 6abaee42621c07e81a2cd189ad4368b5e8c50280
Author: Reinhard Thies <Reinhard.Thies@web.de>
Date: Wed Jan 10 14:41:14 2007 +0100
Adjusted default environment for cam5200 board.
commit bab5a90d4ccc1a46a8127b867fa59028cc623ad9
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Wed Jan 10 15:35:52 2007 +0100
Update CHANGELOG
commit 787fa15860a57833e50bd30555079a9cd4e519b8
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Wed Jan 10 01:28:39 2007 +0100
@ -12,6 +99,14 @@ Date: Wed Jan 10 01:28:39 2007 +0100
Also correct the decoding of the keypad status. With this update, the
key that will trigger the update is Column 2, Row 2.
commit d9384de2f571046e71081bae22b49e3d5ca2e3d5
Author: Marian Balakowicz <m8@semihalf.com>
Date: Wed Jan 10 00:26:15 2007 +0100
CAM5200 flash driver modifications:
- use CFI driver (replaces custom flash driver) for main 'cam5200' target
- add second build target 'cam5200_niosflash' which still uses custom driver
commit 67fea022fa957f59653b5238c7496f80a6b70432
Author: Markus Klotzbuecher <mk@denx.de>
Date: Tue Jan 9 16:02:48 2007 +0100
@ -206,6 +301,14 @@ Date: Thu Dec 21 17:17:02 2006 +0100
Signed-off-by: Heiko Schocher <hs@denx.de>
commit 6dedf3d49dd14c3bf541c8ecee7ffaac5f0e1d6c
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Thu Dec 21 16:14:48 2006 +0100
[PATCH] Add support for the UC101 board from MAN.
Signed-off-by: Heiko Schocher <hs@denx.de>
commit c84bad0ef60e7055ab0bd49b93069509cecc382a
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Wed Dec 20 00:29:43 2006 +0100

5
Makefile
View File

@ -602,6 +602,8 @@ TQM5200_STK100_config: unconfig
{ echo "TEXT_BASE = 0xFFF00000" >$(obj)board/tqm5200/config.tmp ; \
}
@$(MKCONFIG) -n $@ -a TQM5200 ppc mpc5xxx tqm5200
uc101_config: unconfig
@$(MKCONFIG) uc101 ppc mpc5xxx uc101
#########################################################################
## MPC8xx Systems
@ -1198,6 +1200,9 @@ sequoia_nand_config: unconfig
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
solidcard3_config:unconfig
@./mkconfig $(@:_config=) ppc ppc4xx solidcard3
sycamore_config: unconfig
@echo "Configuring for sycamore board as subset of walnut..."
@$(MKCONFIG) -a walnut ppc ppc4xx walnut amcc

3
board/amcc/sequoia/sdram.h
View File

@ -86,7 +86,6 @@
#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_01 0x01
#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
@ -355,8 +354,6 @@
#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_23 0x17
#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)

6
board/mcc200/mcc200.c
View File

@ -92,8 +92,8 @@ static void sdram_start (int hi_addr)
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
* is something else than 0x00000000.
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
* is something else than 0x00000000.
*/
long int initdram (int board_type)
@ -291,7 +291,7 @@ int misc_init_r (void)
}
#ifdef CONFIG_AUTO_UPDATE
do_auto_update();
do_auto_update();
#endif
return (0);
}

47
board/solidcard3/Makefile Normal file
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@ -0,0 +1,47 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o sc3nand.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

24
board/solidcard3/config.mk Normal file
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@ -0,0 +1,24 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0xFFFC0000

382
board/solidcard3/init.S Normal file
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@ -0,0 +1,382 @@
/*------------------------------------------------------------------------------+
*
* This souce code has been made available to you by EuroDesign
* (www.eurodsn.de). It's based on the original IBM source code, so
* this follows:
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
* copyrights to use it in any way he or she deems fit, including
* copying it, modifying it, compiling it, and redistributing it either
* with or without modifications. No license under IBM patents or
* patent applications is to be implied by the copyright license.
*
* Any user of this software should understand that IBM cannot provide
* technical support for this software and will not be responsible for
* any consequences resulting from the use of this software.
*
* Any person who transfers this source code or any derivative work
* must include the IBM copyright notice, this paragraph, and the
* preceding two paragraphs in the transferred software.
*
* COPYRIGHT I B M CORPORATION 1995
* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
*------------------------------------------------------------------------------- */
#include <config.h>
#include <ppc4xx.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
/**
* ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
*
* IMPORTANT: For pass1 this code must run from cache since you can not
* reliably change a peripheral banks timing register (pbxap) while running
* code from that bank. For ex., since we are running from ROM on bank 0, we
* can NOT execute the code that modifies bank 0 timings from ROM, so
* we run it from cache.
*
* Bank 0 - Boot-Flash
* Bank 1 - NAND-Flash
* Bank 2 - ISA bus
* Bank 3 - Second Flash
* Bank 4 - USB controller
*/
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
/*
* We need the current boot up configuration to set correct
* timings into internal flash and external flash
*/
mfdcr r24,strap /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
0 0 -> 8 bit external ROM
0 1 -> 16 bit internal ROM */
addi r4,0,2
srw r24,r24,r4 /* shift right r24 two positions */
andi. r24,r24,0x06000
/*
* All calculations are based on 33MHz EBC clock.
*
* First, create a "very slow" timing (~250ns) with burst mode enabled
* This is need for the external flash access
*/
lis r25,0x0800
ori r25,r25,0x0280 /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280
/*
* Second, create a fast timing:
* 90ns first cycle - 3 clock access
* and 90ns burst cycle, plus 1 clock after the last access
* This is used for the internal access
*/
lis r26,0x8900
ori r26,r26,0x0280 /* 1000 1001 0xxx 0000 0000 0010 100x xxxx
/*
* We can't change settings on CS# if we currently use them.
* -> load a few instructions into cache and run this code from cache
*/
mflr r4 /* save link register */
bl ..getAddr
..getAddr:
mflr r3 /* get address of ..getAddr */
mtlr r4 /* restore link register */
addi r4,0,14 /* set ctr to 10; used to prefetch */
mtctr r4 /* 10 cache lines to fit this function
in cache (gives us 8x10=80 instructions) */
..ebcloop:
icbt r0,r3 /* prefetch cache line for addr in r3 */
addi r3,r3,32 /* move to next cache line */
bdnz ..ebcloop /* continue for 10 cache lines */
/*
* Delay to ensure all accesses to ROM are complete before changing
* bank 0 timings. 200usec should be enough.
* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
*/
lis r3,0x0
ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
mtctr r3
..spinlp:
bdnz ..spinlp /* spin loop */
/*-----------------------------------------------------------------------
* Memory Bank 0 (BOOT-ROM) initialization
* 0xFFEF00000....0xFFFFFFF
* We only have to change the timing. Mapping is ok by boot-strapping
*----------------------------------------------------------------------- */
li r4,pb0ap /* PB0AP=Peripheral Bank 0 Access Parameters */
mtdcr ebccfga,r4
mr r4,r26 /* assume internal fast flash is boot flash */
cmpwi r24,0x2000 /* assumption true? ... */
beq 1f /* ...yes! */
mr r4,r25 /* ...no, use the slow variant */
mr r25,r26 /* use this for the other flash */
1:
mtdcr ebccfgd,r4 /* change timing now */
li r4,pb0cr /* PB0CR=Peripheral Bank 0 Control Register */
mtdcr ebccfga,r4
mfdcr r4,ebccfgd
lis r3,0x0001
ori r3,r3,0x8000 /* allow reads and writes */
or r4,r4,r3
mtdcr ebccfgd,r4
/*-----------------------------------------------------------------------
* Memory Bank 3 (Second-Flash) initialization
* 0xF0000000...0xF01FFFFF -> 2MB
*----------------------------------------------------------------------- */
li r4,pb3ap /* Peripheral Bank 1 Access Parameter */
mtdcr ebccfga,r4
mtdcr ebccfgd,r2 /* change timing */
li r4,pb3cr /* Peripheral Bank 1 Configuration Registers */
mtdcr ebccfga,r4
lis r4,0xF003
ori r4,r4,0x8000
/*
* Consider boot configuration
*/
xori r24,r24,0x2000 /* invert current bus width */
or r4,r4,r24
mtdcr ebccfgd,r4
/*-----------------------------------------------------------------------
* Memory Bank 1 (NAND-Flash) initialization
* 0x77D00000...0x77DFFFFF -> 1MB
* - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
* - the setup time is 0ns
* - the hold time is 15ns
* ->
* - TWT = 0
* - CSN = 0
* - OEN = 0
* - WBN = 0
* - WBF = 0
* - TH = 1
* ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
*----------------------------------------------------------------------- */
li r4,pb1ap /* Peripheral Bank 1 Access Parameter */
mtdcr ebccfga,r4
lis r4,0x0000
ori r4,r4,0x0200
mtdcr ebccfgd,r4
li r4,pb1cr /* Peripheral Bank 1 Configuration Registers */
mtdcr ebccfga,r4
lis r4,0x77D1
ori r4,r4,0x8000
mtdcr ebccfgd,r4
/* USB init (without acceleration) */
#ifndef CONFIG_ISP1161_PRESENT
li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */
mtdcr ebccfga,r4
lis r4,0x0180
ori r4,r4,0x5940
mtdcr ebccfgd,r4
#endif
/*-----------------------------------------------------------------------
* Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
* 0x78000000...0x7BFFFFFF -> 64 MB
* Wir arbeiten bei 33 MHz -> 30ns
*-----------------------------------------------------------------------
A7 (ppc notation) or A24 (standard notation) decides about
the type of access:
A7/A24=0 -> memory cycle
A7/ /A24=1 -> I/O cycle
*/
li r4,pb2ap /* PB2AP=Peripheral Bank 2 Access Parameters */
mtdcr ebccfga,r4
/*
We emulate an ISA access
1. Address active
2. wait 0 EBC clocks -> CSN=0
3. set CS#
4. wait 0 EBC clock -> OEN/WBN=0
5. set OE#/WE#
6. wait 4 clocks (ca. 90ns) and for Ready signal
7. hold for 4 clocks -> TH=4
*/
#if 1
/* faster access to isa-bus */
lis r4,0x0180
ori r4,r4,0x5940
#else
lis r4,0x0100
ori r4,r4,0x0340
#endif
mtdcr ebccfgd,r4
#ifdef IDE_USES_ISA_EMULATION
li r25,pb5ap /* PB5AP=Peripheral Bank 5 Access Parameters */
mtdcr ebccfga,r25
mtdcr ebccfgd,r4
#endif
li r25,pb6ap /* PB6AP=Peripheral Bank 6 Access Parameters */
mtdcr ebccfga,r25
mtdcr ebccfgd,r4
li r25,pb7ap /* PB7AP=Peripheral Bank 7 Access Parameters */
mtdcr ebccfga,r25
mtdcr ebccfgd,r4
li r25,pb2cr /* PB2CR=Peripheral Bank 2 Configuration Register */
mtdcr ebccfga,r25
lis r4,0x780B
ori r4,r4,0xA000
mtdcr ebccfgd,r4
/*
* the other areas are only 1MiB in size
*/
lis r4,0x7401
ori r4,r4,0xA000
li r25,pb6cr /* PB6CR=Peripheral Bank 6 Configuration Register */
mtdcr ebccfga,r25
lis r4,0x7401
ori r4,r4,0xA000
mtdcr ebccfgd,r4
li r25,pb7cr /* PB7CR=Peripheral Bank 7 Configuration Register */
mtdcr ebccfga,r25
lis r4,0x7411
ori r4,r4,0xA000
mtdcr ebccfgd,r4
#ifndef CONFIG_ISP1161_PRESENT
li r25,pb4cr /* PB4CR=Peripheral Bank 4 Configuration Register */
mtdcr ebccfga,r25
lis r4,0x7421
ori r4,r4,0xA000
mtdcr ebccfgd,r4
#endif
#ifdef IDE_USES_ISA_EMULATION
li r25,pb5cr /* PB5CR=Peripheral Bank 5 Configuration Register */
mtdcr ebccfga,r25
lis r4,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
#endif
/*-----------------------------------------------------------------------
* Memory bank 4: USB controller Philips ISP6111
* 0x77C00000 ... 0x77CFFFFF
*
* The chip is connected to:
* - CPU CS#4
* - CPU IRQ#2
* - CPU DMA 3
*
* Timing:
* - command to first data: 300ns. Software must ensure this timing!
* - Write pulse: 26ns
* - Read pulse: 33ns
* - read cycle time: 150ns
* - write cycle time: 140ns
*
* Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
*
* |- 300ns --|
* |---- 420ns ---|---- 420ns ---| cycle
* CS ############:###____#######:###____#######
* OE ############:####___#######:####___#######
* WE ############:####__########:####__########
*
* ----> 2 clocks RD/WR pulses: 60ns
* ----> CSN: 3 clock, 90ns
* ----> OEN: 1 clocks (read cycle)
* ----> WBN: 1 clocks (write cycle)
* ----> WBE: 2 clocks
* ----> TH: 7 clock, 210ns
* ----> TWT: 7 clocks
*----------------------------------------------------------------------- */
#ifdef CONFIG_ISP1161_PRESENT
li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */
mtdcr ebccfga,r4
lis r4,0x030D
ori r4,r4,0x5E80
mtdcr ebccfgd,r4
li r4,pb4cr /* PB2CR=Peripheral Bank 4 Configuration Register */
mtdcr ebccfga,r4
lis r4,0x77C1
ori r4,r4,0xA000
mtdcr ebccfgd,r4
#endif
#ifndef IDE_USES_ISA_EMULATION
/*-----------------------------------------------------------------------
* Memory Bank 5 used for IDE access
*
* Timings for IDE Interface
*
* SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
* 70 165 30 PIO-Mode 0, [ns]
* 3 6 1 [Cycles] ----> AP=0x040C0200
* 50 125 20 PIO-Mode 1, [ns]
* 2 5 1 [Cycles] ----> AP=0x03080200
* 30 100 15 PIO-Mode 2, [ns]
* 1 4 1 [Cycles] ----> AP=0x02040200
* 30 80 10 PIO-Mode 3, [ns]
* 1 3 1 [Cycles] ----> AP=0x01840200
* 25 70 10 PIO-Mode 4, [ns]
* 1 3 1 [Cycles] ----> AP=0x01840200
*
*----------------------------------------------------------------------- */
li r4,pb5ap
mtdcr ebccfga,r4
lis r4,0x040C
ori r4,r4,0x0200
mtdcr ebccfgd,r4
li r4,pb5cr /* PB2CR=Peripheral Bank 2 Configuration Register */
mtdcr ebccfga,r4
lis r4,0x7A01
ori r4,r4,0xA000
mtdcr ebccfgd,r4
#endif
/*
* External Peripheral Control Register
*/
li r4,epcr
mtdcr ebccfga,r4
lis r4,0xB84E
ori r4,r4,0xF000
mtdcr ebccfgd,r4
/*
* drive POST code
*/
lis r4,0x7900
ori r4,r4,0x0080
li r3,0x0001
stb r3,0(r4) /* 01 -> external bus controller is initialized */
nop /* pass2 DCR errata #8 */
blr

94
board/solidcard3/sc3nand.c Normal file
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@ -0,0 +1,94 @@
/*
* (C) Copyright 2007
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <nand.h>
#include <asm/processor.h>
#define readb(addr) *(volatile u_char *)(addr)
#define readl(addr) *(volatile u_long *)(addr)
#define writeb(d,addr) *(volatile u_char *)(addr) = (d)
#define SC3_NAND_ALE 29 /* GPIO PIN 3 */
#define SC3_NAND_CLE 30 /* GPIO PIN 2 */
#define SC3_NAND_CE 27 /* GPIO PIN 5 */
static void *sc3_io_base;
static void *sc3_control_base = (void *)0xEF600700;
static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd)
{
switch (cmd) {
case NAND_CTL_SETCLE:
set_bit (SC3_NAND_CLE, sc3_control_base);
break;
case NAND_CTL_CLRCLE:
clear_bit (SC3_NAND_CLE, sc3_control_base);
break;
case NAND_CTL_SETALE:
set_bit (SC3_NAND_ALE, sc3_control_base);
break;
case NAND_CTL_CLRALE:
clear_bit (SC3_NAND_ALE, sc3_control_base);
break;
case NAND_CTL_SETNCE:
set_bit (SC3_NAND_CE, sc3_control_base);
break;
case NAND_CTL_CLRNCE:
clear_bit (SC3_NAND_CE, sc3_control_base);
break;
}
}
static int sc3_nand_dev_ready(struct mtd_info *mtd)
{
if (!(readl(sc3_control_base + 0x1C) & 0x4000))
return 0;
return 1;
}
static void sc3_select_chip(struct mtd_info *mtd, int chip)
{
clear_bit (SC3_NAND_CE, sc3_control_base);
}
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
sc3_io_base = (void *) CFG_NAND_BASE;
/* Set address of NAND IO lines (Using Linear Data Access Region) */
nand->IO_ADDR_R = (void __iomem *) sc3_io_base;
nand->IO_ADDR_W = (void __iomem *) sc3_io_base;
/* Reference hardware control function */
nand->hwcontrol = sc3_nand_hwcontrol;
nand->dev_ready = sc3_nand_dev_ready;
nand->select_chip = sc3_select_chip;
return 0;
}
#endif

779
board/solidcard3/solidcard3.c Normal file
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@ -0,0 +1,779 @@
/*
* (C) Copyright 2007
* Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
*
* (C) Copyright 2003
* Juergen Beisert, EuroDesign embedded technologies, info@eurodsn.de
* Derived from walnut.c
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* $Log:$
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include "solidcard3.h"
#include <pci.h>
#include <i2c.h>
#include <malloc.h>
#undef writel
#undef writeb
#define writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
/* write only register to configure things in our CPLD */
#define CPLD_CONTROL_1 0x79000102
#define CPLD_VERSION 0x79000103
#define IS_CAMERON ((*(unsigned char *)(CPLD_VERSION)== 0x32) ? 1 : 0)
static struct pci_controller hose={0,};
/************************************************************
* Standard definition
************************************************************/
/* CPC0_CR0 Function ISA bus
- GPIO0
- GPIO1 -> Output: NAND-Command Latch Enable
- GPIO2 -> Output: NAND Address Latch Enable
- GPIO3 -> IRQ input ISA-IRQ #5 (through CPLD)
- GPIO4 -> Output: NAND-Chip Enable
- GPIO5 -> IRQ input ISA-IRQ#7 (through CPLD)
- GPIO6 -> IRQ input ISA-IRQ#9 (through CPLD)
- GPIO7 -> IRQ input ISA-IRQ#10 (through CPLD)
- GPIO8 -> IRQ input ISA-IRQ#11 (through CPLD)
- GPIO9 -> IRQ input ISA-IRQ#12 (through CPLD)
- GPIO10/CS1# -> CS1# NAND ISA-CS#0
- GPIO11/CS2# -> CS2# ISA emulation ISA-CS#1
- GPIO12/CS3# -> CS3# 2nd Flash-Bank ISA-CS#2 or ISA-CS#7
- GPIO13/CS4# -> CS4# USB HC or ISA emulation ISA-CS#3
- GPIO14/CS5# -> CS5# Boosted IDE access ISA-CS#4
- GPIO15/CS6# -> CS6# ISA emulation ISA-CS#5
- GPIO16/CS7# -> CS7# ISA emulation ISA-CS#6
- GPIO17/IRQ0 -> GPIO, in, NAND-Ready/Busy# line ISA-IRQ#3
- GPIO18/IRQ1 -> IRQ input ISA-IRQ#14
- GPIO19/IRQ2 -> IRQ input or USB ISA-IRQ#4
- GPIO20/IRQ3 -> IRQ input PCI-IRQ#D
- GPIO21/IRQ4 -> IRQ input PCI-IRQ#C
- GPIO22/IRQ5 -> IRQ input PCI-IRQ#B
- GPIO23/IRQ6 -> IRQ input PCI-IRQ#A
- GPIO24 -> if GPIO output: 0=JTAG CPLD activ, 1=JTAG CPLD inactiv
*/
/*
| CPLD register: io-space at offset 0x102 (write only)
| 0
| 1
| 2 0=CS#4 USB CS#, 1=ISA or GP bus
| 3
| 4
| 5
| 6 1=enable faster IDE access
| 7
*/
#define USB_CHIP_ENABLE 0x04
#define IDE_BOOSTING 0x40
/* --------------- USB stuff ------------------------------------- */
#ifdef CONFIG_ISP1161_PRESENT
/**
* initUsbHost- Initialize the Philips isp1161 HC part if present
* @cpldConfig: Pointer to value in write only CPLD register
*
* Initialize the USB host controller if present and fills the
* scratch register to inform the driver about used resources
*/
static void initUsbHost (unsigned char *cpldConfig)
{
int i;
unsigned long usbBase;
/*
* Read back where init.S has located the USB chip
*/
mtdcr (0x012, 0x04);
usbBase = mfdcr (0x013);
if (!(usbBase & 0x18000)) /* enabled? */
return;
usbBase &= 0xFFF00000;
/*
* to test for the USB controller enable using of CS#4 and DMA 3 for USB access
*/
writeb (*cpldConfig | USB_CHIP_ENABLE,CPLD_CONTROL_1);
/*
* first check: is the controller assembled?
*/
hcWriteWord (usbBase, 0x5555, HcScratch);
if (hcReadWord (usbBase, HcScratch) == 0x5555) {
hcWriteWord (usbBase, 0xAAAA, HcScratch);
if (hcReadWord (usbBase, HcScratch) == 0xAAAA) {
if ((hcReadWord (usbBase, HcChipID) & 0xFF00) != 0x6100)
return; /* this is not our controller */
/*
* try a software reset. This needs up to 10 seconds (see datasheet)
*/
hcWriteDWord (usbBase, 0x00000001, HcCommandStatus);
for (i = 1000; i > 0; i--) { /* loop up to 10 seconds */
udelay (10);
if (!(hcReadDWord (usbBase, HcCommandStatus) & 0x01))
break;
}
if (!i)
return; /* the controller doesn't responding. Broken? */
/*
* OK. USB controller is ready. Initialize it in such way the later driver
* can us it (without any knowing about specific implementation)
*/
hcWriteDWord (usbBase, 0x00000000, HcControl);
/*
* disable all interrupt sources. Because we
* don't know where we come from (hard reset, cold start, soft reset...)
*/
hcWriteDWord (usbBase, 0x8000007D, HcInterruptDisable);
/*
* our current setup hardware configuration
* - every port power supply can switched indepently
* - every port can signal overcurrent
* - every port is "outside" and the devices are removeable
*/
hcWriteDWord (usbBase, 0x32000902, HcRhDescriptorA);
hcWriteDWord (usbBase, 0x00060000, HcRhDescriptorB);
/*
* don't forget to switch off power supply of each port
* The later running driver can reenable them to find and use
* the (maybe) connected devices.
*
*/
hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus1);
hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus2);
hcWriteWord (usbBase, 0x0428, HcHardwareConfiguration);
hcWriteWord (usbBase, 0x0040, HcDMAConfiguration);
hcWriteWord (usbBase, 0x0000, HcuPInterruptEnable);
hcWriteWord (usbBase, 0xA000 | (0x03 << 8) | 27, HcScratch);
/*
* controller is present and usable
*/
*cpldConfig |= USB_CHIP_ENABLE;
}
}
}
#endif
#if defined(CONFIG_START_IDE)
int board_start_ide(void)
{
if (IS_CAMERON) {
puts ("no IDE on cameron board.\n");
return 0;
}
return 1;
}
#endif
static int sc3_cameron_init (void)
{
/* Set up the Memory Controller for the CAMERON version */
mtebc (pb4ap, 0x01805940);
mtebc (pb4cr, 0x7401a000);
mtebc (pb5ap, 0x01805940);
mtebc (pb5cr, 0x7401a000);
mtebc (pb6ap, 0x0);
mtebc (pb6cr, 0x0);
mtebc (pb7ap, 0x0);
mtebc (pb7cr, 0x0);
return 0;
}
void sc3_read_eeprom (void)
{
uchar i2c_buffer[18];
i2c_read (0x50, 0x03, 1, i2c_buffer, 9);
i2c_buffer[9] = 0;
setenv ("serial#", (char *)i2c_buffer);
/* read mac-address from eeprom */
i2c_read (0x50, 0x11, 1, i2c_buffer, 15);
i2c_buffer[17] = 0;
i2c_buffer[16] = i2c_buffer[14];
i2c_buffer[15] = i2c_buffer[13];
i2c_buffer[14] = ':';
i2c_buffer[13] = i2c_buffer[12];
i2c_buffer[12] = i2c_buffer[11];
i2c_buffer[11] = ':';
i2c_buffer[8] = ':';
i2c_buffer[5] = ':';
i2c_buffer[2] = ':';
setenv ("ethaddr", (char *)i2c_buffer);
}
int board_early_init_f (void)
{
/* write only register to configure things in our CPLD */
unsigned char cpldConfig_1=0x00;
/*-------------------------------------------------------------------------+
| Interrupt controller setup for the SolidCard III CPU card (plus Evaluation board).
|
| Note: IRQ 0 UART 0, active high; level sensitive
| IRQ 1 UART 1, active high; level sensitive
| IRQ 2 IIC, active high; level sensitive
| IRQ 3 Ext. master, rising edge, edge sensitive
| IRQ 4 PCI, active high; level sensitive
| IRQ 5 DMA Channel 0, active high; level sensitive
| IRQ 6 DMA Channel 1, active high; level sensitive
| IRQ 7 DMA Channel 2, active high; level sensitive
| IRQ 8 DMA Channel 3, active high; level sensitive
| IRQ 9 Ethernet Wakeup, active high; level sensitive
| IRQ 10 MAL System Error (SERR), active high; level sensitive
| IRQ 11 MAL Tx End of Buffer, active high; level sensitive
| IRQ 12 MAL Rx End of Buffer, active high; level sensitive
| IRQ 13 MAL Tx Descriptor Error, active high; level sensitive
| IRQ 14 MAL Rx Descriptor Error, active high; level sensitive
| IRQ 15 Ethernet, active high; level sensitive
| IRQ 16 External PCI SERR, active high; level sensitive
| IRQ 17 ECC Correctable Error, active high; level sensitive
| IRQ 18 PCI Power Management, active high; level sensitive
|
| IRQ 19 (EXT IRQ7 405GPr only)
| IRQ 20 (EXT IRQ8 405GPr only)
| IRQ 21 (EXT IRQ9 405GPr only)
| IRQ 22 (EXT IRQ10 405GPr only)
| IRQ 23 (EXT IRQ11 405GPr only)
| IRQ 24 (EXT IRQ12 405GPr only)
|
| IRQ 25 (EXT IRQ 0) NAND-Flash R/B# (raising edge means flash is ready)
| IRQ 26 (EXT IRQ 1) IDE0 interrupt (x86 = IRQ14). Active high (edge sensitive)
| IRQ 27 (EXT IRQ 2) USB controller
| IRQ 28 (EXT IRQ 3) INT D, VGA; active low; level sensitive
| IRQ 29 (EXT IRQ 4) INT C, Ethernet; active low; level sensitive
| IRQ 30 (EXT IRQ 5) INT B, PC104+ SLOT; active low; level sensitive
| IRQ 31 (EXT IRQ 6) INT A, PC104+ SLOT; active low; level sensitive
|
| Direct Memory Access Controller Signal Polarities
| DRQ0 active high (like ISA)
| ACK0 active low (like ISA)
| EOT0 active high (like ISA)
| DRQ1 active high (like ISA)
| ACK1 active low (like ISA)
| EOT1 active high (like ISA)
| DRQ2 active high (like ISA)
| ACK2 active low (like ISA)
| EOT2 active high (like ISA)
| DRQ3 active high (like ISA)
| ACK3 active low (like ISA)
| EOT3 active high (like ISA)
|
+-------------------------------------------------------------------------*/
writeb (cpldConfig_1, CPLD_CONTROL_1); /* disable everything in CPLD */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
if (IS_CAMERON) {
sc3_cameron_init();
mtdcr (0x0B6, 0x18000000);
mtdcr (uicpr, 0xFFFFFFF0);
mtdcr (uictr, 0x10001030);
} else {
mtdcr (0x0B6, 0x0000000);
mtdcr (uicpr, 0xFFFFFFE0);
mtdcr (uictr, 0x10000020);
}
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
/* setup other implementation specific details */
mtdcr (ecr, 0x60606000);
mtdcr (cntrl1, 0x000042C0);
if (IS_CAMERON) {
mtdcr (cntrl0, 0x01380000);
/* Setup the GPIOs */
writel (0x08008000, 0xEF600700); /* Output states */
writel (0x00000000, 0xEF600718); /* Open Drain control */
writel (0x68098000, 0xEF600704); /* Output control */
} else {
mtdcr (cntrl0,0x00080000);
/* Setup the GPIOs */
writel (0x08000000, 0xEF600700); /* Output states */
writel (0x14000000, 0xEF600718); /* Open Drain control */
writel (0x7C000000, 0xEF600704); /* Output control */
}
/* Code decompression disabled */
mtdcr (kiar, kconf);
mtdcr (kidr, 0x2B);
/* CPC0_ER: enable sleep mode of (currently) unused components */
/* CPC0_FR: force unused components into sleep mode */
mtdcr (cpmer, 0x3F800000);
mtdcr (cpmfr, 0x14000000);
/* set PLB priority */
mtdcr (0x87, 0x08000000);
/* --------------- DMA stuff ------------------------------------- */
mtdcr (0x126, 0x49200000);
#ifndef IDE_USES_ISA_EMULATION
cpldConfig_1 |= IDE_BOOSTING; /* enable faster IDE */
/* cpldConfig |= 0x01; */ /* enable 8.33MHz output, if *not* present on your baseboard */
writeb (cpldConfig_1, CPLD_CONTROL_1);
#endif
#ifdef CONFIG_ISP1161_PRESENT
initUsbHost (&cpldConfig_1);
writeb (cpldConfig_1, CPLD_CONTROL_1);
#endif
return(0);
}
int misc_init_r (void)
{
char *s1;
int i, xilinx_val;
volatile char *xilinx_adr;
xilinx_adr = (char *)0x79000102;
*xilinx_adr = 0x00;
/* customer settings ***************************************** */
/*
s1 = getenv ("function");
if (s1) {
if (!strcmp (s1, "Rosho")) {
printf ("function 'Rosho' activated\n");
*xilinx_adr = 0x40;
}
else {
printf (">>>>>>>>>> function %s not recognized\n",s1);
}
}
*/
/* individual settings ***************************************** */
if ((s1 = getenv ("xilinx"))) {
i=0;
xilinx_val = 0;
while (i < 3 && s1[i]) {
if (s1[i] >= '0' && s1[i] <= '9')
xilinx_val = (xilinx_val << 4) + s1[i] - '0';
else
if (s1[i] >= 'A' && s1[i] <= 'F')
xilinx_val = (xilinx_val << 4) + s1[i] - 'A' + 10;
else
if (s1[i] >= 'a' && s1[i] <= 'f')
xilinx_val = (xilinx_val << 4) + s1[i] - 'a' + 10;
else {
xilinx_val = -1;
break;
}
i++;
}
if (xilinx_val >= 0 && xilinx_val <=255 && i < 3) {
printf ("Xilinx: set to %s\n", s1);
*xilinx_adr = (unsigned char) xilinx_val;
} else
printf ("Xilinx: rejected value %s\n", s1);
}
return 0;
}
/* -------------------------------------------------------------------------
* printCSConfig
*
* Print some informations about chips select configurations
* Only used while debugging.
*
* Params:
* - No. of CS pin
* - AP of this CS
* - CR of this CS
*
* Returns
* nothing
------------------------------------------------------------------------- */
#ifdef SC3_DEBUGOUT
static void printCSConfig(int reg,unsigned long ap,unsigned long cr)
{
const char *bsize[4] = {"8","16","32","?"};
const unsigned char banks[8] = {1, 2, 4, 8, 16, 32, 64, 128};
const char *bankaccess[4] = {"disabled", "RO", "WO", "RW"};
#define CYCLE 30 /* time of one clock (based on 33MHz) */
printf("\nCS#%d",reg);
if (!(cr & 0x00018000))
puts(" unused");
else {
if (((cr&0xFFF00000U) & ((banks[(cr & 0x000E0000) >> 17]-1) << 20)))
puts(" Address is not multiple of bank size!");
printf("\n -%s bit device",
bsize[(cr & 0x00006000) >> 13]);
printf(" at 0x%08lX", cr & 0xFFF00000U);
printf(" size: %u MB", banks[(cr & 0x000E0000) >> 17]);
printf(" rights: %s", bankaccess[(cr & 0x00018000) >> 15]);
if (ap & 0x80000000) {
printf("\n -Burst device (%luns/%luns)",
(((ap & 0x7C000000) >> 26) + 1) * CYCLE,
(((ap & 0x03800000) >> 23) + 1) * CYCLE);
} else {
printf("\n -Non burst device, active cycle %luns",
(((ap & 0x7F800000) >> 23) + 1) * CYCLE);
printf("\n -Address setup %luns",
((ap & 0xC0000) >> 18) * CYCLE);
printf("\n -CS active to RD %luns/WR %luns",
((ap & 0x30000) >> 16) * CYCLE,
((ap & 0xC000) >> 14) * CYCLE);
printf("\n -WR to CS inactive %luns",
((ap & 0x3000) >> 12) * CYCLE);
printf("\n -Hold after access %luns",
((ap & 0xE00) >> 9) * CYCLE);
printf("\n -Ready is %sabled",
ap & 0x100 ? "en" : "dis");
}
}
}
#endif
#ifdef SC3_DEBUGOUT
static unsigned int ap[] = {pb0ap, pb1ap, pb2ap, pb3ap, pb4ap,
pb5ap, pb6ap, pb7ap};
static unsigned int cr[] = {pb0cr, pb1cr, pb2cr, pb3cr, pb4cr,
pb5cr, pb6cr, pb7cr};
static int show_reg (int nr)
{
unsigned long ul1, ul2;
mtdcr (ebccfga, ap[nr]);
ul1 = mfdcr (ebccfgd);
mtdcr (ebccfga, cr[nr]);
ul2 = mfdcr(ebccfgd);
printCSConfig(nr, ul1, ul2);
return 0;
}
#endif
int checkboard (void)
{
#ifdef SC3_DEBUGOUT
unsigned long ul1;
int i;
for (i = 0; i < 8; i++) {
show_reg (i);
}
mtdcr (ebccfga, epcr);
ul1 = mfdcr (ebccfgd);
puts ("\nGeneral configuration:\n");
if (ul1 & 0x80000000)
printf(" -External Bus is always driven\n");
if (ul1 & 0x400000)
printf(" -CS signals are always driven\n");
if (ul1 & 0x20000)
printf(" -PowerDown after %lu clocks\n",
(ul1 & 0x1F000) >> 7);
switch (ul1 & 0xC0000)
{
case 0xC0000:
printf(" -No external master present\n");
break;
case 0x00000:
printf(" -8 bit external master present\n");
break;
case 0x40000:
printf(" -16 bit external master present\n");
break;
case 0x80000:
printf(" -32 bit external master present\n");
break;
}
switch (ul1 & 0x300000)
{
case 0x300000:
printf(" -Prefetch: Illegal setting!\n");
break;
case 0x000000:
printf(" -1 doubleword prefetch\n");
break;
case 0x100000:
printf(" -2 doublewords prefetch\n");
break;
case 0x200000:
printf(" -4 doublewords prefetch\n");
break;
}
putc ('\n');
#endif
printf("Board: SolidCard III %s %s version.\n",
(IS_CAMERON ? "Cameron" : "Eurodesign"), CONFIG_SC3_VERSION);
return 0;
}
static int printSDRAMConfig(char reg, unsigned long cr)
{
const int bisize[8]={4, 8, 16, 32, 64, 128, 256, 0};
#ifdef SC3_DEBUGOUT
const char *basize[8]=
{"4", "8", "16", "32", "64", "128", "256", "Reserved"};
printf("SDRAM bank %d",reg);
if (!(cr & 0x01))
puts(" disabled\n");
else {
printf(" at 0x%08lX, size %s MB",cr & 0xFFC00000,basize[(cr&0xE0000)>>17]);
printf(" mode %lu\n",((cr & 0xE000)>>13)+1);
}
#endif
if (cr & 0x01)
return(bisize[(cr & 0xE0000) >> 17]);
return 0;
}
#ifdef SC3_DEBUGOUT
static unsigned int mbcf[] = {mem_mb0cf, mem_mb1cf, mem_mb2cf, mem_mb3cf};
#endif
long int initdram (int board_type)
{
unsigned int mems=0;
unsigned long ul1;
#ifdef SC3_DEBUGOUT
unsigned long ul2;
int i;
puts("\nSDRAM configuration:\n");
mtdcr (memcfga, mem_mcopt1);
ul1 = mfdcr(memcfgd);
if (!(ul1 & 0x80000000)) {
puts(" Controller disabled\n");
return 0;
}
for (i = 0; i < 4; i++) {
mtdcr (memcfga, mbcf[i]);
ul1 = mfdcr (memcfgd);
mems += printSDRAMConfig (i, ul1);
}
mtdcr (memcfga, mem_sdtr1);
ul1 = mfdcr(memcfgd);
printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1);
printf (" -R/W to Precharge %lu (CTP)\n", ((ul1 & 0x30000) >> 16) + 1);
printf (" -Leadoff %lu\n", ((ul1 & 0xC000) >> 14) + 1);
printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
puts ("Misc:\n");
mtdcr (memcfga, mem_rtr);
ul1 = mfdcr(memcfgd);
printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7);
mtdcr(memcfga,mem_pmit);
ul2=mfdcr(memcfgd);
mtdcr(memcfga,mem_mcopt1);
ul1=mfdcr(memcfgd);
if (ul1 & 0x20000000)
printf(" -Power Down after: %luns\n",
((ul2 & 0xFFC00000) >> 22) * 7);
else
puts(" -Power Down disabled\n");
if (ul1 & 0x40000000)
printf(" -Self refresh feature active\n");
else
puts(" -Self refresh disabled\n");
if (ul1 & 0x10000000)
puts(" -ECC enabled\n");
else
puts(" -ECC disabled\n");
if (ul1 & 0x8000000)
puts(" -Using registered SDRAM\n");
if (!(ul1 & 0x6000000))
puts(" -Using 32 bit data width\n");
else
puts(" -Illegal data width!\n");
if (ul1 & 0x400000)
puts(" -ECC drivers inactive\n");
else
puts(" -ECC drivers active\n");
if (ul1 & 0x200000)
puts(" -Memory lines always active outputs\n");
else
puts(" -Memory lines only at write cycles active outputs\n");
mtdcr (memcfga, mem_status);
ul1 = mfdcr (memcfgd);
if (ul1 & 0x80000000)
puts(" -SDRAM Controller ready\n");
else
puts(" -SDRAM Controller not ready\n");
if (ul1 & 0x4000000)
puts(" -SDRAM in self refresh mode!\n");
return (mems * 1024 * 1024);
#else
mtdcr (memcfga, mem_mb0cf);
ul1 = mfdcr (memcfgd);
mems = printSDRAMConfig (0, ul1);
mtdcr (memcfga, mem_mb1cf);
ul1 = mfdcr (memcfgd);
mems += printSDRAMConfig (1, ul1);
mtdcr (memcfga, mem_mb2cf);
ul1 = mfdcr(memcfgd);
mems += printSDRAMConfig (2, ul1);
mtdcr (memcfga, mem_mb3cf);
ul1 = mfdcr(memcfgd);
mems += printSDRAMConfig (3, ul1);
return (mems * 1024 * 1024);
#endif
}
static void pci_solidcard3_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
{
/*-------------------------------------------------------------------------+
| ,-. ,-. ,-. ,-. ,-.
| INTD# ----|B|-----|P|-. ,-|P|-. ,-| |-. ,-|G|
| |R| |C| \ / |C| \ / |E| \ / |r|
| INTC# ----|I|-----|1|-. `/---|1|-. `/---|t|-. `/---|a|
| |D| |0| \/ |0| \/ |h| \/ |f|
| INTB# ----|G|-----|4|-./`----|4|-./`----|e|-./`----|i|
| |E| |+| /\ |+| /\ |r| /\ |k|
| INTA# ----| |-----| |- `----| |- `----| |- `----| |
| `-' `-' `-' `-' `-'
| Slot 0 10 11 12 13
| REQ# 0 1 2 *
| GNT# 0 1 2 *
+-------------------------------------------------------------------------*/
unsigned char int_line = 0xff;
switch (PCI_DEV(dev)) {
case 10:
int_line = 31; /* INT A */
POST_OUT(0x42);
break;
case 11:
int_line = 30; /* INT B */
POST_OUT(0x43);
break;
case 12:
int_line = 29; /* INT C */
POST_OUT(0x44);
break;
case 13:
int_line = 28; /* INT D */
POST_OUT(0x45);
break;
}
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
}
extern void pci_405gp_init(struct pci_controller *hose);
extern void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
extern void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,struct pci_config_table *entry);
/*
* The following table is used when there is a special need to setup a PCI device.
* For every PCI device found in this table is called the given init function with given
* parameters. So never let all IDs at PCI_ANY_ID. In this case any found device gets the same
* parameters!
*
*/
static struct pci_config_table pci_solidcard3_config_table[] =
{
/* Host to PCI Bridge device (405GP) */
{
vendor: 0x1014,
device: 0x0156,
class: PCI_CLASS_BRIDGE_HOST,
bus: 0,
dev: 0,
func: 0,
config_device: pci_405gp_setup_bridge
},
{ }
};
/*-------------------------------------------------------------------------+
| pci_init_board (Called from pci_init() in drivers/pci.c)
|
| Init the PCI part of the SolidCard III
|
| Params:
* - Pointer to current PCI hose
* - Current Device
*
* Returns
* nothing
+-------------------------------------------------------------------------*/
void pci_init_board(void)
{
POST_OUT(0x41);
/*
* we want the ptrs to RAM not flash (ie don't use init list)
*/
hose.fixup_irq = pci_solidcard3_fixup_irq;
hose.config_table = pci_solidcard3_config_table;
pci_405gp_init(&hose);
}

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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/**
* hcWriteWord - write a 16 bit value into the USB controller
* @base: base address to access the chip registers
* @value: 16 bit value to write into register @offset
* @offset: register to write the @value into
*
*/
static void inline hcWriteWord (unsigned long base, unsigned int value,
unsigned int offset)
{
out_le16 ((volatile u16*)(base + 2), offset | 0x80);
out_le16 ((volatile u16*)base, value);
}
/**
* hcWriteDWord - write a 32 bit value into the USB controller
* @base: base address to access the chip registers
* @value: 32 bit value to write into register @offset
* @offset: register to write the @value into
*
*/
static void inline hcWriteDWord (unsigned long base, unsigned long value,
unsigned int offset)
{
out_le16 ((volatile u16*)(base + 2), offset | 0x80);
out_le16 ((volatile u16*)base, value);
out_le16 ((volatile u16*)base, value >> 16);
}
/**
* hcReadWord - read a 16 bit value from the USB controller
* @base: base address to access the chip registers
* @offset: register to read from
*
* Returns the readed register value
*/
static unsigned int inline hcReadWord (unsigned long base, unsigned int offset)
{
out_le16 ((volatile u16*)(base + 2), offset);
return (in_le16 ((volatile u16*)base));
}
/**
* hcReadDWord - read a 32 bit value from the USB controller
* @base: base address to access the chip registers
* @offset: register to read from
*
* Returns the readed register value
*/
static unsigned long inline hcReadDWord (unsigned long base, unsigned int offset)
{
unsigned long val, val16;
out_le16 ((volatile u16*)(base + 2), offset);
val = in_le16((volatile u16*)base);
val16 = in_le16((volatile u16*)base);
return (val | (val16 << 16));
}
/* control and status registers isp1161 */
#define HcRevision 0x00
#define HcControl 0x01
#define HcCommandStatus 0x02
#define HcInterruptStatus 0x03
#define HcInterruptEnable 0x04
#define HcInterruptDisable 0x05
#define HcFmInterval 0x0D
#define HcFmRemaining 0x0E
#define HcFmNumber 0x0F
#define HcLSThreshold 0x11
#define HcRhDescriptorA 0x12
#define HcRhDescriptorB 0x13
#define HcRhStatus 0x14
#define HcRhPortStatus1 0x15
#define HcRhPortStatus2 0x16
#define HcHardwareConfiguration 0x20
#define HcDMAConfiguration 0x21
#define HcTransferCounter 0x22
#define HcuPInterrupt 0x24
#define HcuPInterruptEnable 0x25
#define HcChipID 0x27
#define HcScratch 0x28
#define HcSoftwareReset 0x29
#define HcITLBufferLength 0x2A
#define HcATLBufferLength 0x2B
#define HcBufferStatus 0x2C
#define HcReadBackITL0Length 0x2D
#define HcReadBackITL1Length 0x2E
#define HcITLBufferPort 0x40
#define HcATLBufferPort 0x41

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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/solidcard3/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

50
board/uc101/Makefile Normal file
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@ -0,0 +1,50 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

41
board/uc101/config.mk Normal file
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@ -0,0 +1,41 @@
#
# (C) Copyright 2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# INKA 4X0 board:
#
# Valid values for TEXT_BASE are:
#
# 0xFFE00000 boot high
#
# 0x00100000 boot from RAM (for testing only)
#
ifndef TEXT_BASE
## Standard: boot high
TEXT_BASE = 0xFFF00000
## For testing: boot from RAM
#TEXT_BASE = 0x00100000
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board

136
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@ -0,0 +1,136 @@
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc5xxx/start.o (.text)
cpu/mpc5xxx/traps.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/cache.o (.text)
lib_ppc/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.ppcenv)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

371
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@ -0,0 +1,371 @@
/*
* (C) Copyright 2006
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* (C) Copyright 2004
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <malloc.h>
/* some SIMPLE GPIO Pins */
#define GPIO_USB_8 (31-12)
#define GPIO_USB_7 (31-13)
#define GPIO_USB_6 (31-14)
#define GPIO_USB_0 (31-15)
#define GPIO_PSC3_7 (31-18)
#define GPIO_PSC3_6 (31-19)
#define GPIO_PSC3_1 (31-22)
#define GPIO_PSC3_0 (31-23)
/* some simple Interrupt GPIO Pins */
#define GPIO_PSC3_8 2
#define GPIO_USB1_9 3
#define GPT_OUT_0 0x00000027
#define GPT_OUT_1 0x00000037
#define GPT_DISABLE 0x00000000 /* GPT pin disabled */
#define GP_SIMP_ENABLE_O(n, v) {pgpio->simple_dvo |= (v << n); \
pgpio->simple_ddr |= (1 << n); \
pgpio->simple_gpioe |= (1 << n); \
}
#define GP_SIMP_ENABLE_I(n) { pgpio->simple_ddr |= ~(1 << n); \
pgpio->simple_gpioe |= (1 << n); \
}
#define GP_SIMP_SET_O(n, v) (pgpio->simple_dvo = v ? \
(pgpio->simple_dvo | (1 << n)) : \
(pgpio->simple_dvo & ~(1 << n)) )
#define GP_SIMP_GET_O(n) ((pgpio->simple_dvo >> n) & 1)
#define GP_SIMP_GET_I(n) ((pgpio->simple_ival >> n) & 1)
#define GP_SINT_SET_O(n, v) (pgpio->sint_dvo = v ? \
(pgpio->sint_dvo | (1 << n)) : \
(pgpio->sint_dvo & ~(1 << n)) )
#define GP_SINT_ENABLE_O(n, v) {pgpio->sint_ode &= ~(1 << n); \
pgpio->sint_ddr |= (1 << n); \
GP_SINT_SET_O(n, v); \
pgpio->sint_gpioe |= (1 << n); \
}
#define GP_SINT_ENABLE_I(n) { pgpio->sint_ddr |= ~(1 << n); \
pgpio->sint_gpioe |= (1 << n); \
}
#define GP_SINT_GET_O(n) ((pgpio->sint_ival >> n) & 1)
#define GP_SINT_GET_I(n) ((pgpio-ntt_ival >> n) & 1)
#define GP_TIMER_ENABLE_O(n, v) ( \
((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr = v ? \
GPT_OUT_1 : \
GPT_OUT_0 )
#define GP_TIMER_SET_O(n, v) GP_TIMER_ENABLE_O(n, v)
#define GP_TIMER_GET_O(n, v) ( \
(((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr & 0x10) >> 4)
#define GP_TIMER_GET_I(n, v) ( \
(((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->sr & 0x100) >> 8)
#ifndef CFG_RAMBOOT
static void sdram_start (int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
__asm__ volatile ("sync");
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set mode register: extended mode */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
__asm__ volatile ("sync");
/* set mode register: reset DLL */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
__asm__ volatile ("sync");
#endif
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
/* auto refresh */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
__asm__ volatile ("sync");
/* set mode register */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
__asm__ volatile ("sync");
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
}
#endif
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
* is something else than 0x00000000.
*/
long int initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
ulong test1, test2;
/* setup SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
__asm__ volatile ("sync");
/* setup config registers */
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set tap delay */
*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
__asm__ volatile ("sync");
#endif
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
sdram_start(1);
test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize < (1 << 20)) {
dramsize = 0;
}
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0) {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
__builtin_ffs(dramsize >> 20) - 1;
} else {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
}
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
#else /* CFG_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
if (dramsize >= 0x13) {
dramsize = (1 << (dramsize - 0x13)) << 20;
} else {
dramsize = 0;
}
/* retrieve size of memory connected to SDRAM CS1 */
dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
if (dramsize2 >= 0x13) {
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
} else {
dramsize2 = 0;
}
#endif /* CFG_RAMBOOT */
/* return dramsize + dramsize2; */
return dramsize;
}
int checkboard (void)
{
puts ("Board: MAN UC101\n");
return 0;
}
static void init_ports (void)
{
volatile struct mpc5xxx_gpio *pgpio =
(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
GP_SIMP_ENABLE_I(GPIO_USB_8); /* HEX Bit 3 */
GP_SIMP_ENABLE_I(GPIO_USB_7); /* HEX Bit 2 */
GP_SIMP_ENABLE_I(GPIO_USB_6); /* HEX Bit 1 */
GP_SIMP_ENABLE_I(GPIO_USB_0); /* HEX Bit 0 */
GP_SIMP_ENABLE_I(GPIO_PSC3_0); /* Switch Menue A */
GP_SIMP_ENABLE_I(GPIO_PSC3_1); /* Switch Menue B */
GP_SIMP_ENABLE_I(GPIO_PSC3_6); /* Switch Cold_Warm */
GP_SIMP_ENABLE_I(GPIO_PSC3_7); /* Switch Restart */
GP_SINT_ENABLE_O(GPIO_PSC3_8, 0); /* LED H2 */
GP_SINT_ENABLE_O(GPIO_USB1_9, 0); /* LED H3 */
GP_TIMER_ENABLE_O(4, 0); /* LED H4 */
GP_TIMER_ENABLE_O(5, 0); /* LED H5 */
GP_TIMER_ENABLE_O(3, 0); /* LED HB */
GP_TIMER_ENABLE_O(1, 0); /* RES_COLDSTART */
}
#ifdef CONFIG_PREBOOT
static uchar kbd_magic_prefix[] = "key_magic";
static uchar kbd_command_prefix[] = "key_cmd";
struct kbd_data_t {
char s1;
};
struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
{
volatile struct mpc5xxx_gpio *pgpio =
(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
kbd_data->s1 = GP_SIMP_GET_I(GPIO_USB_8) << 3 | \
GP_SIMP_GET_I(GPIO_USB_7) << 2 | \
GP_SIMP_GET_I(GPIO_USB_6) << 1 | \
GP_SIMP_GET_I(GPIO_USB_0) << 0;
return kbd_data;
}
static int compare_magic (const struct kbd_data_t *kbd_data, uchar *str)
{
char s1 = str[0];
if (s1 >= '0' && s1 <= '9')
s1 -= '0';
else if (s1 >= 'a' && s1 <= 'f')
s1 = s1 - 'a' + 10;
else if (s1 >= 'A' && s1 <= 'F')
s1 = s1 - 'A' + 10;
else
return -1;
if (s1 != kbd_data->s1) return -1;
return 0;
}
static uchar *key_match (const struct kbd_data_t *kbd_data)
{
uchar magic[sizeof (kbd_magic_prefix) + 1];
uchar *suffix;
uchar *kbd_magic_keys;
/*
* The following string defines the characters that can be appended
* to "key_magic" to form the names of environment variables that
* hold "magic" key codes, i. e. such key codes that can cause
* pre-boot actions. If the string is empty (""), then only
* "key_magic" is checked (old behaviour); the string "125" causes
* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
*/
if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
kbd_magic_keys = "";
/* loop over all magic keys;
* use '\0' suffix in case of empty string
*/
for (suffix = kbd_magic_keys; *suffix ||
suffix == kbd_magic_keys; ++suffix) {
sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
if (compare_magic(kbd_data, getenv(magic)) == 0) {
uchar cmd_name[sizeof (kbd_command_prefix) + 1];
char *cmd;
sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
cmd = getenv (cmd_name);
return (cmd);
}
}
return (NULL);
}
#endif /* CONFIG_PREBOOT */
int misc_init_r (void)
{
/* Init the I/O ports */
init_ports ();
#ifdef CONFIG_PREBOOT
struct kbd_data_t kbd_data;
/* Decode keys */
uchar *str = strdup (key_match (get_keys (&kbd_data)));
/* Set or delete definition */
setenv ("preboot", str);
free (str);
#endif /* CONFIG_PREBOOT */
return 0;
}
int board_early_init_r (void)
{
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
*(vu_long *)MPC5XXX_BOOTCS_START =
*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
*(vu_long *)MPC5XXX_BOOTCS_STOP =
*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
/* Interbus enable it here ?? */
*(vu_long *)MPC5XXX_GPT6_ENABLE = GPT_OUT_1;
return 0;
}
#ifdef CONFIG_PCI
static struct pci_controller hose;
extern void pci_mpc5xxx_init(struct pci_controller *);
void pci_init_board(void)
{
pci_mpc5xxx_init(&hose);
}
#endif
#if defined(CONFIG_HW_WATCHDOG)
void hw_watchdog_reset(void)
{
/* Trigger HW Watchdog with TIMER_0 */
*(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_1;
*(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_0;
}
#endif

2
cpu/mpc5xxx/cpu_init.c
View File

@ -123,7 +123,7 @@ void cpu_init_f (void)
#endif
#if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE)
*(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS5_START);
*(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS7_START);
*(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE);
addecr |= (1 << 27);
#endif

7
cpu/mpc5xxx/fec.c
View File

@ -376,7 +376,7 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
#if (DEBUG & 0x2)
if (fec->xcv_type != SEVENWIRE)
mpc5xxx_fec_phydump ();
mpc5xxx_fec_phydump (dev->name);
#endif
/*
@ -575,7 +575,7 @@ static void mpc5xxx_fec_halt(struct eth_device *dev)
#if (DEBUG & 0x2)
if (fec->xcv_type != SEVENWIRE)
mpc5xxx_fec_phydump ();
mpc5xxx_fec_phydump (dev->name);
#endif
/*
@ -882,7 +882,8 @@ int mpc5xxx_fec_initialize(bd_t * bis)
defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
defined(CONFIG_MCC200) || defined(CONFIG_O2DNT) || \
defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \
defined(CONFIG_TQM5200) || defined(CONFIG_V38B)
defined(CONFIG_TQM5200) || defined(CONFIG_V38B) || \
defined(CONFIG_UC101)
# ifndef CONFIG_FEC_10MBIT
fec->xcv_type = MII100;
# else

6
cpu/mpc8xx/serial.c
View File

@ -229,15 +229,15 @@ static int smc_init (void)
#ifdef CFG_SPC1920_SMC1_CLK4
/* clock source is PLD */
/* set freq to 19200 Baud */
*((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0x3;
/* configure clk4 as input */
im->im_ioport.iop_pdpar |= 0x800;
im->im_ioport.iop_pddir &= ~0x800;
cp->cp_simode = 0x0000;
cp->cp_simode |= 0x7000;
cp->cp_simode |= 0x7000;
#else
/* Set up the baud rate generator */
smc_setbrg ();

4
cpu/ppc4xx/405gp_pci.c
View File

@ -380,7 +380,7 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
}
#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405))
#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) || defined (CONFIG_SOLIDCARD3)
/*
*As is these functs get called out of flash Not a horrible
@ -406,6 +406,7 @@ static struct pci_controller hose = {
config_table: pci_405gp_config_table,
};
#ifndef CONFIG_SOLIDCARD3
void pci_init_board(void)
{
/*we want the ptrs to RAM not flash (ie don't use init list)*/
@ -413,6 +414,7 @@ void pci_init_board(void)
hose.config_table = pci_405gp_config_table;
pci_405gp_init(&hose);
}
#endif
#endif

2
cpu/ppc4xx/cpu.c
View File

@ -439,7 +439,7 @@ int ppc440spe_revB() {
unsigned int pvr;
pvr = get_pvr();
if (pvr == PVR_440SPe_RB)
if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
return 1;
else
return 0;

11
cpu/ppc4xx/cpu_init.c
View File

@ -219,6 +219,10 @@ void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_M
void
cpu_init_f (void)
{
#if defined(CONFIG_WATCHDOG)
unsigned long val;
#endif
#if defined(CONFIG_405EP)
/*
* GPIO0 setup (select GPIO or alternate function)
@ -309,9 +313,12 @@ cpu_init_f (void)
mtebc(pb7cr, CFG_EBC_PB7CR);
#endif
#if defined(CONFIG_WATCHDOG)
unsigned long val;
#if defined (CONFIG_SOLIDCARD3)
mtebc(epcr, 0xb84ef000);
*(unsigned long *)0x79000080 = 0x0001;
#endif
#if defined(CONFIG_WATCHDOG)
val = mfspr(tcr);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
val |= 0xb8000000; /* generate system reset after 1.34 seconds */

12
drivers/cfi_flash.c
View File

@ -40,6 +40,10 @@
#include <environment.h>
#ifdef CFG_FLASH_CFI_DRIVER
#if defined(CONFIG_SOLIDCARD3)
#define __LITTLE_ENDIAN
#endif
/*
* This file implements a Common Flash Interface (CFI) driver for U-Boot.
* The width of the port and the width of the chips are determined at initialization.
@ -867,7 +871,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
cword->c = c;
break;
case FLASH_CFI_16BIT:
#if defined(__LITTLE_ENDIAN)
#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SOLIDCARD3)
w = c;
w <<= 8;
cword->w = (cword->w >> 8) | w;
@ -1359,7 +1363,6 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest,
ctladdr.cp = flash_make_addr (info, 0, 0);
cptr.cp = (uchar *) dest;
/* Check if Flash is (sufficiently) erased */
switch (info->portwidth) {
case FLASH_CFI_8BIT:
@ -1531,4 +1534,9 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
}
}
#endif /* CFG_FLASH_USE_BUFFER_WRITE */
#if defined(CONFIG_SOLIDCARD3)
#undef __LITTLE_ENDIAN
#endif
#endif /* CFG_FLASH_CFI */

2
dtt/Makefile
View File

@ -30,7 +30,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libdtt.a
COBJS = lm75.o ds1621.o adm1021.o
COBJS = lm75.o ds1621.o adm1021.o lm81.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

148
dtt/lm81.c Normal file
View File

@ -0,0 +1,148 @@
/*
* (C) Copyright 2006
* Heiko Schocher, DENX Software Enginnering <hs@denx.de>
*
* based on dtt/lm75.c which is ...
*
* (C) Copyright 2001
* Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* On Semiconductor's LM81 Temperature Sensor
*/
#include <common.h>
#ifdef CONFIG_DTT_LM81
#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \
(CFG_EEPROM_PAGE_WRITE_BITS < 1)
# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_LM81"
#endif
#include <i2c.h>
#include <dtt.h>
/*
* Device code
*/
#define DTT_I2C_DEV_CODE 0x2c /* ON Semi's LM81 device */
int dtt_read(int sensor, int reg)
{
int dlen = 1;
uchar data[2];
/*
* Calculate sensor address and register.
*/
sensor = DTT_I2C_DEV_CODE + (sensor & 0x03); /* calculate address of lm81 */
/*
* Now try to read the register.
*/
if (i2c_read(sensor, reg, 1, data, dlen) != 0)
return -1;
return (int)data[0];
} /* dtt_read() */
int dtt_write(int sensor, int reg, int val)
{
uchar data;
/*
* Calculate sensor address and register.
*/
sensor = DTT_I2C_DEV_CODE + (sensor & 0x03); /* calculate address of lm81 */
data = (char)(val & 0xff);
/*
* Write value to register.
*/
if (i2c_write(sensor, reg, 1, &data, 1) != 0)
return 1;
return 0;
} /* dtt_write() */
#define DTT_MANU 0x3e
#define DTT_REV 0x3f
#define DTT_CONFIG 0x40
#define DTT_ADR 0x48
static int _dtt_init(int sensor)
{
int man;
int adr;
int rev;
if (dtt_write (sensor, DTT_CONFIG, 0x01) < 0)
return 1;
/* The LM81 needs 400ms to get the correct values ... */
udelay (400000);
man = dtt_read (sensor, DTT_MANU);
if (man != 0x01)
return 1;
adr = dtt_read (sensor, DTT_ADR);
if (adr < 0)
return 1;
rev = dtt_read (sensor, DTT_REV);
if (adr < 0)
return 1;
printf ("DTT: Found LM81@%x Rev: %d\n", adr, rev);
return 0;
} /* _dtt_init() */
int dtt_init (void)
{
int i;
unsigned char sensors[] = CONFIG_DTT_SENSORS;
const char *const header = "DTT: ";
for (i = 0; i < sizeof(sensors); i++) {
if (_dtt_init(sensors[i]) != 0)
printf("%s%d FAILED INIT\n", header, i+1);
else
printf("%s%d is %i C\n", header, i+1,
dtt_get_temp(sensors[i]));
}
return (0);
} /* dtt_init() */
#define TEMP_FROM_REG(temp) \
((temp)<256?((((temp)&0x1fe) >> 1) * 10) + ((temp) & 1) * 5: \
((((temp)&0x1fe) >> 1) -255) * 10 - ((temp) & 1) * 5) \
int dtt_get_temp(int sensor)
{
int val = dtt_read (sensor, DTT_READ_TEMP);
int tmpcnf = dtt_read (sensor, DTT_CONFIG_TEMP);
return (TEMP_FROM_REG((val << 1) + ((tmpcnf & 0x80) >> 7))) / 10;
} /* dtt_get_temp() */
#endif /* CONFIG_DTT_LM81 */

562
include/configs/solidcard3.h Normal file
View File

@ -0,0 +1,562 @@
/*
* (C) Copyright 2007
* Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
*
* From:
* (C) Copyright 2003
* Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#undef USE_VGA_GRAPHICS
/* Memory Map
0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB)
0x74000000 .... 0x740FFFFF -> CS#6
0x74100000 .... 0x741FFFFF -> CS#7
0x74200000 .... 0x742FFFFF -> CS4# if no internal USB
0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE
0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB)
0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB)
0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB)
0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB)
0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored)
0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB)
0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1)
0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF)
0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF)
0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF)
0xEED00000 .... 0xEED00003 -> PCI-Bus
0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers
0xEF40003F .... 0xEF5FFFFF -> reserved
0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB)
0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB)
0xF0200000 .... 0xF7FFFFFF -> free for flash devices
0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB)
0xF8001000 .... 0xFFDFFFFF -> free for flash devices
0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB)
*/
#define CONFIG_SOLIDCARD3 1
#define CONFIG_4xx 1
#define CONFIG_405GP 1
#define CONFIG_BOARD_EARLY_INIT_F 1
/*
* define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range
* If undefed, IDE access uses a seperat emulation with higher access speed
* Consider to inform your Linux IDE driver about the different addresses!
* IDE_USES_ISA_EMULATION is only used if your CONFIG_COMMANDS macro includes the CFG_CMD_IDE macro!
*/
#define IDE_USES_ISA_EMULATION
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_SERIAL_MULTI
#undef CONFIG_SERIAL_SOFTWARE_FIFO
/*
* define CONFIG_POWER_DOWN if your cpu should power down while waiting for your input
* Works only, if you have enabled the CONFIG_SERIAL_SOFTWARE_FIFO feature
*/
#if CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_POWER_DOWN
#endif
/*
* define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz
*/
#define CONFIG_SYS_CLK_FREQ 33333333
/*
* define CONFIG_BAUDRATE to the baudrate value you want to use as default
*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"nand_args=setenv bootargs root=/dev/mtdblock4 rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
"bootm ${kernel_addr}\0" \
"flash_nand=nand_args addip addcon;bootm ${kernel_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/sc3/uImage\0" \
"kernel_addr=FFE08000\0" \
""
#undef CONFIG_BOOTCOMMAND
#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
#if 1 /* feel free to disable for development */
#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
#define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with S\n"
#define CONFIG_AUTOBOOT_DELAY_STR "S" /* 1st "password" */
#endif
/*
* define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after
* the CONFIG_BOOTDELAY delay to boot your machine
*/
#define CONFIG_BOOTCOMMAND "bootp;dcache on;bootm"
/*
* define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't
* set different values at the u-boot prompt
*/
#ifdef USE_VGA_GRAPHICS
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re"
#else
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs rw ip=bootp"
#endif
/*
* Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT
* This reserves memory bank #4 for this purpose
*/
#undef CONFIG_ISP1161_PRESENT
#undef CONFIG_LOADS_ECHO /* no echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_NET_MULTI
/* #define CONFIG_EEPRO100_SROM_WRITE */
/* #define CONFIG_SHOW_MAC */
#define CONFIG_EEPRO100
#define CONFIG_MII 1 /* add 405GP MII PHY management */
#define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */
#define CONFIG_COMMANDS \
(CONFIG_CMD_DFL | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_NET | \
CFG_CMD_MII | \
CFG_CMD_PING | \
CFG_CMD_NAND | \
CFG_CMD_I2C | \
CFG_CMD_IDE | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_CACHE | \
CFG_CMD_ELF )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP 1 /* undef to save memory */
#define CFG_PROMPT "SC3> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
/*
* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
* If CFG_405_UART_ERRATA_59, then UART divisor is 31.
* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
* The Linux BASE_BAUD define should match this configuration.
* baseBaud = cpuClock/(uartDivisor*16)
* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*
* Consider the OPB clock! If it get lower the BASE_BAUD must be lower to
* (see 405GP datasheet for descritpion)
*/
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD 921600 /* internal clock */
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
#define CFG_LOAD_ADDR 0x1000000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* IIC stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define I2C_INIT
#define I2C_ACTIVE 0
#define I2C_TRISTATE 0
#define CFG_I2C_SPEED 100000 /* use the standard 100kHz speed */
#define CFG_I2C_SLAVE 0x7F /* mask valid bits */
#define CONFIG_RTC_DS1337
#define CFG_I2C_RTC_ADDR 0x68
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
/* If you want to see, whats connected to your PCI bus */
/* #define CONFIG_PCI_SCAN_SHOW */
#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
/*-----------------------------------------------------------------------
* External peripheral base address
*-----------------------------------------------------------------------
*/
#if !(CONFIG_COMMANDS & CFG_CMD_IDE)
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
/*-----------------------------------------------------------------------
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
#else /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */
#define CONFIG_START_IDE 1 /* check, if use IDE */
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
#define CONFIG_ATAPI
#define CONFIG_DOS_PARTITION
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
#ifndef IDE_USES_ISA_EMULATION
/* New and faster access */
#define CFG_ATA_BASE_ADDR 0x7A000000 /* start of ISA IO emulation */
/* How many IDE busses are available */
#define CFG_IDE_MAXBUS 1
/* What IDE ports are available */
#define CFG_ATA_IDE0_OFFSET 0x000 /* first is available */
#undef CFG_ATA_IDE1_OFFSET /* second not available */
/* access to the data port is calculated:
CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
/* access to the registers is calculated:
CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
/* access to the alternate register is calculated:
CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
#define CFG_ATA_ALT_OFFSET 0x008 /* Offset for alternate registers */
#else /* IDE_USES_ISA_EMULATION */
#define CFG_ATA_BASE_ADDR 0x79000000 /* start of ISA IO emulation */
/* How many IDE busses are available */
#define CFG_IDE_MAXBUS 1
/* What IDE ports are available */
#define CFG_ATA_IDE0_OFFSET 0x01F0 /* first is available */
#undef CFG_ATA_IDE1_OFFSET /* second not available */
/* access to the data port is calculated:
CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
/* access to the registers is calculated:
CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
/* access to the alternate register is calculated:
CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
#define CFG_ATA_ALT_OFFSET 0x03F0 /* Offset for alternate registers */
#endif /* IDE_USES_ISA_EMULATION */
#endif /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */
/*
#define CFG_KEY_REG_BASE_ADDR 0xF0100000
#define CFG_IR_REG_BASE_ADDR 0xF0200000
#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
*/
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*
* CFG_FLASH_BASE -> start address of internal flash
* CFG_MONITOR_BASE -> start of u-boot
*/
#ifndef __ASSEMBLER__
extern unsigned long offsetOfBigFlash;
extern unsigned long offsetOfEnvironment;
#endif
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFFE00000
#define CFG_MONITOR_BASE 0xFFFC0000 /* placed last 256k */
#define CFG_MONITOR_LEN (224 * 1024) /* Reserve 224 KiB for Monitor */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KiB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MiB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization ## FIXME: lookup in datasheet
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_FLASH_CFI /* flash is CFI compat. */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_ENV_IS_IN_FLASH 1
#if CFG_ENV_IS_IN_FLASH
#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector in bottom type */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x4000 /* see README - env sector total size */
#endif
/* let us changing anything in our environment */
#define CONFIG_ENV_OVERWRITE
/*
* NAND-FLASH stuff
*/
#define CFG_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE 0x77D00000
/*-----------------------------------------------------------------------
* Cache Configuration
*
* CFG_DCACHE_SIZE -> size of data cache:
* - 405GP 8k
* - 405GPr 16k
* How to handle the difference in chache size?
* CFG_CACHELINE_SIZE -> size of one cache line: 32 bytes
* (used in cpu/ppc4xx/start.S)
*/
#define CFG_DCACHE_SIZE 16384
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*
*/
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE
#define FLASH_BASE1_PRELIM 0
/*-----------------------------------------------------------------------
* Some informations about the internal SRAM (OCM=On Chip Memory)
*
* CFG_OCM_DATA_ADDR -> location
* CFG_OCM_DATA_SIZE -> size
*/
#define CFG_TEMP_STACK_OCM 1
#define CFG_OCM_DATA_ADDR 0xF8000000
#define CFG_OCM_DATA_SIZE 0x1000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM):
* - we are using the internal 4k SRAM, so we don't need data cache mapping
* - internal SRAM (OCM=On Chip Memory) is placed to CFG_OCM_DATA_ADDR
* - Stackpointer will be located to
* (CFG_INIT_RAM_ADDR&0xFFFF0000) | (CFG_INIT_SP_OFFSET&0x0000FFFF)
* in cpu/ppc4xx/start.S
*/
#undef CFG_INIT_DCACHE_CS
/* Where the internal SRAM starts */
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR
/* Where the internal SRAM ends (only offset) */
#define CFG_INIT_RAM_END 0x0F00
/*
CFG_INIT_RAM_ADDR ------> ------------ lower address
| |
| ^ |
| | |
| | Stack |
CFG_GBL_DATA_OFFSET ----> ------------
| |
| 64 Bytes |
| |
CFG_INIT_RAM_END ------> ------------ higher address
(offset only)
*/
/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_SIZE 64
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/* Initial value of the stack pointern in internal SRAM */
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/* ################################################################################### */
/* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects */
/* They are currently undefined cause they are initiaized in board/solidcard3/init.S */
/* This chip select accesses the boot device */
/* It depends on boot select switch if this device is 16 or 8 bit */
#undef CFG_EBC_PB0AP
#undef CFG_EBC_PB0CR
#undef CFG_EBC_PB1AP
#undef CFG_EBC_PB1CR
#undef CFG_EBC_PB2AP
#undef CFG_EBC_PB2CR
#undef CFG_EBC_PB3AP
#undef CFG_EBC_PB3CR
#undef CFG_EBC_PB4AP
#undef CFG_EBC_PB4CR
#undef CFG_EBC_PB5AP
#undef CFG_EBC_PB5CR
#undef CFG_EBC_PB6AP
#undef CFG_EBC_PB6CR
#undef CFG_EBC_PB7AP
#undef CFG_EBC_PB7CR
#define CONFIG_SDRAM_BANK0 /* use the standard SDRAM initialization */
#undef CONFIG_SPD_EEPROM
/*
* Define this to get more information about system configuration
*/
/* #define SC3_DEBUGOUT */
#undef SC3_DEBUGOUT
/***********************************************************************
* External peripheral base address
***********************************************************************/
#define CFG_ISA_MEM_BASE_ADDRESS 0x78000000
/*
Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu.
Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die
das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen
auf ISA- und PCI-Zyklen)
*/
#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
/*#define CFG_ISA_IO_BASE_ADDRESS 0x79000000 */
/************************************************************
* Video support
************************************************************/
#ifdef USE_VGA_GRAPHICS
#define CONFIG_VIDEO /* To enable video controller support */
#define CONFIG_VIDEO_CT69000
#define CONFIG_CFB_CONSOLE
/* #define CONFIG_VIDEO_LOGO */
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_SW_CURSOR
/* #define CONFIG_VIDEO_HW_CURSOR */
#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
#define VIDEO_HW_RECTFILL
#define VIDEO_HW_BITBLT
#endif
/************************************************************
* Ident
************************************************************/
#define CONFIG_SC3_VERSION "r1.4"
#define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x)
#endif /* __CONFIG_H */

353
include/configs/uc101.h Normal file
View File

@ -0,0 +1,353 @@
/*
* (C) Copyright 2003-2006
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_UC101 1 /* UC101 board */
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
#define CONFIG_BOARD_EARLY_INIT_R
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/* Partitions */
#define CONFIG_DOS_PARTITION
/*
* Supported commands
*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_DATE | \
CFG_CMD_DISPLAY | \
CFG_CMD_DHCP | \
CFG_CMD_PING | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_DTT | \
CFG_CMD_IDE | \
CFG_CMD_FAT | \
CFG_CMD_NFS | \
CFG_CMD_MII | \
CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
#if (TEXT_BASE == 0xFFF00000) /* Boot low */
# define CFG_LOWBOOT 1
#endif
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addwdt=setenv bootargs ${bootargs} wdt=off" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
"bootm ${kernel_addr}\0" \
"net_nfs=tftp 300000 ${bootfile};run nfsargs addip addwdt;bootm\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
#define CONFIG_MISC_INIT_R 1
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
#define CFG_I2C_SPEED 100000 /* 100 kHz */
#define CFG_I2C_SLAVE 0x7F
/*
* EEPROM configuration
*/
#define CFG_I2C_EEPROM_ADDR 0x58
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_BITS 4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
/* for LM81 */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*
* RTC configuration
*/
#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR 0x51
/* I2C SYSMON (LM75) */
#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
#define CFG_DTT_MAX_TEMP 70
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
/*
* Flash configuration
*/
#define CFG_FLASH_BASE 0xFF800000
#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
#define CFG_MAX_FLASH_SECT 140 /* max num of sects on one chip */
#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_CFI_AMD_RESET
/*
* Environment settings
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x4000
#define CFG_ENV_SECT_SIZE 0x10000
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
/*
* Memory map
*/
#define CFG_MBAR 0xF0000000
#define CFG_DEFAULT_MBAR 0x80000000
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SRAM_BASE 0x80100000 /* CS 1 */
#define CFG_DISPLAY_BASE 0x80600000 /* CS 3 */
#define CFG_IB_MASTER 0xc0510000 /* CS 6 */
#define CFG_IB_EPLD 0xc0500000 /* CS 7 */
/* Settings for XLB = 132 MHz */
#define SDRAM_DDR 1
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x714f0f00
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
/* SRAM */
#define SRAM_BASE CFG_SRAM_BASE /* SRAM base address */
#define SRAM_LEN 0x1fffff
#define SRAM_END (SRAM_BASE + SRAM_LEN)
/* Use ON-Chip SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
#else
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
#endif
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT 1
#endif
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
#define CONFIG_PHY_ADDR 0x00
#define CONFIG_MII 1
/*
* GPIO configuration
*/
#define CFG_GPS_PORT_CONFIG 0x4d558044
/*use Hardware WDT */
#define CONFIG_HW_WATCHDOG
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST
#define CFG_MEMTEST_START 0x00300000 /* memtest works on */
#define CFG_MEMTEST_END 0x00f00000 /* 3 ... 15 MB in DRAM */
#define CFG_LOAD_ADDR 0x300000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
* which is normally part of the default commands (CFV_CMD_DFL)
*/
#define CONFIG_LOOPW
/*
* Various low-level settings
*/
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL HID0_ICE
#else
#define CFG_HID0_INIT 0
#define CFG_HID0_FINAL 0
#endif
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG 0x00045D00
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
/* 8Mbit SRAM @0x80100000 */
#define CFG_CS1_START CFG_SRAM_BASE
#define CFG_CS1_SIZE 0x00100000
#define CFG_CS1_CFG 0x21D00
/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
#define CFG_CS3_START CFG_DISPLAY_BASE
#define CFG_CS3_SIZE 0x00000100
#define CFG_CS3_CFG 0x00081802
/* Interbus Master 16 Bit */
#define CFG_CS6_START CFG_IB_MASTER
#define CFG_CS6_SIZE 0x00010000
#define CFG_CS6_CFG 0x00FF3500
/* Interbus EPLD 8 Bit */
#define CFG_CS7_START CFG_IB_EPLD
#define CFG_CS7_SIZE 0x00010000
#define CFG_CS7_CFG 0x00081800
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333333
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
#define CONFIG_IDE_PREINIT 1
/* #define CONFIG_IDE_RESET 1 beispile siehe tqm5200.c */
#define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET (0x005C)
/* Interval between registers */
#define CFG_ATA_STRIDE 4
#define CONFIG_ATAPI 1
/*---------------------------------------------------------------------*/
/* Display addresses */
/*---------------------------------------------------------------------*/
#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38)
#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30)
#endif /* __CONFIG_H */

9
include/dtt.h
View File

@ -29,6 +29,7 @@
#if defined(CONFIG_DTT_LM75) || \
defined(CONFIG_DTT_DS1621) || \
defined(CONFIG_DTT_LM81) || \
defined(CONFIG_DTT_ADM1021)
#define CONFIG_DTT /* We have a DTT */
@ -58,6 +59,14 @@ extern int dtt_get_temp(int sensor);
#define DTT_TEMP_SET 0x3
#endif
#if defined(CONFIG_DTT_LM81)
#define DTT_READ_TEMP 0x27
#define DTT_CONFIG_TEMP 0x4b
#define DTT_TEMP_MAX 0x39
#define DTT_TEMP_HYST 0x3a
#define DTT_CONFIG 0x40
#endif
#if defined(CONFIG_DTT_DS1621)
#define DTT_READ_TEMP 0xAA
#define DTT_READ_COUNTER 0xA8

1
include/ppc405.h
View File

@ -160,6 +160,7 @@
#define mem_bear 0x10 /* bus error address reg */
#endif
#define mem_mcopt1 0x20 /* memory controller options 1 */
#define mem_status 0x24 /* memory status */
#define mem_rtr 0x30 /* refresh timer reg */
#define mem_pmit 0x34 /* power management idle timer */
#define mem_mb0cf 0x40 /* memory bank 0 configuration */

16
lib_ppc/board.c
View File

@ -76,6 +76,10 @@
extern int update_flash_size (int flash_size);
#endif
#if defined(CONFIG_SOLIDCARD3)
extern void sc3_read_eeprom(void);
#endif
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
void doc_init (void);
#endif
@ -93,6 +97,9 @@ static char *failed = "*** failed ***\n";
extern flash_info_t flash_info[];
#endif
#if defined(CONFIG_START_IDE)
extern int board_start_ide(void);
#endif
#include <environment.h>
DECLARE_GLOBAL_DATA_PTR;
@ -815,6 +822,9 @@ void board_init_r (gd_t *id, ulong dest_addr)
#endif /* CONFIG_405GP, CONFIG_405EP */
#endif /* CFG_EXTBDINFO */
#if defined(CONFIG_SOLIDCARD3)
sc3_read_eeprom();
#endif
s = getenv ("ethaddr");
#if defined (CONFIG_MBX) || \
defined (CONFIG_RPXCLASSIC) || \
@ -921,6 +931,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
defined(CONFIG_KUP4X) || \
defined(CONFIG_LWMON) || \
defined(CONFIG_PCU_E) || \
defined(CONFIG_SOLIDCARD3) || \
defined(CONFIG_W7O) || \
defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
@ -1030,7 +1041,12 @@ void board_init_r (gd_t *id, ulong dest_addr)
# else
puts ("IDE: ");
#endif
#if defined(CONFIG_START_IDE)
if (board_start_ide())
ide_init ();
#else
ide_init ();
#endif
#endif /* CFG_CMD_IDE */
#ifdef CONFIG_LAST_STAGE_INIT