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Merge git://git.denx.de/u-boot-fsl-qoriq

Browse Source 
Layerscape: Enable gpio
Bug fixes & updates related to dspi, qspi, pciep, SVR mask,
stream-id, env variables, mdio for LAyerscape Platforms
Add SATA, network variant 1, 2 support on sl28
powerpc: T1042: drop CONFIG_VIDEO, Add kmcent2 board supporrt, keymile
Bug fixes and updates for keymile, Kontron
This commit is contained in:
Tom Rini 2021-02-08 10:55:28 -05:00
commit a10d06add7
183 changed files with 3894 additions and 192 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/cpu/armv7/ls102xa/cpu.c
View File

@ -316,6 +316,8 @@ int arch_cpu_init(void)
struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
u32 state;
icache_enable();
/*
* The RCPM FSM state may not be reset after power-on.
* So, reset them.

2
arch/arm/dts/Makefile
View File

@ -438,6 +438,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1012a-frdm.dtb \
fsl-ls1012a-frwy.dtb
dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
fsl-ls1028a-kontron-sl28-var1.dtb \
fsl-ls1028a-kontron-sl28-var2.dtb \
fsl-ls1028a-kontron-sl28-var3.dtb \
fsl-ls1028a-kontron-sl28-var4.dtb \

20
arch/arm/dts/fsl-ls1012a.dtsi
View File

@ -71,6 +71,26 @@
bus-width = <4>;
};
gpio0: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <0 66 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@2310000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <0 67 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;

62
arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
View File

@ -10,8 +10,6 @@
i2c1 = &i2c3;
i2c2 = &i2c4;
rtc0 = &rtc;
ethernet0 = &enetc0;
ethernet1 = &enetc1;
ethernet2 = &enetc2;
ethernet3 = &enetc6;
};
@ -52,6 +50,28 @@
};
fdt-2 {
description = "fsl-ls1028a-kontron-sl28-var1";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dtb";
};
};
fdt-3 {
description = "fsl-ls1028a-kontron-sl28-var2";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dtb";
};
};
fdt-4 {
description = "fsl-ls1028a-kontron-sl28-var3";
type = "flat_dt";
arch = "arm";
@ -62,7 +82,7 @@
};
};
fdt-3 {
fdt-5 {
description = "fsl-ls1028a-kontron-sl28-var4";
type = "flat_dt";
arch = "arm";
@ -84,16 +104,30 @@
};
conf-2 {
description = "fsl-ls1028a-kontron-sl28-var3";
description = "fsl-ls1028a-kontron-sl28-var1";
firmware = "uboot";
fdt = "fdt-2";
};
conf-3 {
description = "fsl-ls1028a-kontron-sl28-var4";
description = "fsl-ls1028a-kontron-sl28-var2";
firmware = "uboot";
fdt = "fdt-3";
};
conf-4 {
description = "fsl-ls1028a-kontron-sl28-var3";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-4";
};
conf-5 {
description = "fsl-ls1028a-kontron-sl28-var4";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-5";
};
};
};
};
@ -133,6 +167,16 @@
firmware = "bl31";
loadables = "uboot";
};
conf-4 {
firmware = "bl31";
loadables = "uboot";
};
conf-5 {
firmware = "bl31";
loadables = "uboot";
};
};
};
};
@ -169,6 +213,14 @@
conf-3 {
loadables = "uboot", "bl32";
};
conf-4 {
loadables = "uboot", "bl32";
};
conf-5 {
loadables = "uboot", "bl32";
};
};
};
};

8
arch/arm/dts/fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi Normal file
View File

@ -0,0 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi"
/ {
aliases {
ethernet0 = &enetc1;
};
};

57
arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts Normal file
View File

@ -0,0 +1,57 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Device Tree file for the Kontron SMARC-sAL28 board.
*
* This is for the network variant 1 which has one ethernet port. It is
* different than the base variant, which also has one port, but here the
* port is connected via RGMII. This port is not TSN aware.
* None of the four SerDes lanes are used by the module, instead they are
* all led out to the carrier for customer use.
*
* Copyright (C) 2020 Michael Walle <michael@walle.cc>
*
*/
/dts-v1/;
#include "fsl-ls1028a-kontron-sl28.dts"
#include <dt-bindings/net/qca-ar803x.h>
/ {
model = "Kontron SMARC-sAL28 (4 Lanes)";
compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
};
&enetc0 {
status = "disabled";
/delete-property/ phy-handle;
};
&enetc1 {
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
};
/delete-node/ &phy0;
&mdio0 {
phy0: ethernet-phy@4 {
reg = <0x4>;
eee-broken-1000t;
eee-broken-100tx;
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
vddio-supply = <&vddh>;
vddio: vddio-regulator {
regulator-name = "VDDIO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddh: vddh-regulator {
regulator-name = "VDDH";
};
};
};

2
arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi Normal file
View File

@ -0,0 +1,2 @@
// SPDX-License-Identifier: GPL-2.0+
#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi"

25
arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts Normal file
View File

@ -0,0 +1,25 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Device Tree file for the Kontron SMARC-sAL28 board.
*
* This is for the network variant 2 which has no ethernet support in the
* bootloader.
*
* Copyright (C) 2020 Michael Walle <michael@walle.cc>
*
*/
/dts-v1/;
#include "fsl-ls1028a-kontron-sl28.dts"
/ {
model = "Kontron SMARC-sAL28 (TSN-on-module)";
compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a";
};
&enetc0 {
status = "disabled";
/delete-property/ phy-handle;
};
/delete-node/ &phy0;

6
arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi
View File

@ -1,2 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi"
/ {
aliases {
ethernet0 = &enetc0;
};
};

7
arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi
View File

@ -1,2 +1,9 @@
// SPDX-License-Identifier: GPL-2.0+
#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi"
/ {
aliases {
ethernet0 = &enetc0;
ethernet1 = &enetc1;
};
};

4
arch/arm/dts/fsl-ls1028a-kontron-sl28.dts
View File

@ -172,6 +172,10 @@
};
};
&sata {
status = "okay";
};
&serial0 {
status = "okay";
};

33
arch/arm/dts/fsl-ls1028a.dtsi
View File

@ -380,6 +380,39 @@
status = "disabled";
};
gpio0: gpio@2300000 {
compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
little-endian;
};
gpio1: gpio@2310000 {
compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
little-endian;
};
gpio2: gpio@2320000 {
compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
little-endian;
};
sata: sata@3200000 {
compatible = "fsl,ls1028a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */

40
arch/arm/dts/fsl-ls1043a.dtsi
View File

@ -79,6 +79,46 @@
bus-width = <4>;
};
gpio0: gpio@2300000 {
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <0 66 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@2310000 {
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <0 67 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2320000 {
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <0 68 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@2330000 {
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <0 134 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;

40
arch/arm/dts/fsl-ls1046a.dtsi
View File

@ -78,6 +78,46 @@
bus-width = <4>;
};
gpio0: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <0 66 4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@2310000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <0 67 4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2320000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <0 68 4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@2330000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <0 134 4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;

47
arch/arm/dts/fsl-ls1088a.dtsi
View File

@ -2,9 +2,10 @@
/*
* NXP ls1088a SOC common device tree source
*
* Copyright 2017, 2020 NXP
* Copyright 2017, 2020-2021 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "fsl,ls1088a";
interrupt-parent = <&gic>;
@ -115,6 +116,50 @@
bus-width = <4>;
};
gpio0: gpio@2300000 {
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@2310000 {
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2320000 {
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@2330000 {
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x2240000 0x0 0x20000>;

46
arch/arm/dts/fsl-ls2080a.dtsi
View File

@ -2,7 +2,7 @@
/*
* NXP ls2080a SOC common device tree source
*
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*/
@ -120,6 +120,50 @@
bus-width = <4>;
};
gpio0: gpio@2300000 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <0 36 0x4>; /* Level high type */
gpio-controller;
little-endian;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@2310000 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <0 36 0x4>; /* Level high type */
gpio-controller;
little-endian;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2320000 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <0 37 0x4>; /* Level high type */
gpio-controller;
little-endian;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@2330000 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <0 37 0x4>; /* Level high type */
gpio-controller;
little-endian;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
usb0: usb3@3100000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;

125
arch/arm/dts/fsl-lx2162a-qds.dts
View File

@ -15,20 +15,123 @@
compatible = "fsl,lx2162aqds", "fsl,lx2160a";
aliases {
pcie@3500000 {
status = "disabled";
};
pcie@3800000 {
status = "disabled";
};
pcie@3900000 {
status = "disabled";
};
spi1 = &dspi0;
spi2 = &dspi1;
spi3 = &dspi2;
};
};
&usb1 {
status = "disabled";
};
&pcie2 {
status = "disabled";
};
&pcie5 {
status = "disabled";
};
&pcie6 {
status = "disabled";
};
&dspi0 {
bus-num = <0>;
status = "okay";
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <2>;
};
};
&dspi1 {
bus-num = <0>;
status = "okay";
dflash3: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash4: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash5: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <2>;
};
};
&dspi2 {
bus-num = <0>;
status = "okay";
dflash6: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash7: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash8: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <2>;
};
};

40
arch/arm/dts/ls1021a.dtsi
View File

@ -98,6 +98,46 @@
bus-width = <4>;
};
gpio0: gpio@2300000 {
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@2310000 {
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2320000 {
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@2330000 {
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
scfg: scfg@1570000 {
compatible = "fsl,ls1021a-scfg", "syscon";
reg = <0x1570000 0x10000>;

10
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View File

@ -589,5 +589,15 @@ struct ccsr_serdes {
u8 res5[0x19fc - 0xa00];
};
struct ccsr_gpio {
u32 gpdir;
u32 gpodr;
u32 gpdat;
u32 gpier;
u32 gpimr;
u32 gpicr;
u32 gpibe;
};
#endif /*__ASSEMBLY__ */
#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */

40
arch/arm/include/asm/arch-fsl-layerscape/soc.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017-2020 NXP
* Copyright 2017-2021 NXP
* Copyright 2015 Freescale Semiconductor
*/
@ -16,6 +16,7 @@
#include <asm/arch/immap_lsch3.h>
#endif
#endif
#include <asm/arch/svr.h>
#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
#define gur_in32(a) in_le32(a)
@ -77,46 +78,17 @@ enum boot_src get_boot_src(void);
#endif
#endif
#define SVR_WO_E 0xFFFFFE
#define SVR_LS1012A 0x870400
#define SVR_LS1043A 0x879200
#define SVR_LS1023A 0x879208
/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
#define SVR_LS1043A_P23 0x879202
#define SVR_LS1023A_P23 0x87920A
#define SVR_LS1017A 0x870B24
#define SVR_LS1018A 0x870B20
#define SVR_LS1027A 0x870B04
#define SVR_LS1028A 0x870B00
#define SVR_LS1046A 0x870700
#define SVR_LS1026A 0x870708
#define SVR_LS1048A 0x870320
#define SVR_LS1084A 0x870302
#define SVR_LS1088A 0x870300
#define SVR_LS1044A 0x870322
#define SVR_LS2045A 0x870120
#define SVR_LS2080A 0x870110
#define SVR_LS2085A 0x870100
#define SVR_LS2040A 0x870130
#define SVR_LS2088A 0x870900
#define SVR_LS2084A 0x870910
#define SVR_LS2048A 0x870920
#define SVR_LS2044A 0x870930
#define SVR_LS2081A 0x870918
#define SVR_LS2041A 0x870914
#define SVR_LX2160A 0x873600
#define SVR_LX2120A 0x873620
#define SVR_LX2080A 0x873602
#define SVR_LX2162A 0x873608
#define SVR_LX2122A 0x873628
#define SVR_LX2082A 0x87360A
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
#define SVR_REV(svr) (((svr) >> 0) & 0xff)
#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1))
#define SVR_WO_CE 0xFFFFEE
#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_CE)
#else
#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
#endif
#ifdef CONFIG_ARCH_LS1028A
#define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1))

4
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2015-2020 NXP
* Copyright 2015-2021 NXP
* Copyright 2014 Freescale Semiconductor, Inc.
*
*/
@ -103,7 +103,7 @@
#define FSL_DPAA2_STREAM_ID_END 63
/* PCI IEPs, this overlaps DPAA2 but these two are exclusive at least for now */
#define FSL_ECAM_STREAM_ID_START 32
#define FSL_ECAM_STREAM_ID_START 41
#define FSL_ECAM_STREAM_ID_END 63
#define FSL_SEC_STREAM_ID 64

42
arch/arm/include/asm/arch-fsl-layerscape/svr.h Normal file
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@ -0,0 +1,42 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2021 NXP
*/
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_
#define _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_
#define SVR_LS1012A 0x870400
#define SVR_LS1043A 0x879200
#define SVR_LS1023A 0x879208
/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
#define SVR_LS1043A_P23 0x879202
#define SVR_LS1023A_P23 0x87920A
#define SVR_LS1017A 0x870B24
#define SVR_LS1018A 0x870B20
#define SVR_LS1027A 0x870B04
#define SVR_LS1028A 0x870B00
#define SVR_LS1046A 0x870700
#define SVR_LS1026A 0x870708
#define SVR_LS1048A 0x870320
#define SVR_LS1084A 0x870302
#define SVR_LS1088A 0x870300
#define SVR_LS1044A 0x870322
#define SVR_LS2045A 0x870120
#define SVR_LS2080A 0x870110
#define SVR_LS2085A 0x870100
#define SVR_LS2040A 0x870130
#define SVR_LS2088A 0x870900
#define SVR_LS2084A 0x870910
#define SVR_LS2048A 0x870920
#define SVR_LS2044A 0x870930
#define SVR_LS2081A 0x870918
#define SVR_LS2041A 0x870914
#define SVR_LX2160A 0x873600
#define SVR_LX2120A 0x873620
#define SVR_LX2080A 0x873602
#define SVR_LX2162A 0x873608
#define SVR_LX2122A 0x873628
#define SVR_LX2082A 0x87360A
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ */

16
arch/arm/include/asm/arch-ls102xa/gpio.h
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@ -13,4 +13,20 @@
#ifndef __ASM_ARCH_LS102XA_GPIO_H_
#define __ASM_ARCH_LS102XA_GPIO_H_
struct ccsr_gpio {
u32 gpdir;
u32 gpodr;
u32 gpdat;
u32 gpier;
u32 gpimr;
u32 gpicr;
u32 gpibe;
};
struct mpc8xxx_gpio_plat {
ulong addr;
ulong size;
uint ngpios;
};
#endif

13
arch/arm/include/asm/arch-ls102xa/svr.h Normal file
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@ -0,0 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2021 NXP
*/
#ifndef _ASM_LS102X_SVR_H_
#define _ASM_LS102X_SVR_H_
#define SVR_LS102XA 0
#define SVR_VAR_PER_SHIFT 8
#define SVR_LS102XA_MASK 0x700
#endif /* _ASM_LS102X_SVR_H_ */

4
arch/powerpc/cpu/mpc85xx/Kconfig
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@ -256,6 +256,10 @@ config TARGET_KMP204X
bool "Support kmp204x"
select VENDOR_KM
config TARGET_KMCENT2
bool "Support kmcent2"
select VENDOR_KM
config TARGET_XPEDITE520X
bool "Support xpedite520x"
select ARCH_MPC8548

2
arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
View File

@ -390,7 +390,7 @@ int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn)
return -1;
sizebit = __ilog2_roundup_64(size);
size = 1 << sizebit;
size = 1ull << sizebit;
debug("min start_addr is %llx\n", min_addr);
debug("max end_addr is %llx\n", max_addr);
debug("size found is %llx\n", size);

1
arch/powerpc/dts/Makefile
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@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_KMCENT2) += kmcent2.dtb
dtb-$(CONFIG_TARGET_KMCOGE5NE) += kmcoge5ne.dtb
dtb-$(CONFIG_TARGET_KMETER1) += kmeter1.dtb
dtb-$(CONFIG_TARGET_KMOPTI2) += kmopti2.dtb

55
arch/powerpc/dts/elo3-dma-0.dtsi Normal file
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@ -0,0 +1,55 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* QorIQ Elo3 DMA device tree stub [ controller @ offset 0x100000 ]
*
* Copyright 2013 Freescale Semiconductor Inc.
*/
dma0: dma@100300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,elo3-dma";
reg = <0x100300 0x4>,
<0x100600 0x4>;
ranges = <0x0 0x100100 0x500>;
dma-channel@0 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
interrupts = <28 2 0 0>;
};
dma-channel@80 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
interrupts = <29 2 0 0>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
interrupts = <30 2 0 0>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
interrupts = <31 2 0 0>;
};
dma-channel@300 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x300 0x80>;
interrupts = <76 2 0 0>;
};
dma-channel@380 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x380 0x80>;
interrupts = <77 2 0 0>;
};
dma-channel@400 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x400 0x80>;
interrupts = <78 2 0 0>;
};
dma-channel@480 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x480 0x80>;
interrupts = <79 2 0 0>;
};
};

55
arch/powerpc/dts/elo3-dma-1.dtsi Normal file
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@ -0,0 +1,55 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ]
*
* Copyright 2013 Freescale Semiconductor Inc.
*/
dma1: dma@101300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,elo3-dma";
reg = <0x101300 0x4>,
<0x101600 0x4>;
ranges = <0x0 0x101100 0x500>;
dma-channel@0 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
interrupts = <32 2 0 0>;
};
dma-channel@80 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
interrupts = <33 2 0 0>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
interrupts = <34 2 0 0>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
interrupts = <35 2 0 0>;
};
dma-channel@300 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x300 0x80>;
interrupts = <80 2 0 0>;
};
dma-channel@380 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x380 0x80>;
interrupts = <81 2 0 0>;
};
dma-channel@400 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x400 0x80>;
interrupts = <82 2 0 0>;
};
dma-channel@480 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x480 0x80>;
interrupts = <83 2 0 0>;
};
};

97
arch/powerpc/dts/kmcent2-u-boot.dtsi Normal file
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@ -0,0 +1,97 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* (C) Copyright 2021 Niel Fourie <lusus@denx.de>
*/
#include <config.h>
/ {
aliases {
spi0 = "/soc@ffe000000/spi@110000";
i2c0 = "/soc@ffe000000/i2c@118000";
i2c1 = "/soc@ffe000000/i2c@118000/mux@70/i2c@0";
i2c2 = "/soc@ffe000000/i2c@118000/mux@70/i2c@1";
i2c3 = "/soc@ffe000000/i2c@118000/mux@70/i2c@7";
i2c4 = "/soc@ffe000000/i2c@118100";
/delete-property/ pci1;
/delete-property/ pci2;
/delete-property/ pci3;
};
chosen {
stdout-path = "/soc@ffe000000/serial@11c500";
};
soc@ffe000000 {
u-boot,dm-pre-reloc;
spi@110000 {
/* This documents where km_fpgacfg should be appear */
fpga@0 {
compatible = "keymile,fpga-conf";
reg = <0>;
spi-max-frequency = <25000000>;
};
};
sdhc@114000 {
status = "okay";
};
i2c@118000 {
u-boot,dm-pre-reloc;
mux@70 {
i2c@1 { /* IVM bus */
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
serial@11c500 {
u-boot,dm-pre-reloc;
clock-frequency = <200000000>;
};
fman@400000 {
ethernet@e0000 {
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-connection-type = "rgmii-id";
};
};
};
pcie@ffe240000 {
compatible = "fsl,pcie-t104x";
law_trgt_if = <0>;
};
binman {
filename = "u-boot-with-dtb.bin";
skip-at-start = <CONFIG_SYS_TEXT_BASE>;
sort-by-offset;
pad-byte = <0xff>;
size = <CONFIG_SYS_MONITOR_LEN>;
u-boot-with-ucode-ptr {
offset = <CONFIG_SYS_TEXT_BASE>;
optional-ucode;
};
u-boot-dtb-with-ucode {
align = <256>;
};
powerpc-mpc85xx-bootpg-resetvec {
offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
};
};
};

338
arch/powerpc/dts/kmcent2.dts Normal file
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@ -0,0 +1,338 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Keymile kmcent2 Device Tree Source, based on T1040RDB DTS
*
* (C) Copyright 2016
* Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
*
* Copyright 2014 - 2015 Freescale Semiconductor Inc.
*/
/include/ "t104xsi-pre.dtsi"
/ {
model = "keymile,kmcent2";
compatible = "keymile,kmcent2";
aliases {
front_phy = &front_phy;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
qman_fqd: qman-fqd {
size = <0 0x400000>;
alignment = <0 0x400000>;
};
qman_pfdr: qman-pfdr {
size = <0 0x2000000>;
alignment = <0 0x2000000>;
};
};
ifc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x2000>;
ranges = <0 0 0xf 0xe8000000 0x04000000
1 0 0xf 0xfa000000 0x00010000
2 0 0xf 0xfb000000 0x00010000
4 0 0xf 0xc0000000 0x08000000
6 0 0xf 0xd0000000 0x08000000
7 0 0xf 0xd8000000 0x08000000>;
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x04000000>;
bank-width = <2>;
device-width = <2>;
};
nand@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,ifc-nand";
reg = <0x1 0x0 0x10000>;
};
board-control@2,0 {
compatible = "keymile,qriox";
reg = <0x2 0x0 0x80>;
};
chassis-mgmt@6,0 {
compatible = "keymile,bfticu";
reg = <6 0 0x100>;
interrupt-controller;
interrupt-parent = <&mpic>;
interrupts = <11 1 0 0>;
#interrupt-cells = <1>;
};
};
memory {
device_type = "memory";
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01072000>;
};
bportals: bman-portals@ff4000000 {
ranges = <0x0 0xf 0xf4000000 0x2000000>;
};
qportals: qman-portals@ff6000000 {
ranges = <0x0 0xf 0xf6000000 0x2000000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
spi@110000 {
network-clock@1 {
compatible = "zarlink,zl30364";
reg = <1>;
spi-max-frequency = <1000000>;
};
};
sdhc@114000 {
status = "disabled";
};
i2c@118000 {
clock-frequency = <100000>;
mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@54 {
compatible = "atmel,24c02";
reg = <0x54>;
pagesize = <2>;
read-only;
label = "ddr3-spd";
};
};
i2c@7 {
reg = <7>;
#address-cells = <1>;
#size-cells = <0>;
temp-sensor@48 {
compatible = "national,lm75";
reg = <0x48>;
label = "SENSOR_0";
};
temp-sensor@4a {
compatible = "national,lm75";
reg = <0x4a>;
label = "SENSOR_2";
};
temp-sensor@4b {
compatible = "national,lm75";
reg = <0x4b>;
label = "SENSOR_3";
};
};
};
};
i2c@118100 {
clock-frequency = <100000>;
eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
pagesize = <16>;
};
eeprom@54 {
compatible = "atmel,24c08";
reg = <0x54>;
pagesize = <16>;
};
};
i2c@119000 {
status = "disabled";
};
i2c@119100 {
status = "disabled";
};
serial2: serial@11d500 {
status = "disabled";
};
serial3: serial@11d600 {
status = "disabled";
};
usb0: usb@210000 {
status = "disabled";
};
usb1: usb@211000 {
status = "disabled";
};
display@180000 {
status = "disabled";
};
sata@220000 {
status = "disabled";
};
sata@221000 {
status = "disabled";
};
fman@400000 {
ethernet@e0000 {
phy-mode = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
ethernet@e2000 {
phy-mode = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
ethernet@e4000 {
status = "disabled";
};
ethernet@e6000 {
status = "disabled";
};
ethernet@e8000 {
phy-handle = <&front_phy>;
phy-mode = "rgmii-id";
};
mdio0: mdio@fc000 {
front_phy: ethernet-phy@11 {
reg = <0x11>;
};
};
};
};
pci0: pcie@ffe240000 {
reg = <0xf 0xfe240000 0 0x10000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x20000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
pci1: pcie@ffe250000 {
status = "disabled";
reg = <0xf 0xfe250000 0 0x10000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000
0x01000000 0 0 0xf 0xf8010000 0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x10000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
pci2: pcie@ffe260000 {
status = "disabled";
reg = <0xf 0xfe260000 0 0x10000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x10000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
pci3: pcie@ffe270000 {
status = "disabled";
reg = <0xf 0xfe270000 0 0x10000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x10000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
qe: qe@ffe140000 {
ranges = <0x0 0xf 0xfe140000 0x40000>;
reg = <0xf 0xfe140000 0 0x480>;
brg-frequency = <0>;
bus-frequency = <0>;
si1: si@700 {
compatible = "fsl,t1040-qe-si";
reg = <0x700 0x80>;
};
siram1: siram@1000 {
compatible = "fsl,t1040-qe-siram";
reg = <0x1000 0x800>;
};
ucc_hdlc: ucc@2000 {
device_type = "hdlc";
compatible = "fsl,ucc-hdlc";
rx-clock-name = "clk9";
tx-clock-name = "clk9";
fsl,hdlc-bus;
};
};
};
#include "t1040si-post.dtsi"

14
arch/powerpc/dts/qoriq-bman1.dtsi Normal file
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@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* QorIQ BMan device tree stub [ controller @ offset 0x31a000 ]
*
* Copyright 2011 - 2014 Freescale Semiconductor Inc.
*/
bman: bman@31a000 {
compatible = "fsl,bman";
reg = <0x31a000 0x1000>;
interrupts = <16 2 1 2>;
fsl,bman-portals = <&bportals>;
memory-region = <&bman_fbpr>;
};

24
arch/powerpc/dts/qoriq-duart-0.dtsi Normal file
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@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* QorIQ DUART device tree stub [ controller @ offset 0x11c000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
*/
serial0: serial@11c500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x11c500 0x100>;
clock-frequency = <0>;
interrupts = <36 2 0 0>;
};
serial1: serial@11c600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x11c600 0x100>;
clock-frequency = <0>;
interrupts = <36 2 0 0>;
};

24
arch/powerpc/dts/qoriq-duart-1.dtsi Normal file
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@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* QorIQ DUART device tree stub [ controller @ offset 0x11d000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
*/
serial2: serial@11d500 {
cell-index = <2>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x11d500 0x100>;
clock-frequency = <0>;
interrupts = <37 2 0 0>;
};
serial3: serial@11d600 {
cell-index = <3>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x11d600 0x100>;
clock-frequency = <0>;
interrupts = <37 2 0 0>;
};

13
arch/powerpc/dts/qoriq-esdhc-0.dtsi Normal file
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@ -0,0 +1,13 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* QorIQ eSDHC device tree stub [ controller @ offset 0x114000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
*/
sdhc: sdhc@114000 {
compatible = "fsl,esdhc";
reg = <0x114000 0x1000>;
interrupts = <48 2 0 0>;
clock-frequency = <0>;
};

14
arch/powerpc/dts/qoriq-espi-0.dtsi Normal file
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@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* QorIQ eSPI device tree stub [ controller @ offset 0x110000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
*/
spi@110000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc8536-espi";
reg = <0x110000 0x1000>;
interrupts = <53 0x2 0 0>;
};

79
arch/powerpc/dts/qoriq-mpic.dtsi Normal file
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@ -0,0 +1,79 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
*/
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "fsl,mpic", "chrp,open-pic";
device_type = "open-pic";
clock-frequency = <0x0>;
};
timer@41100 {
compatible = "fsl,mpic-global-timer";
reg = <0x41100 0x100 0x41300 4>;
interrupts = <0 0 3 0
1 0 3 0
2 0 3 0
3 0 3 0>;
};
msi0: msi@41600 {
compatible = "fsl,mpic-msi";
reg = <0x41600 0x200 0x44140 4>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0 0 0
0xe1 0 0 0
0xe2 0 0 0
0xe3 0 0 0
0xe4 0 0 0
0xe5 0 0 0
0xe6 0 0 0
0xe7 0 0 0>;
};
msi1: msi@41800 {
compatible = "fsl,mpic-msi";
reg = <0x41800 0x200 0x45140 4>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe8 0 0 0
0xe9 0 0 0
0xea 0 0 0
0xeb 0 0 0
0xec 0 0 0
0xed 0 0 0
0xee 0 0 0
0xef 0 0 0>;
};
msi2: msi@41a00 {
compatible = "fsl,mpic-msi";
reg = <0x41a00 0x200 0x46140 4>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xf0 0 0 0
0xf1 0 0 0
0xf2 0 0 0
0xf3 0 0 0
0xf4 0 0 0
0xf5 0 0 0
0xf6 0 0 0
0xf7 0 0 0>;
};
timer@42100 {
compatible = "fsl,mpic-global-timer";
reg = <0x42100 0x100 0x42300 4>;
interrupts = <4 0 3 0
5 0 3 0
6 0 3 0
7 0 3 0>;
};

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* QorIQ QMan rev3 device tree stub [ controller @ offset 0x318000 ]
*
* Copyright 2014 Freescale Semiconductor Inc.
*/
qman: qman@318000 {
compatible = "fsl,qman";
reg = <0x318000 0x2000>;
interrupts = <16 2 1 3>;
fsl,qman-portals = <&qportals>;
memory-region = <&qman_fqd &qman_pfdr>;
};

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* QorIQ SATAv2 device tree stub [ controller @ offset 0x220000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
*/
sata@220000 {
compatible = "fsl,pq-sata-v2";
reg = <0x220000 0x1000>;
interrupts = <68 0x2 0 0>;
};

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* QorIQ SATAv2 device tree stub [ controller @ offset 0x221000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
*/
sata@221000 {
compatible = "fsl,pq-sata-v2";
reg = <0x221000 0x1000>;
interrupts = <69 0x2 0 0>;
};

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
*
* Copyright 2012 Freescale Semiconductor Inc.
*/
crypto: crypto@300000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <5>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300000 0x10000>;
ranges = <0 0x300000 0x10000>;
interrupts = <92 2 0 0>;
sec_jr0: jr@1000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <88 2 0 0>;
};
sec_jr1: jr@2000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <89 2 0 0>;
};
sec_jr2: jr@3000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <90 2 0 0>;
};
sec_jr3: jr@4000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x4000 0x1000>;
interrupts = <91 2 0 0>;
};
rtic@6000 {
compatible = "fsl,sec-v5.0-rtic",
"fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x6000 0x100>;
ranges = <0x0 0x6100 0xe00>;
rtic_a: rtic-a@0 {
compatible = "fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x00 0x20 0x100 0x80>;
};
rtic_b: rtic-b@20 {
compatible = "fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x20 0x20 0x200 0x80>;
};
rtic_c: rtic-c@40 {
compatible = "fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x40 0x20 0x300 0x80>;
};
rtic_d: rtic-d@60 {
compatible = "fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x60 0x20 0x500 0x80>;
};
};
};
sec_mon: sec_mon@314000 {
compatible = "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
reg = <0x314000 0x1000>;
interrupts = <93 2 0 0>;
};

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* QorIQ USB DR device tree stub [ controller @ offset 0x211000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
*/
usb@211000 {
compatible = "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
reg = <0x211000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <45 0x2 0 0>;
};

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* QorIQ USB Host device tree stub [ controller @ offset 0x210000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
*/
usb@210000 {
compatible = "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
reg = <0x210000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <44 0x2 0 0>;
};

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* T1040 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2013 - 2014 Freescale Semiconductor Inc.
*/
#include <dt-bindings/thermal/thermal.h>
&bman_fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0x10000 0>;
};
&qman_fqd {
compatible = "fsl,qman-fqd";
alloc-ranges = <0 0 0x10000 0>;
};
&qman_pfdr {
compatible = "fsl,qman-pfdr";
alloc-ranges = <0 0 0x10000 0>;
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,ifc", "simple-bus";
interrupts = <25 2 0 0>;
};
&pci0 {
compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0x0 0xff>;
interrupts = <20 2 0 0>;
fsl,iommu-parent = <&pamu0>;
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
interrupts = <20 2 0 0>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 40 1 0 0
0000 0 0 2 &mpic 1 1 0 0
0000 0 0 3 &mpic 2 1 0 0
0000 0 0 4 &mpic 3 1 0 0
>;
};
};
&pci1 {
compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0 0xff>;
interrupts = <21 2 0 0>;
fsl,iommu-parent = <&pamu0>;
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
interrupts = <21 2 0 0>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 41 1 0 0
0000 0 0 2 &mpic 5 1 0 0
0000 0 0 3 &mpic 6 1 0 0
0000 0 0 4 &mpic 7 1 0 0
>;
};
};
&pci2 {
compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0x0 0xff>;
interrupts = <22 2 0 0>;
fsl,iommu-parent = <&pamu0>;
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
interrupts = <22 2 0 0>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 42 1 0 0
0000 0 0 2 &mpic 9 1 0 0
0000 0 0 3 &mpic 10 1 0 0
0000 0 0 4 &mpic 11 1 0 0
>;
};
};
&pci3 {
compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0x0 0xff>;
interrupts = <23 2 0 0>;
fsl,iommu-parent = <&pamu0>;
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
interrupts = <23 2 0 0>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 43 1 0 0
0000 0 0 2 &mpic 0 1 0 0
0000 0 0 3 &mpic 4 1 0 0
0000 0 0 4 &mpic 8 1 0 0
>;
};
};
&dcsr {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,dcsr", "simple-bus";
dcsr-epu@0 {
compatible = "fsl,t1040-dcsr-epu", "fsl,dcsr-epu";
interrupts = <52 2 0 0
84 2 0 0
85 2 0 0>;
reg = <0x0 0x1000>;
};
dcsr-npc {
compatible = "fsl,t1040-dcsr-cnpc", "fsl,dcsr-cnpc";
reg = <0x1000 0x1000 0x1002000 0x10000>;
};
dcsr-nxc@2000 {
compatible = "fsl,dcsr-nxc";
reg = <0x2000 0x1000>;
};
dcsr-corenet {
compatible = "fsl,dcsr-corenet";
reg = <0x8000 0x1000 0x1A000 0x1000>;
};
dcsr-dpaa@9000 {
compatible = "fsl,t1040-dcsr-dpaa", "fsl,dcsr-dpaa";
reg = <0x9000 0x1000>;
};
dcsr-ocn@11000 {
compatible = "fsl,t1040-dcsr-ocn", "fsl,dcsr-ocn";
reg = <0x11000 0x1000>;
};
dcsr-ddr@12000 {
compatible = "fsl,dcsr-ddr";
dev-handle = <&ddr1>;
reg = <0x12000 0x1000>;
};
dcsr-nal@18000 {
compatible = "fsl,t1040-dcsr-nal", "fsl,dcsr-nal";
reg = <0x18000 0x1000>;
};
dcsr-rcpm@22000 {
compatible = "fsl,t1040-dcsr-rcpm", "fsl,dcsr-rcpm";
reg = <0x22000 0x1000>;
};
dcsr-snpc@30000 {
compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc";
reg = <0x30000 0x1000 0x1022000 0x10000>;
};
dcsr-snpc@31000 {
compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc";
reg = <0x31000 0x1000 0x1042000 0x10000>;
};
dcsr-cpu-sb-proxy@100000 {
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu0>;
reg = <0x100000 0x1000 0x101000 0x1000>;
};
dcsr-cpu-sb-proxy@108000 {
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu1>;
reg = <0x108000 0x1000 0x109000 0x1000>;
};
dcsr-cpu-sb-proxy@110000 {
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu2>;
reg = <0x110000 0x1000 0x111000 0x1000>;
};
dcsr-cpu-sb-proxy@118000 {
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu3>;
reg = <0x118000 0x1000 0x119000 0x1000>;
};
};
&bportals {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "simple-bus";
bman-portal@0 {
compatible = "fsl,bman-portal";
reg = <0x0 0x4000>, <0x1000000 0x1000>;
interrupts = <105 2 0 0>;
};
bman-portal@4000 {
compatible = "fsl,bman-portal";
reg = <0x4000 0x4000>, <0x1001000 0x1000>;
interrupts = <107 2 0 0>;
};
bman-portal@8000 {
compatible = "fsl,bman-portal";
reg = <0x8000 0x4000>, <0x1002000 0x1000>;
interrupts = <109 2 0 0>;
};
bman-portal@c000 {
compatible = "fsl,bman-portal";
reg = <0xc000 0x4000>, <0x1003000 0x1000>;
interrupts = <111 2 0 0>;
};
bman-portal@10000 {
compatible = "fsl,bman-portal";
reg = <0x10000 0x4000>, <0x1004000 0x1000>;
interrupts = <113 2 0 0>;
};
bman-portal@14000 {
compatible = "fsl,bman-portal";
reg = <0x14000 0x4000>, <0x1005000 0x1000>;
interrupts = <115 2 0 0>;
};
bman-portal@18000 {
compatible = "fsl,bman-portal";
reg = <0x18000 0x4000>, <0x1006000 0x1000>;
interrupts = <117 2 0 0>;
};
bman-portal@1c000 {
compatible = "fsl,bman-portal";
reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
interrupts = <119 2 0 0>;
};
bman-portal@20000 {
compatible = "fsl,bman-portal";
reg = <0x20000 0x4000>, <0x1008000 0x1000>;
interrupts = <121 2 0 0>;
};
bman-portal@24000 {
compatible = "fsl,bman-portal";
reg = <0x24000 0x4000>, <0x1009000 0x1000>;
interrupts = <123 2 0 0>;
};
};
&qportals {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "simple-bus";
qportal0: qman-portal@0 {
compatible = "fsl,qman-portal";
reg = <0x0 0x4000>, <0x1000000 0x1000>;
interrupts = <104 0x2 0 0>;
cell-index = <0x0>;
};
qportal1: qman-portal@4000 {
compatible = "fsl,qman-portal";
reg = <0x4000 0x4000>, <0x1001000 0x1000>;
interrupts = <106 0x2 0 0>;
cell-index = <0x1>;
};
qportal2: qman-portal@8000 {
compatible = "fsl,qman-portal";
reg = <0x8000 0x4000>, <0x1002000 0x1000>;
interrupts = <108 0x2 0 0>;
cell-index = <0x2>;
};
qportal3: qman-portal@c000 {
compatible = "fsl,qman-portal";
reg = <0xc000 0x4000>, <0x1003000 0x1000>;
interrupts = <110 0x2 0 0>;
cell-index = <0x3>;
};
qportal4: qman-portal@10000 {
compatible = "fsl,qman-portal";
reg = <0x10000 0x4000>, <0x1004000 0x1000>;
interrupts = <112 0x2 0 0>;
cell-index = <0x4>;
};
qportal5: qman-portal@14000 {
compatible = "fsl,qman-portal";
reg = <0x14000 0x4000>, <0x1005000 0x1000>;
interrupts = <114 0x2 0 0>;
cell-index = <0x5>;
};
qportal6: qman-portal@18000 {
compatible = "fsl,qman-portal";
reg = <0x18000 0x4000>, <0x1006000 0x1000>;
interrupts = <116 0x2 0 0>;
cell-index = <0x6>;
};
qportal7: qman-portal@1c000 {
compatible = "fsl,qman-portal";
reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
interrupts = <118 0x2 0 0>;
cell-index = <0x7>;
};
qportal8: qman-portal@20000 {
compatible = "fsl,qman-portal";
reg = <0x20000 0x4000>, <0x1008000 0x1000>;
interrupts = <120 0x2 0 0>;
cell-index = <0x8>;
};
qportal9: qman-portal@24000 {
compatible = "fsl,qman-portal";
reg = <0x24000 0x4000>, <0x1009000 0x1000>;
interrupts = <122 0x2 0 0>;
cell-index = <0x9>;
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
soc-sram-error {
compatible = "fsl,soc-sram-error";
interrupts = <16 2 1 29>;
};
corenet-law@0 {
compatible = "fsl,corenet-law";
reg = <0x0 0x1000>;
fsl,num-laws = <16>;
};
ddr1: memory-controller@8000 {
compatible = "fsl,qoriq-memory-controller-v5.0",
"fsl,qoriq-memory-controller";
reg = <0x8000 0x1000>;
interrupts = <16 2 1 23>;
};
cpc: l3-cache-controller@10000 {
compatible = "fsl,t1040-l3-cache-controller", "cache";
reg = <0x10000 0x1000>;
interrupts = <16 2 1 27>;
};
corenet-cf@18000 {
compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 31>;
fsl,ccf-num-csdids = <32>;
fsl,ccf-num-snoopids = <32>;
};
iommu@20000 {
compatible = "fsl,pamu-v1.0", "fsl,pamu";
reg = <0x20000 0x1000>;
ranges = <0 0x20000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <
24 2 0 0
16 2 1 30>;
pamu0: pamu@0 {
reg = <0 0x1000>;
fsl,primary-cache-geometry = <128 1>;
fsl,secondary-cache-geometry = <16 2>;
};
};
/include/ "qoriq-mpic.dtsi"
guts: global-utilities@e0000 {
compatible = "fsl,t1040-device-config", "fsl,qoriq-device-config-2.0";
reg = <0xe0000 0xe00>;
fsl,has-rstcr;
fsl,liodn-bits = <12>;
};
/include/ "qoriq-clockgen2.dtsi"
global-utilities@e1000 {
compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0";
};
rcpm: global-utilities@e2000 {
compatible = "fsl,t1040-rcpm", "fsl,qoriq-rcpm-2.1";
reg = <0xe2000 0x1000>;
};
sfp: sfp@e8000 {
compatible = "fsl,t1040-sfp";
reg = <0xe8000 0x1000>;
};
serdes: serdes@ea000 {
compatible = "fsl,t1040-serdes";
reg = <0xea000 0x4000>;
};
tmu: tmu@f0000 {
compatible = "fsl,qoriq-tmu";
reg = <0xf0000 0x1000>;
interrupts = <18 2 0 0>;
fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
fsl,tmu-calibration = <0x00000000 0x00000025
0x00000001 0x00000028
0x00000002 0x0000002d
0x00000003 0x00000031
0x00000004 0x00000036
0x00000005 0x0000003a
0x00000006 0x00000040
0x00000007 0x00000044
0x00000008 0x0000004a
0x00000009 0x0000004f
0x0000000a 0x00000054
0x00010000 0x0000000d
0x00010001 0x00000013
0x00010002 0x00000019
0x00010003 0x0000001f
0x00010004 0x00000025
0x00010005 0x0000002d
0x00010006 0x00000033
0x00010007 0x00000043
0x00010008 0x0000004b
0x00010009 0x00000053
0x00020000 0x00000010
0x00020001 0x00000017
0x00020002 0x0000001f
0x00020003 0x00000029
0x00020004 0x00000031
0x00020005 0x0000003c
0x00020006 0x00000042
0x00020007 0x0000004d
0x00020008 0x00000056
0x00030000 0x00000012
0x00030001 0x0000001d>;
#thermal-sensor-cells = <1>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 2>;
trips {
cpu_alert: cpu-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_alert>;
cooling-device =
<&cpu1 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
map2 {
trip = <&cpu_alert>;
cooling-device =
<&cpu2 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
map3 {
trip = <&cpu_alert>;
cooling-device =
<&cpu3 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
};
scfg: global-utilities@fc000 {
compatible = "fsl,t1040-scfg";
reg = <0xfc000 0x1000>;
};
/include/ "elo3-dma-0.dtsi"
/include/ "elo3-dma-1.dtsi"
/include/ "qoriq-espi-0.dtsi"
spi@110000 {
fsl,espi-num-chipselects = <4>;
};
/include/ "qoriq-esdhc-0.dtsi"
sdhc@114000 {
compatible = "fsl,t1040-esdhc", "fsl,esdhc";
fsl,iommu-parent = <&pamu0>;
fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
sdhci,auto-cmd12;
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
/include/ "qoriq-duart-0.dtsi"
/include/ "qoriq-duart-1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
/include/ "qoriq-usb2-mph-0.dtsi"
usb0: usb@210000 {
compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph";
fsl,iommu-parent = <&pamu0>;
fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
phy_type = "utmi";
port0;
};
/include/ "qoriq-usb2-dr-0.dtsi"
usb1: usb@211000 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
fsl,iommu-parent = <&pamu0>;
fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
dr_mode = "host";
phy_type = "utmi";
};
display@180000 {
compatible = "fsl,t1040-diu", "fsl,diu";
reg = <0x180000 1000>;
interrupts = <74 2 0 0>;
};
/include/ "qoriq-sata2-0.dtsi"
sata@220000 {
fsl,iommu-parent = <&pamu0>;
fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
};
/include/ "qoriq-sata2-1.dtsi"
sata@221000 {
fsl,iommu-parent = <&pamu0>;
fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
};
/include/ "qoriq-sec5.0-0.dtsi"
/include/ "qoriq-qman3.dtsi"
/include/ "qoriq-bman1.dtsi"
/include/ "qoriq-fman3l-0.dtsi"
/include/ "qoriq-fman3-0-1g-0.dtsi"
/include/ "qoriq-fman3-0-1g-1.dtsi"
/include/ "qoriq-fman3-0-1g-2.dtsi"
/include/ "qoriq-fman3-0-1g-3.dtsi"
/include/ "qoriq-fman3-0-1g-4.dtsi"
fman@400000 {
enet0: ethernet@e0000 {
};
enet1: ethernet@e2000 {
};
enet2: ethernet@e4000 {
};
enet3: ethernet@e6000 {
};
enet4: ethernet@e8000 {
};
mdio@fc000 {
interrupts = <100 1 0 0>;
};
mdio@fd000 {
status = "disabled";
};
};
seville_switch: ethernet-switch@800000 {
compatible = "mscc,vsc9953-switch";
reg = <0x800000 0x290000>;
interrupts = <26 2 0 0>;
interrupt-names = "xtr";
little-endian;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
seville_port0: port@0 {
reg = <0>;
status = "disabled";
};
seville_port1: port@1 {
reg = <1>;
status = "disabled";
};
seville_port2: port@2 {
reg = <2>;
status = "disabled";
};
seville_port3: port@3 {
reg = <3>;
status = "disabled";
};
seville_port4: port@4 {
reg = <4>;
status = "disabled";
};
seville_port5: port@5 {
reg = <5>;
status = "disabled";
};
seville_port6: port@6 {
reg = <6>;
status = "disabled";
};
seville_port7: port@7 {
reg = <7>;
status = "disabled";
};
seville_port8: port@8 {
reg = <8>;
phy-mode = "internal";
status = "disabled";
fixed-link {
speed = <2500>;
full-duplex;
};
};
seville_port9: port@9 {
reg = <9>;
phy-mode = "internal";
status = "disabled";
fixed-link {
speed = <2500>;
full-duplex;
};
};
};
};
};
&qe {
#address-cells = <1>;
#size-cells = <1>;
device_type = "qe";
compatible = "fsl,qe";
fsl,qe-num-riscs = <1>;
fsl,qe-num-snums = <28>;
qeic: interrupt-controller@80 {
interrupt-controller;
compatible = "fsl,qe-ic";
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <0x80 0x80>;
interrupts = <95 2 0 0 94 2 0 0>; //high:79 low:78
};
ucc@2000 {
cell-index = <1>;
reg = <0x2000 0x200>;
interrupts = <32>;
interrupt-parent = <&qeic>;
};
ucc@2200 {
cell-index = <3>;
reg = <0x2200 0x200>;
interrupts = <34>;
interrupt-parent = <&qeic>;
};
muram@10000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0x0 0x10000 0x6000>;
data-only@0 {
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
reg = <0x0 0x6000>;
};
};
};

88
arch/powerpc/dts/t104xsi-pre.dtsi Normal file
View File

@ -0,0 +1,88 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* T1040/T1042 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2013-2014 Freescale Semiconductor Inc.
*/
/dts-v1/;
/include/ "e5500_power_isa.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
ccsr = &soc;
dcsr = &dcsr;
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
pci3 = &pci3;
usb0 = &usb0;
usb1 = &usb1;
sdhc = &sdhc;
crypto = &crypto;
fman0 = &fman0;
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
ethernet4 = &enet4;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,e5500@0 {
device_type = "cpu";
reg = <0>;
clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
};
};
cpu1: PowerPC,e5500@1 {
device_type = "cpu";
reg = <1>;
clocks = <&clockgen 1 1>;
next-level-cache = <&L2_2>;
#cooling-cells = <2>;
L2_2: l2-cache {
next-level-cache = <&cpc>;
};
};
cpu2: PowerPC,e5500@2 {
device_type = "cpu";
reg = <2>;
clocks = <&clockgen 1 2>;
next-level-cache = <&L2_3>;
#cooling-cells = <2>;
L2_3: l2-cache {
next-level-cache = <&cpc>;
};
};
cpu3: PowerPC,e5500@3 {
device_type = "cpu";
reg = <3>;
clocks = <&clockgen 1 3>;
next-level-cache = <&L2_4>;
#cooling-cells = <2>;
L2_4: l2-cache {
next-level-cache = <&cpc>;
};
};
};
};

13
arch/powerpc/include/asm/immap_83xx.h
View File

@ -966,6 +966,19 @@ typedef struct immap {
} immap_t;
#endif
struct ccsr_gpio {
u32 gpdir;
u32 gpodr;
u32 gpdat;
u32 gpier;
u32 gpimr;
u32 gpicr;
union {
u32 gpibe;
u8 res0[0xE8];
};
};
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
#define CONFIG_SYS_FSL_DDR_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)

1
board/keymile/Kconfig
View File

@ -114,6 +114,7 @@ config SYS_IVM_EEPROM_PAGE_LEN
Page size of inventory in EEPROM.
source "board/keymile/km83xx/Kconfig"
source "board/keymile/kmcent2/Kconfig"
source "board/keymile/kmp204x/Kconfig"
source "board/keymile/km_arm/Kconfig"

29
board/keymile/common/common.c
View File

@ -41,7 +41,6 @@ DECLARE_GLOBAL_DATA_PTR;
*/
int set_km_env(void)
{
uchar buf[32];
unsigned int pnvramaddr;
unsigned int pram;
unsigned int varaddr;
@ -49,10 +48,9 @@ int set_km_env(void)
char *p;
unsigned long rootfssize = 0;
pnvramaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM
- CONFIG_KM_PNVRAM;
sprintf((char *)buf, "0x%x", pnvramaddr);
env_set("pnvramaddr", (char *)buf);
pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM;
env_set_hex("pnvramaddr", pnvramaddr);
/* try to read rootfssize (ram image) from environment */
p = env_get("rootfssize");
@ -60,16 +58,14 @@ int set_km_env(void)
strict_strtoul(p, 16, &rootfssize);
pram = (rootfssize + CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM +
CONFIG_KM_PNVRAM) / 0x400;
sprintf((char *)buf, "0x%x", pram);
env_set("pram", (char *)buf);
env_set_ulong("pram", pram);
varaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
sprintf((char *)buf, "0x%x", varaddr);
env_set("varaddr", (char *)buf);
varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
env_set_hex("varaddr", varaddr);
kernelmem = gd->ram_size - 0x400 * pram;
sprintf((char *)buf, "0x%x", kernelmem);
env_set("kernelmem", (char *)buf);
env_set_hex("kernelmem", kernelmem);
return 0;
}
@ -243,7 +239,6 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int flag, int argc,
p = env_get("hwkey");
if (p)
rc = strict_strtoul(p, 16, &envhwkey);
if (rc != 0) {
printf("strict_strtoul returns error: %d", rc);
return rc;
@ -305,15 +300,11 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int flag, int argc,
* set the values in environment variables.
*/
if (bid == ivmbid && hwkey == ivmhwkey) {
char buf[10];
found = 1;
envbid = bid;
envhwkey = hwkey;
sprintf(buf, "%lx", bid);
env_set("boardid", buf);
sprintf(buf, "%lx", hwkey);
env_set("hwkey", buf);
env_set_hex("boardid", bid);
env_set_hex("hwkey", hwkey);
}
} /* end while( ! found ) */
}

5
board/keymile/common/common.h
View File

@ -136,6 +136,11 @@ int set_km_env(void);
#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */
#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
void set_sda(int state);
void set_scl(int state);
int get_sda(void);
int get_scl(void);
int i2c_soft_read_pin(void);
int i2c_make_abort(void);
#endif /* __KEYMILE_COMMON_H */

5
board/keymile/common/ivm.c
View File

@ -321,6 +321,11 @@ static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset)
process_mac(valbuf, page2, mac_address_offset, true);
env_set((char *)"eth1addr", (char *)valbuf);
}
if (IS_ENABLED(CONFIG_TARGET_KMCENT2)) {
/* 3rd ethernet interface */
process_mac(valbuf, page2, 2, true);
env_set((char *)"eth4addr", (char *)valbuf);
}
return 0;
}

19
board/keymile/common/qrio.c
View File

@ -5,15 +5,28 @@
*/
#include <common.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include "common.h"
#include "qrio.h"
/* QRIO ID register offset */
#define ID_REV_OFF 0x00
/* QRIO GPIO register offsets */
#define DIRECT_OFF 0x18
#define GPRT_OFF 0x1c
void show_qrio(void)
{
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
printf("QRIO: id = %u, revision = %u\n",
(id_rev >> 8) & 0xff, id_rev & 0xff);
}
int qrio_get_gpio(u8 port_off, u8 gpio_nr)
{
u32 gprt;
@ -129,7 +142,7 @@ void qrio_prst(u8 bit, bool en, bool wden)
void qrio_prstcfg(u8 bit, u8 mode)
{
u32 prstcfg;
unsigned long prstcfg;
u8 i;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
@ -137,9 +150,9 @@ void qrio_prstcfg(u8 bit, u8 mode)
for (i = 0; i < 2; i++) {
if (mode & (1 << i))
set_bit(2 * bit + i, &prstcfg);
__set_bit(2 * bit + i, &prstcfg);
else
clear_bit(2 * bit + i, &prstcfg);
__clear_bit(2 * bit + i, &prstcfg);
}
out_be32(qrio_base + PRSTCFG_OFF, prstcfg);

1
board/keymile/common/qrio.h
View File

@ -11,6 +11,7 @@
#define QRIO_GPIO_A 0x40
#define QRIO_GPIO_B 0x60
void show_qrio(void);
int qrio_get_gpio(u8 port_off, u8 gpio_nr);
void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val);
void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value);

17
board/keymile/kmcent2/Kconfig Normal file
View File

@ -0,0 +1,17 @@
if TARGET_KMCENT2
config SYS_BOARD
default "kmcent2"
config SYS_VENDOR
default "keymile"
config SYS_CONFIG_NAME
default "kmcent2"
config BOARD_SPECIFIC_OPTIONS
def_bool y
select ARCH_T1040
select PHYS_64BIT
endif

8
board/keymile/kmcent2/MAINTAINERS Normal file
View File

@ -0,0 +1,8 @@
KMCENT2 BOARD
M: Niel Fourie <lusus@denx.de>
S: Maintained
F: board/keymile/kmcent2/
F: include/configs/kmcent2.h
F: configs/kmcent2_defconfig
F: arch/powerpc/dts/kmcent2.dts
F: arch/powerpc/dts/kmcent2-u-boot.dtsi

14
board/keymile/kmcent2/Makefile Normal file
View File

@ -0,0 +1,14 @@
# SPDX-License-Identifier: GPL-2.0+
# (C) Copyright 2016 Keymile AG
# Rainer Boschung <rainer.boschung@keymile.com>
#
# Copyright 2013 Freescale Semiconductor, Inc.
#
obj-y += kmcent2.o
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
obj-y += ../common/common.o
obj-y += ../common/ivm.o
obj-y += ../common/qrio.o

88
board/keymile/kmcent2/ddr.c Normal file
View File

@ -0,0 +1,88 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Keymile AG
* Rainer Boschung <rainer.boschung@keymile.com>
*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <asm/fsl_law.h>
#include <asm/mmu.h>
#include <asm/mpc85xx_gpio.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <hwconfig.h>
#include <i2c.h>
#include <init.h>
DECLARE_GLOBAL_DATA_PTR;
#define DQSn_POS(n) (3 - (((n) - 1) % 4)) * 8
#define DQSn_START(n, start) ((start) << DQSn_POS(n))
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
unsigned int ctrl_num)
{
if (ctrl_num > 1) {
printf("Not supported controller number %d\n", ctrl_num);
return;
}
/* 1/2 clk delay between wr command and data strobe */
popts->write_data_delay = 4;
/* clk lauched 1/2 applied cylcle after address command */
popts->clk_adjust = 4;
/* 1T timing: command/address held for only 1 cycle */
popts->twot_en = 0;
popts->threet_en = 0;
/* optimize cpo for erratum A-009942 */
popts->cpo_sample = 0x3b;
/* we have only one module, half str should be OK */
popts->half_strength_driver_enable = 1;
/*
* Write leveling override
*/
/* set for DDR3-1600 */
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
popts->wrlvl_start = 0x7;
/* DQS write leveling start time according layout */
popts->wrlvl_ctl_2 = (DQSn_START(1, 0x06) |
DQSn_START(2, 0x06) |
DQSn_START(3, 0x07) |
DQSn_START(4, 0x07));
popts->wrlvl_ctl_3 = (DQSn_START(5, 0x07) |
DQSn_START(6, 0x08) |
DQSn_START(7, 0x08) |
DQSn_START(8, 0x08));
/*
* rtt and wtt_wr override
*/
popts->rtt_override = 0;
/* Enable ZQ calibration */
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
}
int dram_init(void)
{
phys_size_t dram_size;
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
gd->ram_size = dram_size;
return 0;
}

353
board/keymile/kmcent2/kmcent2.c Normal file
View File

@ -0,0 +1,353 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Keymile AG
* Rainer Boschung <rainer.boschung@keymile.com>
*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <asm/cache.h>
#include <asm/fsl_fdt.h>
#include <asm/fsl_law.h>
#include <asm/fsl_liodn.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_serdes.h>
#include <asm/immap_85xx.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <fdt_support.h>
#include <fm_eth.h>
#include <hwconfig.h>
#include <image.h>
#include <linux/compiler.h>
#include <net.h>
#include <netdev.h>
#include <vsc9953.h>
#include "../common/common.h"
#include "../common/qrio.h"
DECLARE_GLOBAL_DATA_PTR;
static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
int checkboard(void)
{
printf("Board: Hitachi Power Grids %s\n", KM_BOARD_NAME);
return 0;
}
#define RSTRQSR1_WDT_RR 0x00200000
#define RSTRQSR1_SW_RR 0x00100000
int board_early_init_f(void)
{
struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
bool cpuwd_flag = false;
/* board specific IFC configuration: increased bus turnaround time */
setbits_be32(&ifc.gregs->ifc_gcr, 8 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
/* configure mode for uP reset request */
qrio_uprstreq(UPREQ_CORE_RST);
/* board only uses the DDR_MCK0, so disable the DDR_MCK1 */
setbits_be32(&gur->ddrclkdr, 0x40000000);
/* set reset reason according CPU register */
if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
RSTRQSR1_WDT_RR)
cpuwd_flag = true;
qrio_cpuwd_flag(cpuwd_flag);
/* clear CPU bits by writing 1 */
setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
/* configure PRST lines for the application: */
/*
* ETHSW_DDR_RST:
* reset at power-up and unit reset only and enable WD on it
*/
qrio_prstcfg(KM_ETHSW_DDR_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_ETHSW_DDR_RST, true);
/*
* XES_PHY_RST:
* reset at power-up and unit reset only and enable WD on it
*/
qrio_prstcfg(KM_XES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_XES_PHY_RST, true);
/*
* ES_PHY_RST:
* reset at power-up and unit reset only and enable WD on it
*/
qrio_prstcfg(KM_ES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_ES_PHY_RST, true);
/*
* EFE_RST:
* reset at power-up and unit reset only and enable WD on it
*/
qrio_prstcfg(KM_EFE_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_EFE_RST, true);
/*
* BFTIC4_RST:
* reset at power-up and unit reset only and enable WD on it
*/
qrio_prstcfg(KM_BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_BFTIC4_RST, true);
/*
* DPAXE_RST:
* reset at power-up and unit reset only and enable WD on it
*/
qrio_prstcfg(KM_DPAXE_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_DPAXE_RST, true);
/*
* PEXSW_RST:
* reset at power-up and unit reset only, deassert reset w/o WD
*/
qrio_prstcfg(KM_PEXSW_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_prst(KM_PEXSW_RST, false, false);
/*
* PEXSW_NT_RST:
* reset at power-up and unit reset only, deassert reset w/o WD
*/
qrio_prstcfg(KM_PEXSW_NT_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_prst(KM_PEXSW_NT_RST, false, false);
/*
* BOBCAT_RST:
* reset at power-up and unit reset only, deassert reset w/o WD
*/
qrio_prstcfg(KM_BOBCAT_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_prst(KM_BOBCAT_RST, false, false);
/*
* FEMT_RST:
* reset at power-up and unit reset only and enable WD
*/
qrio_prstcfg(KM_FEMT_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_FEMT_RST, true);
/*
* FOAM_RST:
* reset at power-up and unit reset only and enable WD
*/
qrio_prstcfg(KM_FOAM_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_FOAM_RST, true);
return 0;
}
int board_early_init_r(void)
{
int ret = 0;
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
set_liodns();
setup_qbman_portals();
qrio_set_leds();
/* enable Application Buffer */
qrio_enable_app_buffer();
return ret;
}
unsigned long get_serial_clock(unsigned long dummy)
{
return (gd->bus_clk / 2);
}
unsigned long get_board_sys_clk(unsigned long dummy)
{
return 66666666;
}
int misc_init_f(void)
{
/* configure QRIO pis for i2c deblocking */
i2c_deblock_gpio_cfg();
/*
* CFE_RST (front phy):
* reset at power-up, unit and core reset, deasset reset w/o WD
*/
qrio_prstcfg(KM_CFE_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
qrio_prst(KM_CFE_RST, false, false);
/*
* ZL30158_RST (PTP clock generator):
* reset at power-up only, deassert reset and enable WD on it
*/
qrio_prstcfg(KM_ZL30158_RST, PRSTCFG_POWUP_RST);
qrio_prst(KM_ZL30158_RST, false, false);
/*
* ZL30364_RST (EEC generator):
* reset at power-up only, deassert reset and enable WD on it
*/
qrio_prstcfg(KM_ZL30364_RST, PRSTCFG_POWUP_RST);
qrio_prst(KM_ZL30364_RST, false, false);
return 0;
}
#define USED_SRDS_BANK 0
#define EXPECTED_SRDS_RFCK SRDS_PLLCR0_RFCK_SEL_100
#define BRG01_IOCLK12 0x02000000
#define EC2_GTX_CLK125 0x08000000
int misc_init_r(void)
{
serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_MPC85xx_SCFG;
ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* check SERDES bank 0 reference clock */
u32 actual = in_be32(&regs->bank[USED_SRDS_BANK].pllcr0);
if (actual & SRDS_PLLCR0_POFF)
printf("Warning: SERDES bank %u pll is off\n", USED_SRDS_BANK);
if ((actual & SRDS_PLLCR0_RFCK_SEL_MASK) != EXPECTED_SRDS_RFCK) {
printf("Warning: SERDES bank %u expects %sMHz clock, is %sMHz\n",
USED_SRDS_BANK,
serdes_clock_to_string(EXPECTED_SRDS_RFCK),
serdes_clock_to_string(actual));
}
/* QE IO clk : BRG01 is used over clk12 for HDLC clk (20 MhZ) */
out_be32(&scfg->qeioclkcr,
in_be32(&scfg->qeioclkcr) | BRG01_IOCLK12);
ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
/* Fix polarity of Card Detect and Write Protect */
out_be32(&gur->sdhcpcr, 0xFFFFFFFF);
/*
* EC1 is disabled in our design, so we must explicitly set GTXCLKSEL
* to EC2
*/
out_be32(&scfg->emiiocr, in_be32(&scfg->emiiocr) | EC2_GTX_CLK125);
return 0;
}
int hush_init_var(void)
{
ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
return 0;
}
int last_stage_init(void)
{
const char *kmem;
/* DIP switch support on BFTIC */
struct bfticu_iomap *bftic4 =
(struct bfticu_iomap *)SYS_BFTIC_BASE;
u8 dip_switch = in_8((u8 *)&bftic4->mswitch) & BFTICU_DIPSWITCH_MASK;
if (dip_switch != 0) {
/* start bootloader */
puts("DIP: Enabled\n");
env_set("actual_bank", "0");
}
set_km_env();
/*
* bootm_size is used to fixup the FDT memory node
* set it to kernelmem that has the same value
*/
kmem = env_get("kernelmem");
if (kmem)
env_set("bootm_size", kmem);
return 0;
}
void fdt_fixup_fman_mac_addresses(void *blob)
{
int node, ret;
char path[24];
unsigned char mac_addr[6];
/*
* Just the fm1-mac5 must be set by us, u-boot handle the 2 others,
* get the mac addr from env
*/
if (!eth_env_get_enetaddr_by_index("eth", 4, mac_addr)) {
printf("eth4addr env variable not defined\n");
return;
}
/* local management port */
strcpy(path, "/soc/fman/ethernet@e8000");
node = fdt_path_offset(blob, path);
if (node < 0) {
printf("no %s\n", path);
return;
}
ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
if (ret) {
printf("%s\n\terror setting local-mac-address property\n",
path);
}
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = env_get_bootm_low();
size = env_get_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
fdt_fixup_liodn(blob);
fdt_fixup_fman_mac_addresses(blob);
if (hwconfig("qe-tdm"))
fdt_del_diu(blob);
return 0;
}
/* DIC26_SELFTEST GPIO used to start factory test sw */
#define SELFTEST_PORT QRIO_GPIO_A
#define SELFTEST_PIN 0
int post_hotkeys_pressed(void)
{
qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
}

23
board/keymile/kmcent2/law.c Normal file
View File

@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Keymile AG
* Rainer Boschung <rainer.boschung@keymile.com>
*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <config.h>
#include <asm/fsl_law.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC),
/* other application LAW are not used in u-boot */
};
int num_law_entries = ARRAY_SIZE(law_table);

104
board/keymile/kmcent2/tlb.c Normal file
View File

@ -0,0 +1,104 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Keymile AG
* Rainer Boschung <rainer.boschung@keymile.com>
*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <asm/mmu.h>
#include <asm/u-boot.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
CONFIG_SYS_INIT_RAM_ADDR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
0, 2, BOOKE_PAGESZ_128M, 1),
/* *I*G* - PCI1 */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI1 I/O */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 4, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 5, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 8, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 9, BOOKE_PAGESZ_4M, 1),
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
/* QRIO */
SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 11, BOOKE_PAGESZ_64K, 1),
/* MRAM */
SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS,
MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 12, BOOKE_PAGESZ_128M, 1),
/* BFTIC */
SET_TLB_ENTRY(1, SYS_BFTIC_BASE, SYS_BFTIC_BASE_PHYS,
MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 13, BOOKE_PAGESZ_128M, 1),
/*
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so do not use them here!!.
*/
/* PAXE */
SET_TLB_ENTRY(1, CONFIG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS,
MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 16, BOOKE_PAGESZ_128M, 1)
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

2
board/kontron/sl28/Makefile
View File

@ -4,7 +4,7 @@ ifndef CONFIG_SPL_BUILD
obj-y += sl28.o cmds.o
endif
obj-y += common.o ddr.o
obj-y += ddr.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o

10
board/kontron/sl28/common.c
View File

@ -1,10 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
#include <asm/arch-fsl-layerscape/soc.h>
int board_early_init_f(void)
{
fsl_lsch3_early_init_f();
return 0;
}

6
board/kontron/sl28/sl28.c
View File

@ -19,6 +19,12 @@
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
fsl_lsch3_early_init_f();
return 0;
}
int board_init(void)
{
if (CONFIG_IS_ENABLED(FSL_CAAM))

38
board/kontron/sl28/spl.c
View File

@ -3,10 +3,36 @@
#include <common.h>
#include <asm/io.h>
#include <asm/spl.h>
#include <asm/arch-fsl-layerscape/fsl_serdes.h>
#include <asm/arch-fsl-layerscape/soc.h>
#define DCFG_RCWSR25 0x160
#define GPINFO_HW_VARIANT_MASK 0xff
#define SERDES_LNDGCR0 0x1ea08c0
#define LNDGCR0_PROTS_MASK GENMASK(11, 7)
#define LNDGCR0_PROTS_SATA (0x2 << 7)
#define SERDES_LNDGCR1 0x1ea08c4
#define LNDGCR1_RDAT_INV BIT(31)
/*
* On this board the SMARC PCIe lane D might be switched to SATA mode. This
* makes sense if this lane is connected to a Mini PCI slot and a mSATA card
* is plugged in. In this case, the RX pair is swapped and we need to invert
* the received data.
*/
static void fixup_sata_rx_polarity(void)
{
u32 prot = in_le32(SERDES_LNDGCR0) & LNDGCR0_PROTS_MASK;
u32 tmp;
if (prot == LNDGCR0_PROTS_SATA) {
tmp = in_le32(SERDES_LNDGCR1);
tmp |= LNDGCR1_RDAT_INV;
out_le32(SERDES_LNDGCR1, tmp);
}
}
int sl28_variant(void)
{
return in_le32(DCFG_BASE + DCFG_RCWSR25) & GPINFO_HW_VARIANT_MASK;
@ -17,6 +43,10 @@ int board_fit_config_name_match(const char *name)
int variant = sl28_variant();
switch (variant) {
case 1:
return strcmp(name, "fsl-ls1028a-kontron-sl28-var1");
case 2:
return strcmp(name, "fsl-ls1028a-kontron-sl28-var2");
case 3:
return strcmp(name, "fsl-ls1028a-kontron-sl28-var3");
case 4:
@ -30,3 +60,11 @@ void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = BOOT_DEVICE_SPI;
}
int board_early_init_f(void)
{
fixup_sata_rx_polarity();
fsl_lsch3_early_init_f();
return 0;
}

1
configs/T1042D4RDB_NAND_defconfig
View File

@ -84,7 +84,6 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64

1
configs/T1042D4RDB_SDCARD_defconfig
View File

@ -81,7 +81,6 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64

1
configs/T1042D4RDB_SECURE_BOOT_defconfig
View File

@ -57,7 +57,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64

1
configs/T1042D4RDB_SPIFLASH_defconfig
View File

@ -83,7 +83,6 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64

1
configs/T1042D4RDB_defconfig
View File

@ -69,7 +69,6 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64

1
configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
View File

@ -78,7 +78,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64

1
configs/T1042RDB_PI_NAND_defconfig
View File

@ -76,7 +76,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64

1
configs/T1042RDB_PI_SDCARD_defconfig
View File

@ -73,7 +73,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64

1
configs/T1042RDB_PI_SPIFLASH_defconfig
View File

@ -75,7 +75,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64

1
configs/T1042RDB_PI_defconfig
View File

@ -60,7 +60,6 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64

92
configs/kmcent2_defconfig Normal file
View File

@ -0,0 +1,92 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xebf40000
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_KM_IVM_BUS=2
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
CONFIG_DEFAULT_DEVICE_TREE="kmcent2"
CONFIG_MPC85xx=y
CONFIG_TARGET_KMCENT2=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND_TRIMFFS=y
# CONFIG_CMD_SATA is not set
CONFIG_CMD_SPI=y
CONFIG_CMD_PING=y
CONFIG_CMD_ETHSW=y
CONFIG_MP=y
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=ffa000000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:128k(RCW),128k(fman),128k(QE),128k(zarlink),512k(res),62m(ubi0),128k(envred),128k(env),768k(u-boot);ffa000000.flash:-(ubi1);"
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xebf20000
CONFIG_ENV_ADDR_REDUND=0xebf00000
CONFIG_DM=y
# CONFIG_FSL_SATA is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_FMAN_ENET=y
CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCIE_FSL=y
CONFIG_U_QE=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPI_MEM=y
CONFIG_FSL_ESPI=y
CONFIG_WATCHDOG=y
CONFIG_FS_CRAMFS=y
CONFIG_BCH=y
CONFIG_PANIC_HANG=y
CONFIG_LZO=y

2
configs/kontron_sl28_defconfig
View File

@ -62,6 +62,7 @@ CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
@ -73,6 +74,7 @@ CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC=y
CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y

1
configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
View File

@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y

1
configs/ls1012afrwy_qspi_defconfig
View File

@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y

1
configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
View File

@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y

1
configs/ls1012afrwy_tfa_defconfig
View File

@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y

1
configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
View File

@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y

1
configs/ls1012ardb_qspi_defconfig
View File

@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y

1
configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
View File

@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y

1
configs/ls1012ardb_tfa_defconfig
View File

@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y

1
configs/ls1021aqds_ddr4_nor_defconfig
View File

@ -24,6 +24,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y

1
configs/ls1021aqds_ddr4_nor_lpuart_defconfig
View File

@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y

1
configs/ls1021aqds_nand_defconfig
View File

@ -40,6 +40,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y

1
configs/ls1021aqds_nor_SECURE_BOOT_defconfig
View File

@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y

1
configs/ls1021aqds_nor_defconfig
View File

@ -24,6 +24,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y

1
configs/ls1021aqds_nor_lpuart_defconfig
View File

@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y

1
configs/ls1021aqds_qspi_defconfig
View File

@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y

1
configs/ls1021aqds_sdcard_ifc_defconfig
View File

@ -38,6 +38,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y

1
configs/ls1021aqds_sdcard_qspi_defconfig
View File

@ -37,6 +37,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y

1
configs/ls1021atwr_nor_SECURE_BOOT_defconfig
View File

@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y

1
configs/ls1021atwr_nor_defconfig
View File

@ -25,6 +25,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y

1
configs/ls1021atwr_nor_lpuart_defconfig
View File

@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y

1
configs/ls1021atwr_qspi_defconfig
View File

@ -28,6 +28,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y

1
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
View File

@ -41,6 +41,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y

1
configs/ls1021atwr_sdcard_ifc_defconfig
View File

@ -40,6 +40,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y

1
configs/ls1021atwr_sdcard_qspi_defconfig
View File

@ -39,6 +39,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y

1
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
View File

@ -26,6 +26,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y

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