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Small fixes in several i.MX boards

Browse Source 
----------------------------------
 
 - imx8: add pinctrl driveri (mx8m), fix documentation and
   fix reported CPU frequency. Fabio is co-maintainer
 - pico-imx6ul: switch to DM
 - local fixes for ventana, mx6ul_14x14_evk, engicam,
   imx6(q)_logic, liteboard
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Merge tag 'u-boot-imx-20190313' of git://git.denx.de/u-boot-imx

Small fixes in several i.MX boards
----------------------------------

- imx8: add pinctrl driveri (mx8m), fix documentation and
  fix reported CPU frequency. Fabio is co-maintainer
- pico-imx6ul: switch to DM
- local fixes for ventana, mx6ul_14x14_evk, engicam,
  imx6(q)_logic, liteboard
This commit is contained in:
Tom Rini 2019-03-13 16:07:41 -04:00
commit a0d12cd239
40 changed files with 994 additions and 265 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/dts/imx6qdl-u-boot.dtsi
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@ -9,6 +9,9 @@
aips-bus@2000000 {
u-boot,dm-spl;
spba-bus@2000000 {
u-boot,dm-spl;
};
};
aips-bus@2100000 {

100
arch/arm/dts/imx6ul-pico-hobbit.dts Normal file
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@ -0,0 +1,100 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2015 Technexion Ltd.
//
// Author: Wig Cheng <wig.cheng@technexion.com>
// Richard Hu <richard.hu@technexion.com>
// Tapani Utriainen <tapani@technexion.com>
/dts-v1/;
#include "imx6ul-pico.dtsi"
/ {
model = "TechNexion PICO-IMX6UL and HOBBIT baseboard";
compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul";
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led {
label = "gpio-led";
gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
};
};
sound {
compatible = "fsl,imx-audio-sgtl5000";
model = "imx6ul-sgtl5000";
audio-cpu = <&sai1>;
audio-codec = <&sgtl5000>;
audio-routing =
"LINE_IN", "Line In Jack",
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
};
sys_mclk: clock-sys-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
};
&i2c2 {
clock_frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
sgtl5000: codec@a {
reg = <0x0a>;
compatible = "fsl,sgtl5000";
clocks = <&sys_mclk>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
};
&i2c3 {
status = "okay";
polytouch: touchscreen@38 {
compatible = "edt,edt-ft5x06";
reg = <0x38>;
interrupt-parent = <&gpio1>;
interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
};
adc081c: adc@50 {
compatible = "ti,adc081c";
reg = <0x50>;
vref-supply = <&reg_3p3v>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0
MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0
MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0
MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x10b0
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x10b0
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x10b0
>;
};
};

97
arch/arm/dts/imx6ul-pico-pi.dts Normal file
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@ -0,0 +1,97 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2015 Technexion Ltd.
//
// Author: Wig Cheng <wig.cheng@technexion.com>
// Richard Hu <richard.hu@technexion.com>
// Tapani Utriainen <tapani@technexion.com>
/dts-v1/;
#include "imx6ul-pico.dtsi"
/ {
model = "TechNexion PICO-IMX6UL and PI baseboard";
compatible = "technexion,imx6ul-pico-pi", "fsl,imx6ul";
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led {
label = "gpio-led";
gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
};
};
sound {
compatible = "fsl,imx-audio-sgtl5000";
model = "imx6ul-sgtl5000";
audio-cpu = <&sai1>;
audio-codec = <&sgtl5000>;
audio-routing =
"LINE_IN", "Line In Jack",
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
};
sys_mclk: clock-sys-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
};
&i2c2 {
clock_frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
sgtl5000: codec@a {
reg = <0x0a>;
compatible = "fsl,sgtl5000";
clocks = <&sys_mclk>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
};
&i2c3 {
clock_frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
polytouch: touchscreen@38 {
compatible = "edt,edt-ft5x06";
reg = <0x38>;
interrupt-parent = <&gpio1>;
interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0
MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0
MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0
MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x10b0
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x10b0
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0
>;
};
};

461
arch/arm/dts/imx6ul-pico.dtsi Normal file
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@ -0,0 +1,461 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2015 Technexion Ltd.
//
// Author: Wig Cheng <wig.cheng@technexion.com>
// Richard Hu <richard.hu@technexion.com>
// Tapani Utriainen <tapani@technexion.com>
/dts-v1/;
#include "imx6ul.dtsi"
/ {
/* Will be filled by the bootloader */
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0>;
};
chosen {
stdout-path = &uart6;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
status = "okay";
};
reg_2p5v: regulator-2p5v {
compatible = "regulator-fixed";
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_sd1_vmmc: regulator-sd1-vmmc {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 6 0>;
};
reg_brcm: regulator-brcm {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_brcm_reg>;
regulator-name = "brcm_reg";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <200000>;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&clks {
assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <786432000>;
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
max-speed = <100>;
interrupt-parent = <&gpio5>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze3000@8 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
regulators {
/* VDD_ARM_SOC_IN*/
sw1b_reg: sw1b {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1475000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
/* DRAM */
sw3a_reg: sw3 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
regulator-always-on;
};
/* DRAM */
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
};
};
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
display = <&display0>;
status = "okay";
display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33200000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <210>;
hback-porch = <46>;
hsync-len = <1>;
vback-porch = <22>;
vfront-porch = <23>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
status = "okay";
};
&pwm8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
status = "okay";
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
status = "okay";
};
&uart6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart6>;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1_id>;
dr_mode = "otg";
disable-over-current;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
no-1-8-v;
non-removable;
keep-power-in-suspend;
status = "okay";
};
&usdhc2 { /* Wifi SDIO */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
no-1-8-v;
non-removable;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_brcm>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
pinctrl_brcm_reg: brcmreggrp {
fsl,pins = <
MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */
MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0
MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0
MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0
>;
};
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
>;
};
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
/* LCD reset */
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0
>;
};
pinctrl_pwm7: pwm7grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0
>;
};
pinctrl_pwm8: pwm8grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0
MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0
MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0
MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1
MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1
MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
>;
};
pinctrl_uart6: uart6grp {
fsl,pins = <
MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
>;
};
pinctrl_usb_otg1: usbotg1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0
>;
};
pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029
MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
>;
};
};

26
arch/arm/mach-imx/imx8/cpu.c
View File

@ -616,26 +616,32 @@ static const struct udevice_id cpu_imx8_ids[] = {
{ }
};
static ulong imx8_get_cpu_rate(void)
{
ulong rate;
int ret;
ret = sc_pm_get_clock_rate(-1, SC_R_A35, SC_PM_CLK_CPU,
(sc_pm_clock_rate_t *)&rate);
if (ret) {
printf("Could not read CPU frequency: %d\n", ret);
return 0;
}
return rate;
}
static int imx8_cpu_probe(struct udevice *dev)
{
struct cpu_imx_platdata *plat = dev_get_platdata(dev);
struct clk cpu_clk;
u32 cpurev;
int ret;
cpurev = get_cpu_rev();
plat->cpurev = cpurev;
plat->name = get_core_name();
plat->rev = get_imx8_rev(cpurev & 0xFFF);
plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);
ret = clk_get_by_index(dev, 0, &cpu_clk);
if (ret) {
debug("%s: Failed to get CPU clk: %d\n", __func__, ret);
return 0;
}
plat->freq_mhz = clk_get_rate(&cpu_clk) / 1000000;
plat->freq_mhz = imx8_get_cpu_rate() / 1000000;
return 0;
}

2
arch/arm/mach-imx/mx6/Kconfig
View File

@ -403,7 +403,9 @@ config TARGET_OT1200
config TARGET_PICO_IMX6UL
bool "PICO-IMX6UL-EMMC"
select MX6UL
select DM
select SUPPORT_SPL
imply CMD_DM
config TARGET_LITEBOARD
bool "Grinn liteBoard (i.MX6UL)"

161
board/boundary/nitrogen6x/README.mx6qsabrelite
View File

@ -1,63 +1,11 @@
U-Boot for the Freescale i.MX6q SabreLite board
===============================================
This file contains information for the port of U-Boot to the Freescale
i.MX6q SabreLite board.
1. Boot source, boot from SD card
---------------------------------
The recent mainline U-Boot for the Freescale i.MX6q SabreLite board supports
boot from SD card only. However, by default, the SabreLite
boards boot from the SPI NOR flash. These boards need to be reflashed with
a small SD card loader to support boot from SD card. This small SD card loader
will be flashed into the SPI NOR. The board will still boot from SPI NOR, but
the loader will in turn request the BootROM to load the U-Boot from SD card.
The SD card loader is available from
https://wiki.linaro.org/Boards/MX6QSabreLite
under a open-source 3-clause BSD license.
To update the SPI-NOR on the SabreLite board without the Freescale
manufacturing tool use the following procedure:
1. Write this SD card loader onto a large SD card using:
sudo dd if=iMX6DQ_SPI_to_uSDHC3.bin of=/dev/sXx
Note: Replace sXx with the device representing the SD card in your system.
Note: This writes SD card loader at address 0
2. Put this SD card into the slot for the large SD card (SD3 on the bottom of
the board). Make sure SW1 switch is at position "00", so that it can boot
from the fuses.
3. Power-up the SabreLite, press 'space' to enter command mode in the U-Boot
(the default one the board is shipped with, starting from the SPI NOR) and
enter the following commands:
MX6Q SABRELITE U-Boot > mmc dev 0
MX6Q SABRELITE U-Boot > mmc read 0x10800000 0 200
MX6Q SABRELITE U-Boot > sf probe
MX6Q SABRELITE U-Boot > sf erase 0 0x40000
MX6Q SABRELITE U-Boot > sf write 0x10800000 0 0x40000
4. done.
In case you somehow do not succeed with this procedure you will have to use
the Freescale manufacturing tool in order to reflash the SPI-NOR.
Note: The board now boots from full size SD3 on the bottom of the board. NOT
the micro SD4/BOOT slot on the top of the board. I.e. you have to use
full size SD cards.
This information is taken from
https://wiki.linaro.org/Boards/MX6QSabreLite
2. Build
1. Build
--------
To build U-Boot for the SabreLite board:
@ -65,8 +13,107 @@ To build U-Boot for the SabreLite board:
make mx6qsabrelite_config
make
To copy the resulting u-boot.imx to the SD card:
sudo dd if=u-boot.imx of=/dev/sXx bs=512 seek=2&&sudo sync
2. Boot from SD card
--------------------
The SabreLite boards boot from the SPI NOR flash. These boards need their SPI
to be reflashed with a small SD card loader to support boot from SD card. The
board will still boot from SPI NOR, but the loader will in turn request the
BootROM to load the U-Boot from SD card.
The SD card loader is available from
https://wiki.linaro.org/Boards/MX6QSabreLite
This is provided under a open-source 3-clause BSD license.
To following procedure can be used to update the SPI-NOR on the SabreLite
board:
1. Write this SD card loader onto a large SD card using:
sudo dd if=iMX6DQ_SPI_to_uSDHC3.bin of=/dev/sXx
Note: Replace sXx with the device representing the SD card in your system.
Note: This writes SD card loader at address 0
2. Put this SD card into the slot for the large SD card (SD3 on the bottom of
the board). Make sure SW1 switch is at position "00", so that it can boot
from the fuses.
3. Power-up the SabreLite, press 'space' to enter command mode in the U-Boot
(the default one the board is shipped with, starting from the SPI NOR) and
enter the following commands:
MX6Q SABRELITE U-Boot > mmc dev 0
MX6Q SABRELITE U-Boot > mmc read 0x10800000 0 200
MX6Q SABRELITE U-Boot > sf probe
MX6Q SABRELITE U-Boot > sf erase 0 0x40000
MX6Q SABRELITE U-Boot > sf write 0x10800000 0 0x40000
4. Write the u-boot.imx produced during the U-Boot build to the SD card:
sudo dd if=u-boot.imx of=/dev/sXx bs=512 seek=2 && sudo sync
Note: Replace sXx with the device representing the SD card in your system.
5. Re-insert the SD card back in the slot for the large SD card and power-cycle
the board.
Note: The board now boots from full size SD3 on the bottom of the board. NOT
the micro SD4/BOOT slot on the top of the board. I.e. you have to use
full size SD cards.
This information originally taken from:
https://wiki.linaro.org/Boards/MX6QSabreLite
3. Boot from SPI NOR
--------------------
The SabreLite board can also boot U-Boot directly from the SPI NOR flash:
1. Power-up the SabreLite, press 'space' to enter command mode in the U-Boot
and enter the following commands:
=> mmc dev 0
=> mmc read 0x10800000 0x400 0x80000
=> sf probe 0
=> sf erase 0 0xc0000
=> sf write 0x10800000 0x400 0x80000
Note: This procedure assumes you have booted using the desired U-Boot from an
SD card as prepared in the previous section. Alternative mechanisms, such
as using tftpboot to copy an alternative U-Boot image into memory can
also be used.
4. Recovering SPI-NOR
---------------------
In case you somehow do not succeed with this procedure you can upload U-Boot
via USB:
1. Download and install the imx_loader following the instructions provided:
https://github.com/boundarydevices/imx_usb_loader
2. Connect the board to USB via the USB OTG port.
3. Make sure SW1 switch is at position "01", so that it can boot from USB OTG.
4. Power-up the SabreLite and run the imx_loader to upload the U-Boot image:
sudo imx_usb u-boot.imx
Note: This will upload and run the U-Boot image in memory, the SPI will not be
reprogrammed and this procedure will need to be repeated if the board is
reset.
5. Use one of previous descriptions to re-flash the SPI-NOR as required.
6. Ensure SW1 is returned to "00" to boot from the fuses once done.
Note: Replace sXx with the device representing the SD card in your system.

5
board/engicam/common/board.c
View File

@ -8,6 +8,7 @@
#include <common.h>
#include <mmc.h>
#include <asm/arch/sys_proto.h>
#include <watchdog.h>
#include "board.h"
@ -88,6 +89,10 @@ int board_late_init(void)
setenv_fdt_file();
#ifdef CONFIG_HW_WATCHDOG
hw_watchdog_init();
#endif
return 0;
}

1
board/freescale/imx8mq_evk/MAINTAINERS
View File

@ -1,5 +1,6 @@
i.MX8MQ EVK BOARD
M: Peng Fan <peng.fan@nxp.com>
M: Fabio Estevam <festevam@gmail.com>
S: Maintained
F: board/freescale/imx8mq_evk/
F: include/configs/imx8mq_evk.h

3
board/freescale/imx8mq_evk/README
View File

@ -18,8 +18,9 @@ Get the ddr and hdmi firmware
Note: srctree is U-Boot source directory
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
$ chmod +x firmware-imx-7.9.bin
$ ./firmware-imx-7.9.bin
$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(srctree)
$ cp firmware-imx-7.9/firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctee)
$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctee)
Build U-Boot
====================

12
board/freescale/mx6sabreauto/README
View File

@ -9,15 +9,15 @@ $ make mx6sabreauto_defconfig
$ make
This will generate the SPL and u-boot.img binaries.
This will generate the SPL and u-boot-dtb.img binaries.
- Flash the SPL binary into the SD card:
$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
- Flash the u-boot.img binary into the SD card:
- Flash the u-boot-dtb.img binary into the SD card:
$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync
$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 && sync
Booting via Falcon mode
-----------------------
@ -32,15 +32,15 @@ $ make mx6sabreauto_defconfig
$ make
This will generate the SPL image called SPL and the u-boot.img.
This will generate the SPL image called SPL and the u-boot-dtb.img.
- Flash the SPL image into the SD card:
$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync
- Flash the u-boot.img image into the SD card:
- Flash the u-boot-dtb.img image into the SD card:
$ sudo dd if=u-boot.img of=/dev/sdb bs=1K seek=69 && sync
$ sudo dd if=u-boot-dtb.img of=/dev/sdb bs=1K seek=69 && sync
Create a FAT16 boot partition to store uImage and the dtb file, then copy the files there:

18
board/freescale/mx6sabresd/README
View File

@ -21,15 +21,15 @@ $ make mx6sabresd_defconfig
$ make
This will generate the SPL and u-boot.img binaries.
This will generate the SPL and u-boot-dtb.img binaries.
- Flash the SPL binary into the SD card:
$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
- Flash the u-boot.img binary into the SD card:
- Flash the u-boot-dtb.img binary into the SD card:
$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync
$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 && sync
2. Booting from eMMC
@ -39,7 +39,7 @@ $ make mx6sabresd_defconfig
$ make
This will generate the SPL and u-boot.img binaries.
This will generate the SPL and u-boot-dtb.img binaries.
- Boot first from SD card as shown in the previous section
@ -51,10 +51,10 @@ Mount the eMMC in the host PC:
=> ums 0 mmc 2
- Flash SPL and u-boot.img binaries into the eMMC:
- Flash SPL and u-boot-dtb.img binaries into the eMMC:
$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync
$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 && sync
Set SW6 to eMMC 8-bit boot: 11010110
@ -65,15 +65,15 @@ Set SW6 to eMMC 8-bit boot: 11010110
$ make mx6sabresd_defconfig
$ make
This will generate the SPL image called SPL and the u-boot.img.
This will generate the SPL image called SPL and the u-boot-dtb.img.
- Flash the SPL image into the SD card:
$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 oflag=sync status=none && sync
- Flash the u-boot.img image into the SD card:
- Flash the u-boot-dtb.img image into the SD card:
$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 oflag=sync status=none && sync
$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 oflag=sync status=none && sync
Create a partition for root file system and extract it there:

9
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
View File

@ -86,16 +86,13 @@ int power_init_board(void)
pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
/* SW1B step ramp up time from 2us to 4us/25mV */
reg = 0x40;
pmic_reg_write(dev, PFUZE3000_SW1BCONF, reg);
pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
/* SW1B mode to APS/PFM */
reg = 0xc;
pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
/* SW1B standby voltage set to 0.975V */
reg = 0xb;
pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
return 0;
}

10
board/gateworks/gw_ventana/eeprom.c
View File

@ -6,6 +6,7 @@
#include <common.h>
#include <errno.h>
#include <hexdump.h>
#include <i2c.h>
#include <malloc.h>
#include <asm/bitops.h>
@ -46,6 +47,8 @@ read_eeprom(int bus, struct ventana_board_info *info)
/* sanity checks */
if (info->model[0] != 'G' || info->model[1] != 'W') {
puts("EEPROM: Invalid Model in EEPROM\n");
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf,
sizeof(*info));
return GW_UNKNOWN;
}
@ -55,6 +58,8 @@ read_eeprom(int bus, struct ventana_board_info *info)
if ((info->chksum[0] != chksum>>8) ||
(info->chksum[1] != (chksum&0xff))) {
puts("EEPROM: Failed EEPROM checksum\n");
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf,
sizeof(*info));
return GW_UNKNOWN;
}
@ -116,6 +121,11 @@ read_eeprom(int bus, struct ventana_board_info *info)
else if (info->model[4] == '0' && info->model[5] == '9')
type = GW5909;
break;
default:
printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf,
sizeof(*info));
break;
}
return type;
}

5
board/gateworks/gw_ventana/gw_ventana_spl.c
View File

@ -540,6 +540,11 @@ static void spl_dram_init(int width, int size_mb, int board_model)
else
calib = &mx6sdl_256x16_mmdc_calib;
debug("4gB density\n");
} else if (width == 16 && size_mb == 1024) {
mem = &mt41k512m16ha_125;
if (is_cpu_type(MXC_CPU_MX6Q))
calib = &mx6dq_512x32_mmdc_calib;
debug("8gB density\n");
} else if (width == 32 && size_mb == 256) {
/* Same calib as width==16, size==128 */
mem = &mt41k64m16jt_125;

36
board/grinn/liteboard/board.c
View File

@ -24,8 +24,6 @@
#include <mmc.h>
#include <netdev.h>
#include <spl.h>
#include <usb.h>
#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR;
@ -63,26 +61,6 @@ static iomux_v3_cfg_t const sd_pads[] = {
MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#ifdef CONFIG_FEC_MXC
static iomux_v3_cfg_t const fec1_pads[] = {
MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static void setup_iomux_fec(void)
{
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
}
#endif
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
@ -180,13 +158,6 @@ void board_late_mmc_init(void)
#endif
#ifdef CONFIG_FEC_MXC
int board_eth_init(bd_t *bis)
{
setup_iomux_fec();
return fecmxc_initialize(bis);
}
static int setup_fec(void)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
@ -207,13 +178,6 @@ static int setup_fec(void)
}
#endif
#ifdef CONFIG_USB_EHCI_MX6
int board_usb_phy_mode(int port)
{
return USB_INIT_HOST;
}
#endif
int board_early_init_f(void)
{
setup_iomux_uart();

14
board/technexion/pico-imx6ul/README
View File

@ -13,7 +13,7 @@ $ make mrproper
$ make pico-imx6ul_defconfig
$ make
This generates the SPL and u-boot.img binaries.
This generates the SPL and u-boot-dtb.img binaries.
1. Loading U-Boot via USB Serial Download Protocol
@ -31,15 +31,15 @@ Connect a USB cable between the OTG pico port and the host PC.
Open a terminal program such as minicom.
Copy SPL and u-boot.img to the imx_usb_loader folder.
Copy SPL and u-boot-dtb.img to the imx_usb_loader folder.
Load the SPL binary via USB:
$ sudo ./imx_usb SPL
Load the u-boot.img binary via USB:
Load the u-boot-dtb.img binary via USB:
$ sudo ./imx_usb u-boot.img
$ sudo ./imx_usb u-boot-dtb.img
Then U-Boot starts and its messages appear in the console program.
@ -54,11 +54,11 @@ Run the DFU agent so we can flash the new images using dfu-util tool:
=> dfu 0 mmc 0
Flash SPL and u-boot.img into the eMMC running the following commands on a PC:
Flash SPL and u-boot-dtb.img into the eMMC running the following commands on a PC:
$ sudo dfu-util -D SPL -a spl
$ sudo dfu-util -D u-boot.img -a u-boot
$ sudo dfu-util -D u-boot-dtb.img -a u-boot
Remove power from the pico board.
@ -142,7 +142,7 @@ Launch UMS:
Flash the new binaries:
$ sudo dd if=SPL of=/dev/sdX bs=1k seek=1; sync
$ sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=69; sync
$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1k seek=69; sync
And then SPL binary will load and jump directly to the kernel:

96
board/technexion/pico-imx6ul/pico-imx6ul.c
View File

@ -13,13 +13,10 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <miiphy.h>
#include <netdev.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include <linux/sizes.h>
#include <usb.h>
#include <power/pmic.h>
@ -32,15 +29,6 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE)
#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@ -56,23 +44,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define RMII_PHY_RESET IMX_GPIO_NR(1, 28)
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C2 for PMIC */
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
.gp = IMX_GPIO_NR(1, 2),
},
.sda = {
.i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3),
},
};
#endif
static iomux_v3_cfg_t const fec_pads[] = {
MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
@ -96,6 +67,7 @@ int board_eth_init(bd_t *bis)
{
setup_iomux_fec();
gpio_request(RMII_PHY_RESET, "enet_phy_reset");
gpio_direction_output(RMII_PHY_RESET, 0);
/*
* According to KSZ8081MNX-RNB manual:
@ -155,19 +127,6 @@ static iomux_v3_cfg_t const uart6_pads[] = {
MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
@ -185,22 +144,6 @@ static void setup_usb(void)
imx_iomux_v3_setup_multiple_pads(usb_otg_pad, ARRAY_SIZE(usb_otg_pad));
}
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
{USDHC1_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
{
return 1;
}
int board_mmc_init(bd_t *bis)
{
imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
int board_early_init_f(void)
{
setup_iomux_uart();
@ -208,38 +151,33 @@ int board_early_init_f(void)
return 0;
}
#ifdef CONFIG_POWER
#define I2C_PMIC 0
static struct pmic *pfuze;
#ifdef CONFIG_DM_PMIC
int power_init_board(void)
{
int ret;
unsigned int reg, rev_id;
struct udevice *dev;
int ret, dev_id, rev_id;
ret = power_pfuze3000_init(I2C_PMIC);
if (ret)
ret = pmic_get("pfuze3000", &dev);
if (ret == -ENODEV)
return 0;
if (ret != 0)
return ret;
pfuze = pmic_get("PFUZE3000");
ret = pmic_probe(pfuze);
if (ret)
return ret;
pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
/* disable Low Power Mode during standby mode */
pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1);
pmic_reg_write(dev, PFUZE3000_LDOGCTL, 0x1);
/* SW1B step ramp up time from 2us to 4us/25mV */
pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, 0x40);
pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
/* SW1B mode to APS/PFM */
pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, 0xc);
pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
/* SW1B standby voltage set to 0.975V */
pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, 0xb);
pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
return 0;
}
@ -274,10 +212,6 @@ int board_init(void)
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_SYS_I2C_MXC
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
#endif
setup_fec();
setup_usb();

12
board/warp7/README
View File

@ -17,7 +17,7 @@ $ make mrproper
$ make warp7_config
$ make
This will generate the U-Boot binary called u-boot.imx.
This will generate the U-Boot binary called u-boot-dtb.imx.
Put warp7 board in USB download mode:
@ -28,11 +28,11 @@ Connect a USB to serial adapter between the host PC and warp7
Connect a USB cable between the OTG warp7 port and the host PC
Copy u-boot.imx to the imx_usb_loader folder.
Copy u-boot-dtb.imx to the imx_usb_loader folder.
Load u-boot.imx via USB:
Load u-boot-dtb.imx via USB:
$ sudo ./imx_usb u-boot.imx
$ sudo ./imx_usb u-boot-dtb.imx
Then U-Boot should start and its messages will appear in the console program.
@ -46,9 +46,9 @@ Use the default environment variables:
Run the DFU command:
=> dfu 0 mmc 0
Transfer u-boot.imx that will be flashed into the eMMC:
Transfer u-boot-dtb.imx that will be flashed into the eMMC:
$ sudo dfu-util -D u-boot.imx -a boot
$ sudo dfu-util -D u-boot-dtb.imx -a boot
Then on the U-Boot prompt the following message should be seen after a
successful upgrade:

6
board/warp7/warp7.c
View File

@ -11,12 +11,8 @@
#include <asm/gpio.h>
#include <asm/mach-imx/hab.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include <mmc.h>
#include <asm/arch/crm_regs.h>
#include <usb.h>
#include <netdev.h>
@ -81,7 +77,7 @@ int power_init_board(void)
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
/* disable Low Power Mode during standby mode */
pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
pmic_reg_write(dev, PFUZE3000_LDOGCTL, 1);
return 0;
}

1
configs/gwventana_emmc_defconfig
View File

@ -85,5 +85,6 @@ CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_HEXDUMP=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y

1
configs/gwventana_gw5904_defconfig
View File

@ -89,5 +89,6 @@ CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_HEXDUMP=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y

1
configs/gwventana_nand_defconfig
View File

@ -88,5 +88,6 @@ CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_HEXDUMP=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y

3
configs/imx6q_logic_defconfig
View File

@ -39,6 +39,7 @@ CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
@ -58,8 +59,10 @@ CONFIG_PCF8575_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_NAND_MXS_DT=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_FEC_MXC=y

7
configs/imx6qdl_icore_mmc_defconfig
View File

@ -12,6 +12,13 @@ CONFIG_DEBUG_UART_BASE=0x021f0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_CMD_BOOTCOUNT=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000
CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
CONFIG_IMX_WATCHDOG=y
CONFIG_DEBUG_UART=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y

2
configs/imx8mq_evk_defconfig
View File

@ -22,6 +22,7 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
@ -29,6 +30,7 @@ CONFIG_SYS_I2C_MXC=y
CONFIG_DM_MMC=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y

12
configs/liteboard_defconfig
View File

@ -30,10 +30,20 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-liteboard"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y

15
configs/pico-hobbit-imx6ul_defconfig
View File

@ -17,7 +17,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_SDP_SUPPORT=y
@ -33,6 +32,8 @@ CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-hobbit"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DFU_MMC=y
CONFIG_USB_FUNCTION_FASTBOOT=y
@ -40,14 +41,24 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_OF_LIBFDT=y

15
configs/pico-imx6ul_defconfig
View File

@ -17,7 +17,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="ask"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_SDP_SUPPORT=y
@ -35,6 +34,8 @@ CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-hobbit"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DFU_MMC=y
CONFIG_USB_FUNCTION_FASTBOOT=y
@ -42,14 +43,24 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_OF_LIBFDT=y

15
configs/pico-pi-imx6ul_defconfig
View File

@ -17,7 +17,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-pi.dtb"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_SDP_SUPPORT=y
@ -33,6 +32,8 @@ CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-pico-pi"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DFU_MMC=y
CONFIG_USB_FUNCTION_FASTBOOT=y
@ -40,14 +41,24 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_OF_LIBFDT=y

17
drivers/mtd/nand/raw/mxs_nand_spl.c
View File

@ -174,11 +174,11 @@ static int is_badblock(struct mtd_info *mtd, loff_t offs, int allowbbt)
}
/* setup mtd and nand structs and init mxs_nand driver */
static int mxs_nand_init(void)
void nand_init(void)
{
/* return if already initalized */
if (nand_chip.numchips)
return 0;
return;
/* init mxs nand driver */
mxs_nand_init_spl(&nand_chip);
@ -191,7 +191,8 @@ static int mxs_nand_init(void)
/* identify flash device */
if (mxs_flash_ident(mtd)) {
printf("Failed to identify\n");
return -1;
nand_chip.numchips = 0; /* If fail, don't use nand */
return;
}
/* allocate and initialize buffers */
@ -202,8 +203,6 @@ static int mxs_nand_init(void)
mtd->size = nand_chip.chipsize;
nand_chip.scan_bbt(mtd);
mxs_nand_setup_ecc(mtd);
return 0;
}
int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf)
@ -213,9 +212,9 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf)
unsigned int nand_page_per_block;
unsigned int sz = 0;
if (mxs_nand_init())
return -ENODEV;
chip = mtd_to_nand(mtd);
if (!chip->numchips)
return -ENODEV;
page = offs >> chip->page_shift;
nand_page_per_block = mtd->erasesize / mtd->writesize;
@ -256,10 +255,6 @@ int nand_default_bbt(struct mtd_info *mtd)
return 0;
}
void nand_init(void)
{
}
void nand_deselect(void)
{
}

10
drivers/net/fec_mxc.c
View File

@ -1284,22 +1284,16 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
{
struct phy_device *phydev;
int addr;
int mask = 0xffffffff;
addr = device_get_phy_addr(dev);
if (addr >= 0)
mask = 1 << addr;
#ifdef CONFIG_FEC_MXC_PHYADDR
mask = 1 << CONFIG_FEC_MXC_PHYADDR;
addr = CONFIG_FEC_MXC_PHYADDR;
#endif
phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
phydev = phy_connect(priv->bus, addr, dev, priv->interface);
if (!phydev)
return -ENODEV;
phy_connect_dev(phydev, dev);
priv->phydev = phydev;
phy_config(phydev);

14
drivers/pinctrl/nxp/Kconfig
View File

@ -75,6 +75,20 @@ config PINCTRL_IMX8
only parses the 'fsl,pins' property and configures related
registers.
config PINCTRL_IMX8M
bool "IMX8M pinctrl driver"
depends on ARCH_IMX8M && PINCTRL_FULL
select DEVRES
select PINCTRL_IMX
help
Say Y here to enable the imx8m pinctrl driver
This provides a simple pinctrl driver for i.MX8M SoC familiy.
This feature depends on device tree configuration. This driver
is different from the linux one, this is a simple implementation,
only parses the 'fsl,pins' property and configure related
registers.
config PINCTRL_VYBRID
bool "Vybrid (vf610) pinctrl driver"
depends on ARCH_VF610 && PINCTRL_FULL

1
drivers/pinctrl/nxp/Makefile
View File

@ -5,4 +5,5 @@ obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o
obj-$(CONFIG_PINCTRL_IMX8M) += pinctrl-imx8m.o
obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o

36
drivers/pinctrl/nxp/pinctrl-imx8m.c Normal file
View File

@ -0,0 +1,36 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*/
#include <dm/device.h>
#include <dm/pinctrl.h>
#include "pinctrl-imx.h"
static struct imx_pinctrl_soc_info imx8mq_pinctrl_soc_info;
static int imx8mq_pinctrl_probe(struct udevice *dev)
{
struct imx_pinctrl_soc_info *info =
(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
return imx_pinctrl_probe(dev, info);
}
static const struct udevice_id imx8m_pinctrl_match[] = {
{ .compatible = "fsl,imx8mq-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info },
{ .compatible = "fsl,imx8mm-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info },
{ /* sentinel */ }
};
U_BOOT_DRIVER(imx8mq_pinctrl) = {
.name = "imx8mq-pinctrl",
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(imx8m_pinctrl_match),
.probe = imx8mq_pinctrl_probe,
.remove = imx_pinctrl_remove,
.priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
.ops = &imx_pinctrl_ops,
.flags = DM_FLAG_PRE_RELOC,
};

4
drivers/serial/serial_mxc.c
View File

@ -178,7 +178,7 @@ static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk,
writel(UCR1_UARTEN, &base->cr1);
}
#ifndef CONFIG_DM_SERIAL
#if !CONFIG_IS_ENABLED(DM_SERIAL)
#ifndef CONFIG_MXC_UART_BASE
#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
@ -260,7 +260,7 @@ __weak struct serial_device *default_serial_console(void)
}
#endif
#ifdef CONFIG_DM_SERIAL
#if CONFIG_IS_ENABLED(DM_SERIAL)
int mxc_serial_setbrg(struct udevice *dev, int baudrate)
{

11
include/configs/imx6-engicam.h
View File

@ -43,19 +43,30 @@
"fdt_addr=" FDT_ADDR "\0" \
"boot_fdt=try\0" \
"mmcpart=1\0" \
"recovery_device=0\0" \
"recovery_part=2\0" \
"recovery_root=/dev/mmcblk0p2 rootwait rw\0" \
"nandroot=ubi0:rootfs rootfstype=ubifs\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"recovery_mmcargs= setenv bootargs console=${console},${baudrate} "\
"root=${recovery_root}\0" \
"ubiargs=setenv bootargs console=${console},${baudrate} " \
"ubi.mtd=5 root=${nandroot} ${mtdparts}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"recovery_loadimage=ext2load mmc ${recovery_device}:${recovery_part} ${loadaddr} ${image}\0" \
"recovery_loadfdt=ext2load mmc ${recovery_device}:${recovery_part} ${fdt_addr} ${fdt_file}\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"loadfit=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${fit_image}\0" \
"altbootcmd=run recovery_boot\0"\
"recovery_boot=echo Recovery Boot from mmc ...; " \
"run recovery_loadimage ; run recovery_loadfdt; run recovery_mmcargs; "\
"bootm ${loadaddr} - ${fdt_addr}\0" \
"fitboot=echo Booting FIT image from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \

8
include/configs/imx6_logic.h
View File

@ -68,8 +68,8 @@
"nandboot=echo Booting from nand ...; " \
" run nandargs;" \
" nand read ${loadaddr} kernel ${kernelsize};" \
" nand read ${fdt_addr} dtb;" \
" bootz ${loadaddr} - ${fdt_addr}\0" \
" nand read ${fdt_addr_r} dtb;" \
" bootz ${loadaddr} - ${fdt_addr_r}\0" \
"nandramboot=echo Booting RAMdisk from nand ...; " \
" nand read ${ramdisk_addr_r} fs ${ramdisksize};" \
" nand read ${loadaddr} kernel ${kernelsize};" \
@ -88,8 +88,8 @@
"fi; " \
"${get_cmd} ${image}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"if ${get_cmd} ${fdt_addr_r} ${fdt_file}; then " \
"bootz ${loadaddr} - ${fdt_addr_r}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootz; " \

1
include/configs/imx8mq_evk.h
View File

@ -187,7 +187,6 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_OFFSET (64 * SZ_64K)
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */

8
include/configs/pico-imx6ul.h
View File

@ -128,17 +128,9 @@
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* I2C configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1
#define CONFIG_SYS_I2C_SPEED 100000
/* PMIC */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE3000
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
/* environment organization */
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_OFFSET (8 * SZ_64K)