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mips: traps: Set WG bit in EBase register on Octeon
WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of the exception base register. Signed-off-by: Stefan Roese <sr@denx.de>
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@ -366,6 +366,7 @@
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* Bits in the coprocessor 0 EBase register.
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*/
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#define EBASE_CPUNUM 0x3ff
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#define EBASE_WG (_ULCAST_(1) << 11)
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/*
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* Bits in the coprocessor 0 config register.
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@ -108,6 +108,10 @@ void trap_init(ulong reloc_addr)
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saved_ebase = read_c0_ebase() & 0xfffff000;
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/* Set WG bit on Octeon to enable writing to bits 63:30 */
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if (IS_ENABLED(CONFIG_ARCH_OCTEON))
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ebase |= EBASE_WG;
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write_c0_ebase(ebase);
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clear_c0_status(ST0_BEV);
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execution_hazard_barrier();
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