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crypto: caam: Fix pointer size to 32bit for i.MX8M
The CAAM block used in i.MX8M is 32 bits address size but when the flag PHYS_64BIT is enabled for armv8, the CAAM driver will try to use a wrong pointer size. This patch fixes this issue. Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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2532429b16
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@ -3,6 +3,7 @@
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* caam descriptor construction helper functions
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*
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* Copyright 2008-2014 Freescale Semiconductor, Inc.
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* Copyright 2018 NXP
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*
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* Based on desc_constr.h file in linux drivers/crypto/caam
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*/
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@ -12,7 +13,7 @@
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#define IMMEDIATE (1 << 23)
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#define CAAM_CMD_SZ sizeof(u32)
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#define CAAM_PTR_SZ sizeof(dma_addr_t)
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#define CAAM_PTR_SZ sizeof(u32)
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#define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE)
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#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3)
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@ -35,7 +36,7 @@
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LDST_SRCDST_WORD_DECOCTRL | \
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(LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
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#ifdef CONFIG_PHYS_64BIT
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#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
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struct ptr_addr_t {
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#ifdef CONFIG_SYS_FSL_SEC_LE
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u32 low;
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@ -49,9 +50,9 @@ struct ptr_addr_t {
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};
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#endif
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static inline void pdb_add_ptr(dma_addr_t *offset, dma_addr_t ptr)
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static inline void pdb_add_ptr(u32 *offset, u32 ptr)
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{
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#ifdef CONFIG_PHYS_64BIT
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#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
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/* The Position of low and high part of 64 bit address
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* will depend on the endianness of CAAM Block */
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struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset;
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@ -102,11 +103,11 @@ static inline void init_job_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
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options);
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}
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static inline void append_ptr(u32 *desc, dma_addr_t ptr)
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static inline void append_ptr(u32 *desc, uint32_t ptr)
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{
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dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
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u32 *offset = (u32 *)desc_end(desc);
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#ifdef CONFIG_PHYS_64BIT
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#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
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/* The Position of low and high part of 64 bit address
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* will depend on the endianness of CAAM Block */
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struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset;
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@ -159,7 +160,7 @@ static inline u32 *write_cmd(u32 *desc, u32 command)
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return desc + 1;
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}
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static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len,
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static inline void append_cmd_ptr(u32 *desc, uint32_t ptr, int len,
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u32 command)
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{
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append_cmd(desc, command | len);
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@ -167,7 +168,7 @@ static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len,
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}
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/* Write length after pointer, rather than inside command */
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static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr,
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static inline void append_cmd_ptr_extlen(u32 *desc, uint32_t ptr,
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unsigned int len, u32 command)
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{
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append_cmd(desc, command);
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@ -225,7 +226,7 @@ APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD)
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APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE)
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#define APPEND_CMD_PTR(cmd, op) \
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static inline void append_##cmd(u32 *desc, dma_addr_t ptr, unsigned int len, \
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static inline void append_##cmd(u32 *desc, uint32_t ptr, unsigned int len, \
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u32 options) \
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{ \
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PRINT_POS; \
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@ -236,7 +237,7 @@ APPEND_CMD_PTR(load, LOAD)
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APPEND_CMD_PTR(fifo_load, FIFO_LOAD)
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APPEND_CMD_PTR(fifo_store, FIFO_STORE)
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static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len,
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static inline void append_store(u32 *desc, uint32_t ptr, unsigned int len,
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u32 options)
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{
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u32 cmd_src;
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@ -254,7 +255,7 @@ static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len,
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}
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#define APPEND_SEQ_PTR_INTLEN(cmd, op) \
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static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, dma_addr_t ptr, \
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static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, uint32_t ptr, \
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unsigned int len, \
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u32 options) \
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{ \
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@ -278,7 +279,7 @@ APPEND_CMD_PTR_TO_IMM(load, LOAD);
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APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD);
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#define APPEND_CMD_PTR_EXTLEN(cmd, op) \
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static inline void append_##cmd##_extlen(u32 *desc, dma_addr_t ptr, \
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static inline void append_##cmd##_extlen(u32 *desc, uint32_t ptr, \
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unsigned int len, u32 options) \
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{ \
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PRINT_POS; \
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@ -292,7 +293,7 @@ APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR)
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* the size of its type
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*/
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#define APPEND_CMD_PTR_LEN(cmd, op, type) \
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static inline void append_##cmd(u32 *desc, dma_addr_t ptr, \
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static inline void append_##cmd(u32 *desc, uint32_t ptr, \
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type len, u32 options) \
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{ \
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PRINT_POS; \
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@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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* Copyright 2018 NXP
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*
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*/
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@ -95,7 +96,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf,
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return -EINVAL;
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}
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#ifdef CONFIG_PHYS_64BIT
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#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
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sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, (uint32_t)(addr >> 32));
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#else
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sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, 0x0);
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@ -165,9 +165,10 @@ int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt,
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append_u32(desc, aad_w2);
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append_cmd_ptr(desc, (dma_addr_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR);
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append_cmd_ptr(desc, (uint32_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR);
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append_cmd_ptr(desc, (dma_addr_t)dek_blob + 8, out_sz, CMD_SEQ_OUT_PTR);
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append_cmd_ptr(desc, (uint32_t)((ulong)dek_blob + 8),
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out_sz, CMD_SEQ_OUT_PTR);
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append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB |
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OP_PCLID_SECMEM);
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@ -183,7 +184,7 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc,
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/* SHA 256 , output is of length 32 words */
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uint32_t storelen = alg_size;
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u32 options;
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dma_addr_t dma_addr_in, dma_addr_out;
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u32 dma_addr_in, dma_addr_out;
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dma_addr_in = virt_to_phys((void *)msg);
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dma_addr_out = virt_to_phys((void *)digest);
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@ -212,7 +213,7 @@ void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr,
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uint8_t *plain_txt, uint8_t *enc_blob,
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uint32_t in_sz)
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{
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dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
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u32 dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
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uint32_t key_sz = KEY_IDNFR_SZ_BYTES;
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/* output blob will have 32 bytes key blob in beginning and
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* 16 byte HMAC identifier at end of data blob */
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@ -237,7 +238,7 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr,
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uint8_t *enc_blob, uint8_t *plain_txt,
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uint32_t out_sz)
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{
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dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
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u32 dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
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uint32_t key_sz = KEY_IDNFR_SZ_BYTES;
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uint32_t in_sz = out_sz + KEY_BLOB_SIZE + MAC_SIZE;
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@ -313,7 +314,7 @@ void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
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struct pk_in_params *pkin, uint8_t *out,
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uint32_t out_siz)
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{
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dma_addr_t dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out;
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u32 dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out;
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dma_addr_e = virt_to_phys((void *)pkin->e);
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dma_addr_a = virt_to_phys((void *)pkin->a);
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@ -87,13 +87,13 @@ static void jr_initregs(uint8_t sec_idx)
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phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
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phys_addr_t op_base = virt_to_phys((void *)jr->output_ring);
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#ifdef CONFIG_PHYS_64BIT
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#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
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sec_out32(®s->irba_h, ip_base >> 32);
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#else
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sec_out32(®s->irba_h, 0x0);
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#endif
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sec_out32(®s->irba_l, (uint32_t)ip_base);
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#ifdef CONFIG_PHYS_64BIT
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#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
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sec_out32(®s->orba_h, op_base >> 32);
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#else
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sec_out32(®s->orba_h, 0x0);
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@ -119,7 +119,7 @@ static int jr_init(uint8_t sec_idx)
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jr->liodn = DEFAULT_JR_LIODN;
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#endif
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jr->size = JR_SIZE;
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jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
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jr->input_ring = (uint32_t *)memalign(ARCH_DMA_MINALIGN,
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JR_SIZE * sizeof(dma_addr_t));
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if (!jr->input_ring)
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return -1;
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@ -196,7 +196,7 @@ static int jr_enqueue(uint32_t *desc_addr,
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uint32_t desc_word;
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int length = desc_len(desc_addr);
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int i;
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#ifdef CONFIG_PHYS_64BIT
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#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
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uint32_t *addr_hi, *addr_lo;
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#endif
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@ -223,7 +223,7 @@ static int jr_enqueue(uint32_t *desc_addr,
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sizeof(struct jr_info), ARCH_DMA_MINALIGN);
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flush_dcache_range(start, end);
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#ifdef CONFIG_PHYS_64BIT
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#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
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/* Write the 64 bit Descriptor address on Input Ring.
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* The 32 bit hign and low part of the address will
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* depend on endianness of SEC block.
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@ -272,7 +272,7 @@ static int jr_dequeue(int sec_idx)
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int idx, i, found;
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void (*callback)(uint32_t status, void *arg);
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void *arg = NULL;
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#ifdef CONFIG_PHYS_64BIT
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#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
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uint32_t *addr_hi, *addr_lo;
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#else
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uint32_t *addr;
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@ -284,7 +284,7 @@ static int jr_dequeue(int sec_idx)
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found = 0;
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phys_addr_t op_desc;
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#ifdef CONFIG_PHYS_64BIT
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#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
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/* Read the 64 bit Descriptor address from Output Ring.
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* The 32 bit hign and low part of the address will
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* depend on endianness of SEC block.
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@ -678,7 +678,7 @@ int sec_init_idx(uint8_t sec_idx)
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mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
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#endif
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#ifdef CONFIG_PHYS_64BIT
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#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
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mcr |= (1 << MCFGR_PS_SHIFT);
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#endif
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sec_out32(&sec->mcfgr, mcr);
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2008-2014 Freescale Semiconductor, Inc.
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* Copyright 2018 NXP
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*
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*/
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@ -41,8 +42,8 @@
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#define RNG4_MAX_HANDLES 2
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struct op_ring {
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phys_addr_t desc;
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uint32_t status;
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u32 desc;
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u32 status;
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} __packed;
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struct jr_info {
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@ -83,7 +84,7 @@ struct jobring {
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* by SEC
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*/
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/*Circular Ring of i/p descriptors */
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dma_addr_t *input_ring;
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u32 *input_ring;
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/* Circular Ring of o/p descriptors */
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/* Circula Ring containing info regarding descriptors in i/p
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* and o/p ring
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