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crypto: caam: Fix pointer size to 32bit for i.MX8M

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The CAAM block used in i.MX8M is 32 bits address size but when the flag
 PHYS_64BIT is enabled for armv8, the CAAM driver will try to use a
 wrong pointer size.
  This patch fixes this issue.

Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Aymen Sghaier 2021-03-25 17:30:28 +08:00 committed by Stefano Babic
parent 2532429b16
commit a018e6e4f7
5 changed files with 36 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
drivers/crypto/fsl/desc_constr.h
View File

@ -3,6 +3,7 @@
* caam descriptor construction helper functions
*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
*
* Based on desc_constr.h file in linux drivers/crypto/caam
*/
@ -12,7 +13,7 @@
#define IMMEDIATE (1 << 23)
#define CAAM_CMD_SZ sizeof(u32)
#define CAAM_PTR_SZ sizeof(dma_addr_t)
#define CAAM_PTR_SZ sizeof(u32)
#define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE)
#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3)
@ -35,7 +36,7 @@
LDST_SRCDST_WORD_DECOCTRL | \
(LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
#ifdef CONFIG_PHYS_64BIT
#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
struct ptr_addr_t {
#ifdef CONFIG_SYS_FSL_SEC_LE
u32 low;
@ -49,9 +50,9 @@ struct ptr_addr_t {
};
#endif
static inline void pdb_add_ptr(dma_addr_t *offset, dma_addr_t ptr)
static inline void pdb_add_ptr(u32 *offset, u32 ptr)
{
#ifdef CONFIG_PHYS_64BIT
#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
/* The Position of low and high part of 64 bit address
* will depend on the endianness of CAAM Block */
struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset;
@ -102,11 +103,11 @@ static inline void init_job_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
options);
}
static inline void append_ptr(u32 *desc, dma_addr_t ptr)
static inline void append_ptr(u32 *desc, uint32_t ptr)
{
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
u32 *offset = (u32 *)desc_end(desc);
#ifdef CONFIG_PHYS_64BIT
#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
/* The Position of low and high part of 64 bit address
* will depend on the endianness of CAAM Block */
struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset;
@ -159,7 +160,7 @@ static inline u32 *write_cmd(u32 *desc, u32 command)
return desc + 1;
}
static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len,
static inline void append_cmd_ptr(u32 *desc, uint32_t ptr, int len,
u32 command)
{
append_cmd(desc, command | len);
@ -167,7 +168,7 @@ static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len,
}
/* Write length after pointer, rather than inside command */
static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr,
static inline void append_cmd_ptr_extlen(u32 *desc, uint32_t ptr,
unsigned int len, u32 command)
{
append_cmd(desc, command);
@ -225,7 +226,7 @@ APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD)
APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE)
#define APPEND_CMD_PTR(cmd, op) \
static inline void append_##cmd(u32 *desc, dma_addr_t ptr, unsigned int len, \
static inline void append_##cmd(u32 *desc, uint32_t ptr, unsigned int len, \
u32 options) \
{ \
PRINT_POS; \
@ -236,7 +237,7 @@ APPEND_CMD_PTR(load, LOAD)
APPEND_CMD_PTR(fifo_load, FIFO_LOAD)
APPEND_CMD_PTR(fifo_store, FIFO_STORE)
static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len,
static inline void append_store(u32 *desc, uint32_t ptr, unsigned int len,
u32 options)
{
u32 cmd_src;
@ -254,7 +255,7 @@ static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len,
}
#define APPEND_SEQ_PTR_INTLEN(cmd, op) \
static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, dma_addr_t ptr, \
static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, uint32_t ptr, \
unsigned int len, \
u32 options) \
{ \
@ -278,7 +279,7 @@ APPEND_CMD_PTR_TO_IMM(load, LOAD);
APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD);
#define APPEND_CMD_PTR_EXTLEN(cmd, op) \
static inline void append_##cmd##_extlen(u32 *desc, dma_addr_t ptr, \
static inline void append_##cmd##_extlen(u32 *desc, uint32_t ptr, \
unsigned int len, u32 options) \
{ \
PRINT_POS; \
@ -292,7 +293,7 @@ APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR)
* the size of its type
*/
#define APPEND_CMD_PTR_LEN(cmd, op, type) \
static inline void append_##cmd(u32 *desc, dma_addr_t ptr, \
static inline void append_##cmd(u32 *desc, uint32_t ptr, \
type len, u32 options) \
{ \
PRINT_POS; \

3
drivers/crypto/fsl/fsl_hash.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
*
*/
@ -95,7 +96,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf,
return -EINVAL;
}
#ifdef CONFIG_PHYS_64BIT
#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, (uint32_t)(addr >> 32));
#else
sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, 0x0);

13
drivers/crypto/fsl/jobdesc.c
View File

@ -165,9 +165,10 @@ int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt,
append_u32(desc, aad_w2);
append_cmd_ptr(desc, (dma_addr_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR);
append_cmd_ptr(desc, (uint32_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR);
append_cmd_ptr(desc, (dma_addr_t)dek_blob + 8, out_sz, CMD_SEQ_OUT_PTR);
append_cmd_ptr(desc, (uint32_t)((ulong)dek_blob + 8),
out_sz, CMD_SEQ_OUT_PTR);
append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB |
OP_PCLID_SECMEM);
@ -183,7 +184,7 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc,
/* SHA 256 , output is of length 32 words */
uint32_t storelen = alg_size;
u32 options;
dma_addr_t dma_addr_in, dma_addr_out;
u32 dma_addr_in, dma_addr_out;
dma_addr_in = virt_to_phys((void *)msg);
dma_addr_out = virt_to_phys((void *)digest);
@ -212,7 +213,7 @@ void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr,
uint8_t *plain_txt, uint8_t *enc_blob,
uint32_t in_sz)
{
dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
u32 dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
uint32_t key_sz = KEY_IDNFR_SZ_BYTES;
/* output blob will have 32 bytes key blob in beginning and
* 16 byte HMAC identifier at end of data blob */
@ -237,7 +238,7 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr,
uint8_t *enc_blob, uint8_t *plain_txt,
uint32_t out_sz)
{
dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
u32 dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
uint32_t key_sz = KEY_IDNFR_SZ_BYTES;
uint32_t in_sz = out_sz + KEY_BLOB_SIZE + MAC_SIZE;
@ -313,7 +314,7 @@ void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
struct pk_in_params *pkin, uint8_t *out,
uint32_t out_siz)
{
dma_addr_t dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out;
u32 dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out;
dma_addr_e = virt_to_phys((void *)pkin->e);
dma_addr_a = virt_to_phys((void *)pkin->a);

16
drivers/crypto/fsl/jr.c
View File

@ -87,13 +87,13 @@ static void jr_initregs(uint8_t sec_idx)
phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
phys_addr_t op_base = virt_to_phys((void *)jr->output_ring);
#ifdef CONFIG_PHYS_64BIT
#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
sec_out32(&regs->irba_h, ip_base >> 32);
#else
sec_out32(&regs->irba_h, 0x0);
#endif
sec_out32(&regs->irba_l, (uint32_t)ip_base);
#ifdef CONFIG_PHYS_64BIT
#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
sec_out32(&regs->orba_h, op_base >> 32);
#else
sec_out32(&regs->orba_h, 0x0);
@ -119,7 +119,7 @@ static int jr_init(uint8_t sec_idx)
jr->liodn = DEFAULT_JR_LIODN;
#endif
jr->size = JR_SIZE;
jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
jr->input_ring = (uint32_t *)memalign(ARCH_DMA_MINALIGN,
JR_SIZE * sizeof(dma_addr_t));
if (!jr->input_ring)
return -1;
@ -196,7 +196,7 @@ static int jr_enqueue(uint32_t *desc_addr,
uint32_t desc_word;
int length = desc_len(desc_addr);
int i;
#ifdef CONFIG_PHYS_64BIT
#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
uint32_t *addr_hi, *addr_lo;
#endif
@ -223,7 +223,7 @@ static int jr_enqueue(uint32_t *desc_addr,
sizeof(struct jr_info), ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
#ifdef CONFIG_PHYS_64BIT
#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
/* Write the 64 bit Descriptor address on Input Ring.
* The 32 bit hign and low part of the address will
* depend on endianness of SEC block.
@ -272,7 +272,7 @@ static int jr_dequeue(int sec_idx)
int idx, i, found;
void (*callback)(uint32_t status, void *arg);
void *arg = NULL;
#ifdef CONFIG_PHYS_64BIT
#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
uint32_t *addr_hi, *addr_lo;
#else
uint32_t *addr;
@ -284,7 +284,7 @@ static int jr_dequeue(int sec_idx)
found = 0;
phys_addr_t op_desc;
#ifdef CONFIG_PHYS_64BIT
#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
/* Read the 64 bit Descriptor address from Output Ring.
* The 32 bit hign and low part of the address will
* depend on endianness of SEC block.
@ -678,7 +678,7 @@ int sec_init_idx(uint8_t sec_idx)
mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
#endif
#ifdef CONFIG_PHYS_64BIT
#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M)
mcr |= (1 << MCFGR_PS_SHIFT);
#endif
sec_out32(&sec->mcfgr, mcr);

7
drivers/crypto/fsl/jr.h
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
*
*/
@ -41,8 +42,8 @@
#define RNG4_MAX_HANDLES 2
struct op_ring {
phys_addr_t desc;
uint32_t status;
u32 desc;
u32 status;
} __packed;
struct jr_info {
@ -83,7 +84,7 @@ struct jobring {
* by SEC
*/
/*Circular Ring of i/p descriptors */
dma_addr_t *input_ring;
u32 *input_ring;
/* Circular Ring of o/p descriptors */
/* Circula Ring containing info regarding descriptors in i/p
* and o/p ring