From 5c34eee94dfafab27d7d76aa5457458672f7544c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 12 Oct 2006 07:04:24 +0200 Subject: [PATCH 01/14] Fix JFFS2 compilation problem Patch by Stefan Roese, 12 Oct 2006 --- CHANGELOG | 3 +++ lib_generic/crc32.c | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 98b3324eb9..68aa65ae3c 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fix JFFS2 compilation problem + Patch by Stefan Roese, 12 Oct 2006 + * Cleanup of NAND update patch (remove changelog from cmd_nand.c) Patch by Guido Classen, 10 Oct 2006 diff --git a/lib_generic/crc32.c b/lib_generic/crc32.c index 3db224a364..3d99b69296 100644 --- a/lib_generic/crc32.c +++ b/lib_generic/crc32.c @@ -171,8 +171,8 @@ uLong ZEXPORT crc32(crc, buf, len) return crc ^ 0xffffffffL; } -#if ((CONFIG_COMMANDS & CFG_CMD_JFFS2) || (CONFIG_COMMANDS & CFG_CMD_NAND)) \ - && !defined(CFG_NAND_LEGACY) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) || \ + ((CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)) /* No ones complement version. JFFS2 (and other things ?) * don't use ones compliment in their CRC calculations. From 87621bc24789e024c62a8a12bebd592943cdfb02 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 12 Oct 2006 11:43:47 +0200 Subject: [PATCH 02/14] Fix spelling; minor code cleanup. --- CHANGELOG | 2 ++ common/cmd_nand.c | 2 +- drivers/nand/nand_util.c | 6 +++--- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 68aa65ae3c..166cfa3a4e 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fix spelling; minor code cleanup. + * Fix JFFS2 compilation problem Patch by Stefan Roese, 12 Oct 2006 diff --git a/common/cmd_nand.c b/common/cmd_nand.c index fdbe7c78a6..7042a9c226 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -251,7 +251,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) "Use this command only for testing purposes " "if you\n" " " - "are shure of what you are doing!\n" + "are sure of what you are doing!\n" "\nReally scrub this NAND flash? \n" ); diff --git a/drivers/nand/nand_util.c b/drivers/nand/nand_util.c index 5a8e58a741..7570210d5c 100644 --- a/drivers/nand/nand_util.c +++ b/drivers/nand/nand_util.c @@ -170,9 +170,9 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) if (ret > 0) { if (!opts->quiet) printf("\rSkipping bad block at " - "0x%08x " - " \n", - erase.addr); + "0x%08x " + " \n", + erase.addr); continue; } else if (ret < 0) { From e0a46554c3459dc7cabf149c135e79e8df70ae14 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 12 Oct 2006 19:43:29 +0200 Subject: [PATCH 03/14] * PPC405EP: Add CFG_GPIO0_OR, CFG_GPIO0_ODR to setup GPIO completely. - Add configuration of Open Drain GPIO Output selection - Add configuration of initial value of GPIO output pins Patch by Tolunay Orkun, 07 Apr 2006 --- CHANGELOG | 5 +++++ cpu/ppc4xx/cpu_init.c | 14 ++++++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 166cfa3a4e..87a87461d9 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,11 @@ Changes since U-Boot 1.1.4: ====================================================================== +* PPC405EP: Add CFG_GPIO0_OR, CFG_GPIO0_ODR to setup GPIO completely. + - Add configuration of Open Drain GPIO Output selection + - Add configuration of initial value of GPIO output pins + Patch by Tolunay Orkun, 07 Apr 2006 + * Fix spelling; minor code cleanup. * Fix JFFS2 compilation problem diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index b27567fa4d..def46f15ca 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -226,13 +226,19 @@ cpu_init_f (void) /* * GPIO0 setup (select GPIO or alternate function) */ - out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ +#if defined(CFG_GPIO0_OR) + out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */ +#endif +#if defined(CFG_GPIO0_ODR) + out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */ +#endif + out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ out32(GPIO0_OSRL, CFG_GPIO0_OSRL); - out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ + out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); - out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ + out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ out32(GPIO0_TSRL, CFG_GPIO0_TSRL); - out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ + out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ /* * Set EMAC noise filter bits From d7762337cbc8293b259218b4a804dc626e257a4a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 12 Oct 2006 19:50:17 +0200 Subject: [PATCH 04/14] * PPC405EP: Add support for board configuration of CPC0_PCI register This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE* Patch by Tolunay Orkun, 07 Apr 2006 --- CHANGELOG | 4 ++++ cpu/ppc4xx/start.S | 6 +++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/CHANGELOG b/CHANGELOG index 87a87461d9..2a40ab3561 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,10 @@ Changes since U-Boot 1.1.4: ====================================================================== +* PPC405EP: Add support for board configuration of CPC0_PCI register + This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE* + Patch by Tolunay Orkun, 07 Apr 2006 + * PPC405EP: Add CFG_GPIO0_OR, CFG_GPIO0_ODR to setup GPIO completely. - Add configuration of Open Drain GPIO Output selection - Add configuration of initial value of GPIO output pins diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 3f2931411f..3fe13daaf3 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1697,7 +1697,8 @@ ppc405ep_init: mtdcr ebccfgd,r3 #endif - addi r3,0,CPC0_PCI_HOST_CFG_EN +#ifndef CFG_CPC0_PCI + li r3,CPC0_PCI_HOST_CFG_EN #ifdef CONFIG_BUBINGA /* !----------------------------------------------------------------------- @@ -1712,6 +1713,9 @@ ppc405ep_init: beq ..pci_cfg_set /* if not set, then bypass reg write*/ #endif ori r3,r3,CPC0_PCI_ARBIT_EN +#else /* CFG_CPC0_PCI */ + li r3,CFG_CPC0_PCI +#endif /* CFG_CPC0_PCI */ ..pci_cfg_set: mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/ From 4707fb50cc9f815996be5f2e5a8660de852b2c37 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Fri, 13 Oct 2006 21:09:09 +0200 Subject: [PATCH 05/14] Preliminary patch adding support for the MarelV38B board. --- MAKEALL | 2 +- Makefile | 3 + board/v38b/Makefile | 50 ++++++ board/v38b/config.mk | 32 ++++ board/v38b/ethaddr.c | 254 ++++++++++++++++++++++++++++ board/v38b/u-boot.lds | 122 ++++++++++++++ board/v38b/v38b.c | 253 ++++++++++++++++++++++++++++ cpu/mpc5xxx/fec.c | 2 +- include/common.h | 3 +- include/configs/V38B.h | 368 +++++++++++++++++++++++++++++++++++++++++ include/status_led.h | 9 + lib_ppc/board.c | 7 +- 12 files changed, 1100 insertions(+), 5 deletions(-) create mode 100644 board/v38b/Makefile create mode 100644 board/v38b/config.mk create mode 100644 board/v38b/ethaddr.c create mode 100644 board/v38b/u-boot.lds create mode 100644 board/v38b/v38b.c create mode 100644 include/configs/V38B.h diff --git a/MAKEALL b/MAKEALL index 2a334ffbf9..f761467ae6 100755 --- a/MAKEALL +++ b/MAKEALL @@ -39,7 +39,7 @@ LIST_5xxx=" \ icecube_5100 icecube_5200 lite5200b mcc200 \ o2dnt pf5200 PM520 TB5200 \ Total5100 Total5200 Total5200_Rev2 TQM5200 \ - TQM5200_B TQM5200S \ + TQM5200_B TQM5200S v38b \ " ######################################################################### diff --git a/Makefile b/Makefile index ccf7f9f88f..3924f6559a 100644 --- a/Makefile +++ b/Makefile @@ -400,6 +400,9 @@ icecube_5100_config: unconfig } @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube +v38b_config: unconfig + @./mkconfig -a V38B ppc mpc5xxx v38b + inka4x0_config: unconfig @$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0 diff --git a/board/v38b/Makefile b/board/v38b/Makefile new file mode 100644 index 0000000000..304deaa4f2 --- /dev/null +++ b/board/v38b/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o ethaddr.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/v38b/config.mk b/board/v38b/config.mk new file mode 100644 index 0000000000..75577fcbec --- /dev/null +++ b/board/v38b/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MarelV38B board +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +TEXT_BASE = 0xFF000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/v38b/ethaddr.c b/board/v38b/ethaddr.c new file mode 100644 index 0000000000..105608051c --- /dev/null +++ b/board/v38b/ethaddr.c @@ -0,0 +1,254 @@ +/* + * + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define GPIO_ENABLE (MPC5XXX_WU_GPIO) + +/* Open Drain Emulation Register */ +#define GPIO_ODR (MPC5XXX_WU_GPIO + 0x04) + +/* Data Direction Register */ +#define GPIO_DDR (MPC5XXX_WU_GPIO + 0x08) + +/* Data Value Out Register */ +#define GPIO_DVOR (MPC5XXX_WU_GPIO + 0x0C) + +/* Interrupt Enable Register */ +#define GPIO_IER (MPC5XXX_WU_GPIO + 0x10) + +/* Individual Interrupt Enable Register */ +#define GPIO_IIER (MPC5XXX_WU_GPIO + 0x14) + +/* Interrupt Type Register */ +#define GPIO_ITR (MPC5XXX_WU_GPIO + 0x18) + +/* Master Enable Register */ +#define GPIO_MER (MPC5XXX_WU_GPIO + 0x1C) + +/* Data Input Value Register */ +#define GPIO_DIVR (MPC5XXX_WU_GPIO + 0x20) + +/* Status Register */ +#define GPIO_SR (MPC5XXX_WU_GPIO + 0x24) + +#define PSC6_0 0x10000000 +#define WKUP_7 0x80000000 + +/* For NS4 A/B board define WKUP_7, for V38B board PSC_6 */ +#define GPIO_PIN PSC6_0 + +#define NO_ERROR 0 +#define ERR_NO_NUMBER 1 +#define ERR_BAD_NUMBER 2 + +typedef volatile unsigned long GPIO_REG; +typedef GPIO_REG *GPIO_REG_PTR; + +static int is_high(void); +static int check_device(void); +static void io_out(int value); +static void io_input(void); +static void io_output(void); +static void init_gpio(void); +static void read_byte(unsigned char *data); +static void write_byte(unsigned char command); + +void read_2501_memory(unsigned char *psernum, unsigned char *perr); +void board_get_enetaddr(uchar *enetaddr); + +static int is_high() +{ + return (* ((vu_long *) GPIO_DIVR) & GPIO_PIN); +} + +static void io_out(int value) +{ + if (value) + *((vu_long *) GPIO_DVOR) |= GPIO_PIN; + else + *((vu_long *) GPIO_DVOR) &= ~GPIO_PIN; +} + +static void io_input() +{ + *((vu_long *) GPIO_DDR) &= ~GPIO_PIN; + udelay(3); /* allow input to settle */ +} + +static void io_output() +{ + *((vu_long *) GPIO_DDR) |= GPIO_PIN; +} + +static void init_gpio() +{ + *((vu_long *) GPIO_ENABLE) |= GPIO_PIN; /* Enable appropriate pin */ +} + +void read_2501_memory(unsigned char *psernum, unsigned char *perr) +{ +#define NBYTES 28 + unsigned char crcval, i; + unsigned char buf[NBYTES]; + + *perr = 0; + crcval = 0; + + for (i=0; i> 1; + } +} + +static void read_byte(unsigned char *data) +{ + unsigned char i, rdat = 0; + + for (i=0; i<8; i++) { + /* read one bit from one-wire device */ + + /* 1 - 15 us low starts bit slot */ + io_out(0); + io_output(); + udelay(0); + + /* allow line to be pulled high */ + io_input(); + + /* delay 10 us */ + udelay(10); + + /* now sample input status */ + if (is_high()) + rdat = (rdat >> 1) | 0x80; + else + rdat = rdat >> 1; + + udelay(60); /* at least 60 us */ + } + /* copy the return value */ + *data = rdat; +} + +void board_get_enetaddr(uchar *enetaddr) +{ + unsigned char sn[6], err=NO_ERROR; + + init_gpio(); + + read_2501_memory(sn, &err); + + if (err == NO_ERROR) { + sprintf(enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x", + sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]); + printf("MAC address: %s\n", enetaddr); + setenv("ethaddr", enetaddr); + } + else { + sprintf(enetaddr, "00:01:02:03:04:05"); + printf("Error reading MAC address.\n"); + printf("Setting default to %s\n", enetaddr); + setenv("ethaddr", enetaddr); + } +} diff --git a/board/v38b/u-boot.lds b/board/v38b/u-boot.lds new file mode 100644 index 0000000000..6ec525691a --- /dev/null +++ b/board/v38b/u-boot.lds @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c new file mode 100644 index 0000000000..c56c6c84d2 --- /dev/null +++ b/board/v38b/v38b.c @@ -0,0 +1,253 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifndef CFG_RAMBOOT +static void sdram_start(int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif /* SDRAM_DDR */ + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif /* !CFG_RAMBOOT */ + + +long int initdram(int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; + uint svr, pvr; + +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif /* SDRAM_DDR */ + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else + dramsize = test2; + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) + dramsize = 0; + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; + else + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ + + /* find RAM size using SDRAM CS1 only */ + if (!dramsize) + sdram_start(0); + test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + if (!dramsize) { + sdram_start(1); + test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + } + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else + dramsize2 = test2; + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) + dramsize2 = 0; + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + else + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) + dramsize = (1 << (dramsize - 0x13)) << 20; + else + dramsize = 0; + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + else + dramsize2 = 0; + +#endif /* CFG_RAMBOOT */ + + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + + return dramsize + dramsize2; +} + + +int checkboard (void) +{ + puts("Board: MarelV38B\n"); + return 0; +} + + +int board_early_init_r(void) +{ + /* + * Now, when we are in RAM, enable flash write access for detection process. + * Note that CS_BOOT cannot be cleared when executing in flash. + */ + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ + return 0; +} + + +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +#define GPIO_PSC1_4 0x01000000UL + +void init_ide_reset(void) +{ + debug("init_ide_reset\n"); + + /* Configure PSC1_4 as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; + /* Deassert reset */ + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; +} + + +void ide_set_reset(int idereset) +{ + debug("ide_reset(%d)\n", idereset); + + if (idereset) { + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + /* Make a delay. MPC5200 spec says 25 usec min */ + udelay(500000); + } else + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + + +void led_d4_on(void) +{ + /* TIMER7 as GPIO output low */ + *(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x24; +} + + +void led_d4_off(void) +{ + /* TIMER7 as GPIO output high */ + *(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x34; +} + + +void hw_watchdog_reset(void) +{ +/* TODO fill this in */ +} + diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c index 19737ce868..37fe3e7153 100644 --- a/cpu/mpc5xxx/fec.c +++ b/cpu/mpc5xxx/fec.c @@ -882,7 +882,7 @@ int mpc5xxx_fec_initialize(bd_t * bis) defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \ defined(CONFIG_MCC200) || defined(CONFIG_O2DNT) || \ defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \ - defined(CONFIG_TQM5200) + defined(CONFIG_TQM5200) || defined(CONFIG_V38B) # ifndef CONFIG_FEC_10MBIT fec->xcv_type = MII100; # else diff --git a/include/common.h b/include/common.h index bee2fb7022..e296e684a0 100644 --- a/include/common.h +++ b/include/common.h @@ -313,7 +313,8 @@ void board_ether_init (void); #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_MBX) || \ defined(CONFIG_IAD210) || defined(CONFIG_XPEDITE1K) || \ - defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) + defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) || \ + defined(CONFIG_V38B) void board_get_enetaddr (uchar *addr); #endif diff --git a/include/configs/V38B.h b/include/configs/V38B.h new file mode 100644 index 0000000000..9b8fc699a9 --- /dev/null +++ b/include/configs/V38B.h @@ -0,0 +1,368 @@ +/* + * (C) Copyright 2003-2004 Wolfgang Denk, DENX Software Engineering, + * wd@denx.de. + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#if 0 +#define DEBUG 0xFFF +#endif + +#if 0 +#define DEBUG 0x01 +#endif + +/* + * High Level Configuration Options + * (easy to change) +*/ + +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ +#define CONFIG_V38B 1 /* ... on V38B board */ +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ +#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ +#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ + +#define CONFIG_NETCONSOLE 1 + +#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */ + +#define CFG_XLB_PIPELINING 1 /* gives better performance */ + + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + + +/* + * DDR + */ +#define SDRAM_DDR 1 /* is DDR */ +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x704f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + + +/* + * PCI - no suport + */ +#undef CONFIG_PCI + +/* + * Partitions + */ +#define CONFIG_MAC_PARTITION 1 +#define CONFIG_DOS_PARTITION 1 + +/* + * USB + */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_PING | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_IRQ | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_SDRAMi | \ + CFG_CMD_DATE | \ + CFG_CMD_USB | \ + CFG_CMD_FAT) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Boot low with 16 MB Flash + */ +# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT16 1 + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "devno=5\0" \ + "hostname=V38B_$(devno)\0" \ + "ipaddr=10.100.99.$(devno)\0" \ + "netmask=255.255.0.0\0" \ + "serverip=10.100.10.90\0" \ + "gatewayip=10.100.254.254\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=mpc5200/uImage\0" \ + "bootcmd=run net_nfs\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):" \ + "$(netmask):$(hostname):$(netdev):off panic=1\0" \ + "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip;bootm $(kernel_addr) " \ + "$(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs " \ + "addip;bootm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#if defined(CONFIG_MPC5200) +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#endif +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 + +/* + * RTC configuration + */ +#define CFG_I2C_RTC_ADDR 0x51 + +/* + * Flash configuration - use CFI driver + */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */ +#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_OVERWRITE 1 + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_MII 1 + +/* + * GPIO configuration + */ +#define CFG_GPS_PORT_CONFIG 0x90000404 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00047801 +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +/* Status LED */ + +#define CONFIG_STATUS_LED /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ + +#define CFG_LED_BASE (0xf0000600 + 0x70) /* Timer 7 GPIO */ + +#ifndef __ASSEMBLY__ +/* LEDs */ +typedef unsigned int led_id_t; + +#define __led_toggle(_msk) \ + do { \ + *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \ + } while(0) + +#define __led_set(_msk, _st) \ + do { \ + if ((_st)) \ + *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \ + else \ + *((volatile long *) (CFG_LED_BASE)) |= (_msk); \ + } while(0) + +#define __led_init(_msk, st) \ + { \ + *((volatile long *) (CFG_LED_BASE)) |= 0x34; \ + } + +#endif + +#endif /* __CONFIG_H */ diff --git a/include/status_led.h b/include/status_led.h index a56883b9a5..db4c60fe3f 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -346,6 +346,15 @@ void status_led_set (int led, int state); #elif defined(CONFIG_NIOS2) /* XXX empty just to avoid the error */ /************************************************************************/ +#elif defined(CONFIG_V38B) + +# define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */ +# define STATUS_LED_PERIOD (CFG_HZ / 2) +# define STATUS_LED_STATE STATUS_LED_BLINKING + +# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ +# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + #else # error Status LED configuration missing #endif diff --git a/lib_ppc/board.c b/lib_ppc/board.c index cf0e3fdf4b..3e401bead0 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2004 + * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -805,7 +805,10 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif /* CFG_EXTBDINFO */ s = getenv ("ethaddr"); -#if defined (CONFIG_MBX) || defined (CONFIG_RPXCLASSIC) || defined(CONFIG_IAD210) +#if defined (CONFIG_MBX) || \ + defined (CONFIG_RPXCLASSIC) || \ + defined(CONFIG_IAD210) || \ + defined(CONFIG_V38B) if (s == NULL) board_get_enetaddr (bd->bi_enetaddr); else From edf0b5433872eb9f468d7460667445b0492dc7e0 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 18 Oct 2006 15:59:35 +0200 Subject: [PATCH 06/14] Make 4xx bootup message shorter on 440EPx/GRx platforms Patch by Stefan Roese, 18 Oct 2006 --- CHANGELOG | 3 +++ cpu/ppc4xx/cpu.c | 16 ++++++++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 2a40ab3561..1092d30e68 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Make 4xx bootup message shorter on 440EPx/GRx platforms + Patch by Stefan Roese, 18 Oct 2006 + * PPC405EP: Add support for board configuration of CPC0_PCI register This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE* Patch by Tolunay Orkun, 07 Apr 2006 diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 94478dbb10..6badfb1b24 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -190,6 +190,7 @@ int checkcpu (void) uint pvr = get_pvr(); ulong clock = gd->cpu_clk; char buf[32]; + char addstr[64] = ""; #if !defined(CONFIG_IOP480) sys_info_t sys_info; @@ -308,19 +309,23 @@ int checkcpu (void) #endif /* CONFIG_440 */ case PVR_440EPX1_RA: - puts("EPx Rev. A - Security/Kasumi support"); + puts("EPx Rev. A"); + strcpy(addstr, "Security/Kasumi support"); break; case PVR_440EPX2_RA: - puts("EPx Rev. A - No Security/Kasumi support"); + puts("EPx Rev. A"); + strcpy(addstr, "No Security/Kasumi support"); break; case PVR_440GRX1_RA: - puts("GRx Rev. A - Security/Kasumi support"); + puts("GRx Rev. A"); + strcpy(addstr, "Security/Kasumi support"); break; case PVR_440GRX2_RA: - puts("GRx Rev. A - No Security/Kasumi support"); + puts("GRx Rev. A"); + strcpy(addstr, "No Security/Kasumi support"); break; case PVR_440SP_RA: @@ -349,6 +354,9 @@ int checkcpu (void) sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, FREQ_EBC / 1000000); + if (addstr[0] != 0) + printf(" %s\n", addstr); + #if defined(I2C_BOOTROM) printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis"); #if defined(SDR0_PINSTP_SHIFT) From 3231ea64f460e6f55fea14582f2b0dd463744113 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 18 Oct 2006 22:31:08 +0200 Subject: [PATCH 07/14] Update CHANGELOG --- CHANGELOG | 2 ++ 1 file changed, 2 insertions(+) diff --git a/CHANGELOG b/CHANGELOG index 2a40ab3561..da785f4ba8 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Add (preliminary) support for V38B board + * PPC405EP: Add support for board configuration of CPC0_PCI register This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE* Patch by Tolunay Orkun, 07 Apr 2006 From fcfed4f2f234836a0b308fd0a782f4625cd40bad Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 18 Oct 2006 22:44:38 +0200 Subject: [PATCH 08/14] Coding Style cleanup. --- board/v38b/ethaddr.c | 4 +- board/v38b/v38b.c | 1 - doc/README.nand | 3 -- include/configs/V38B.h | 112 ++++++++++++++++++++--------------------- 4 files changed, 58 insertions(+), 62 deletions(-) diff --git a/board/v38b/ethaddr.c b/board/v38b/ethaddr.c index 105608051c..aaa629ef61 100644 --- a/board/v38b/ethaddr.c +++ b/board/v38b/ethaddr.c @@ -118,7 +118,7 @@ void read_2501_memory(unsigned char *psernum, unsigned char *perr) crcval = 0; for (i=0; i> 1) | 0x80; else rdat = rdat >> 1; - + udelay(60); /* at least 60 us */ } /* copy the return value */ diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c index c56c6c84d2..99fe7dbc3c 100644 --- a/board/v38b/v38b.c +++ b/board/v38b/v38b.c @@ -250,4 +250,3 @@ void hw_watchdog_reset(void) { /* TODO fill this in */ } - diff --git a/doc/README.nand b/doc/README.nand index 2b9a52966c..5279a4f2bc 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -1,9 +1,7 @@ NAND FLASH commands and notes - See NOTE below!!! - # (C) Copyright 2003 # Dave Ellis, SIXNET, dge@sixnetio.com # @@ -209,7 +207,6 @@ the tree until the DoC is ported to use the new NAND support (or boards with DoC will break). - Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006 JFFS2 related commands: diff --git a/include/configs/V38B.h b/include/configs/V38B.h index 9b8fc699a9..8eea504742 100644 --- a/include/configs/V38B.h +++ b/include/configs/V38B.h @@ -11,7 +11,7 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. * * You should have received a copy of the GNU General Public License along @@ -35,35 +35,35 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_V38B 1 /* ... on V38B board */ -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ +#define CONFIG_V38B 1 /* ... on V38B board */ +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ -#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ -#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ -#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ +#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ +#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ +#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ #define CONFIG_NETCONSOLE 1 -#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */ +#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */ -#define CFG_XLB_PIPELINING 1 /* gives better performance */ +#define CFG_XLB_PIPELINING 1 /* gives better performance */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /* * Serial console configuration */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } @@ -97,12 +97,12 @@ #define CONFIG_USB_OHCI #define CONFIG_USB_STORAGE -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ /* * Supported commands */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_FAT | \ CFG_CMD_I2C | \ CFG_CMD_IDE | \ @@ -112,7 +112,7 @@ CFG_CMD_IRQ | \ CFG_CMD_JFFS2 | \ CFG_CMD_MII | \ - CFG_CMD_SDRAMi | \ + CFG_CMD_SDRAMi | \ CFG_CMD_DATE | \ CFG_CMD_USB | \ CFG_CMD_FAT) @@ -123,7 +123,7 @@ /* * Boot low with 16 MB Flash */ -# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT 1 # define CFG_LOWBOOT16 1 /* @@ -131,35 +131,35 @@ */ #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ -#define CONFIG_PREBOOT "echo;" \ +#define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "devno=5\0" \ - "hostname=V38B_$(devno)\0" \ - "ipaddr=10.100.99.$(devno)\0" \ - "netmask=255.255.0.0\0" \ - "serverip=10.100.10.90\0" \ - "gatewayip=10.100.254.254\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=mpc5200/uImage\0" \ - "bootcmd=run net_nfs\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):$(netdev):off panic=1\0" \ - "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip;bootm $(kernel_addr) " \ - "$(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs " \ - "addip;bootm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "devno=5\0" \ + "hostname=V38B_$(devno)\0" \ + "ipaddr=10.100.99.$(devno)\0" \ + "netmask=255.255.0.0\0" \ + "serverip=10.100.10.90\0" \ + "gatewayip=10.100.254.254\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=mpc5200/uImage\0" \ + "bootcmd=run net_nfs\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):" \ + "$(netmask):$(hostname):$(netdev):off panic=1\0" \ + "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip;bootm $(kernel_addr) " \ + "$(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs " \ + "addip;bootm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "" #define CONFIG_BOOTCOMMAND "run net_nfs" @@ -196,13 +196,13 @@ */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_CFI_AMD_RESET 1 +#define CFG_FLASH_CFI_AMD_RESET 1 #define CFG_FLASH_BASE 0xFF000000 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */ #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ /* * Environment settings @@ -243,7 +243,7 @@ */ #define CONFIG_MPC5xxx_FEC 1 #define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 +#define CONFIG_MII 1 /* * GPIO configuration @@ -307,12 +307,12 @@ *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ -#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_RESET /* reset for ide supported */ #define CONFIG_IDE_PREINIT #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ @@ -331,13 +331,13 @@ /* Offset for alternate registers */ #define CFG_ATA_ALT_OFFSET (0x005C) -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 -/* Status LED */ +/* Status LED */ -#define CONFIG_STATUS_LED /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ +#define CONFIG_STATUS_LED /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ #define CFG_LED_BASE (0xf0000600 + 0x70) /* Timer 7 GPIO */ From 73652699dd224dffb5cd8cca24d767bed02d7a28 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 20 Oct 2006 12:02:59 +0200 Subject: [PATCH 09/14] Coding style cleanup --- common/usb_storage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/usb_storage.c b/common/usb_storage.c index 69ecf18784..06ea99b2f1 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -932,8 +932,8 @@ static void usb_bin_fixup(struct usb_device_descriptor descriptor, const unsigned char max_vendor_len = 40; const unsigned char max_product_len = 20; if (descriptor.idVendor == 0x0424 && descriptor.idProduct == 0x223a) { - strncpy(vendor, "SMSC", max_vendor_len); - strncpy(product, "Flash Media Cntrller", max_product_len); + strncpy ((char *)vendor, "SMSC", max_vendor_len); + strncpy ((char *)product, "Flash Media Cntrller", max_product_len); } } #endif /* CONFIG_USB_BIN_FIXUP */ From 43a2b0e76a56995f17e1b7628c192ebafe6051ee Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 20 Oct 2006 14:28:52 +0200 Subject: [PATCH 10/14] Add board/cpu specific NAND chip select function to 440 NDFC Based on idea and implementation from Jeff Mann Patch by Stefan Roese, 20 Oct 2006 --- CHANGELOG | 4 ++++ common/cmd_nand.c | 8 ++++++++ cpu/ppc4xx/ndfc.c | 39 ++++++++++++++++++++++++++------------- drivers/nand/nand.c | 9 ++++++++- include/configs/sequoia.h | 15 ++++++++------- include/nand.h | 4 ++++ 6 files changed, 58 insertions(+), 21 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 71096e875f..6ff1f9b37e 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -7,6 +7,10 @@ Changes since U-Boot 1.1.4: * Add (preliminary) support for V38B board +* Add board/cpu specific NAND chip select function to 440 NDFC + Based on idea and implementation from Jeff Mann + Patch by Stefan Roese, 20 Oct 2006 + * PPC405EP: Add support for board configuration of CPC0_PCI register This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE* Patch by Tolunay Orkun, 07 Apr 2006 diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 7042a9c226..4fb3b65960 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -178,6 +178,14 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf("Device %d: %s", dev, nand_info[dev].name); puts("... is now current device\n"); nand_curr_device = dev; + +#ifdef CFG_NAND_SELECT_DEVICE + /* + * Select the chip in the board/cpu specific driver + */ + board_nand_select_device(nand_info[dev].priv, dev); +#endif + return 0; } diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c index 183ab5ef16..2c44111da6 100644 --- a/cpu/ppc4xx/ndfc.c +++ b/cpu/ppc4xx/ndfc.c @@ -66,7 +66,7 @@ static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd) static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; if (hwctl & 0x1) out8(base + NDFC_CMD, byte); @@ -79,7 +79,7 @@ static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte) static u_char ndfc_read_byte(struct mtd_info *mtdinfo) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; return (in8(base + NDFC_DATA)); } @@ -87,7 +87,7 @@ static u_char ndfc_read_byte(struct mtd_info *mtdinfo) static int ndfc_dev_ready(struct mtd_info *mtdinfo) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY)) ; @@ -111,30 +111,30 @@ static int ndfc_dev_ready(struct mtd_info *mtdinfo) static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; uint32_t *p = (uint32_t *) buf; - for(;len > 0; len -= 4) + for (;len > 0; len -= 4) *p++ = in32(base + NDFC_DATA); } static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; uint32_t *p = (uint32_t *) buf; - for(; len > 0; len -= 4) + for (; len > 0; len -= 4) out32(base + NDFC_DATA, *p++); } static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; uint32_t *p = (uint32_t *) buf; - for(; len > 0; len -= 4) + for (; len > 0; len -= 4) if (*p++ != in32(base + NDFC_DATA)) return -1; @@ -142,8 +142,20 @@ static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len } #endif /* #ifndef CONFIG_NAND_SPL */ +void board_nand_select_device(struct nand_chip *nand, int chip) +{ + ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc; + + /* Set NandFlash Core Configuration Register */ + /* 1col x 2 rows */ + out32(base + NDFC_CCR, 0x00000000 | (chip << 24)); +} + void board_nand_init(struct nand_chip *nand) { + int chip = (ulong)nand->IO_ADDR_W & 0x00000003; + ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc; + nand->eccmode = NAND_ECC_SOFT; nand->hwcontrol = ndfc_hwcontrol; @@ -166,10 +178,11 @@ void board_nand_init(struct nand_chip *nand) mtebc(pb0ap, CFG_EBC_PB0AP); #endif - /* Set NandFlash Core Configuration Register */ - /* Chip select 3, 1col x 2 rows */ - out32(CFG_NAND_BASE + NDFC_CCR, 0x00000000 | (CFG_NAND_CS << 24)); - out32(CFG_NAND_BASE + NDFC_BCFG0 + (CFG_NAND_CS << 2), 0x80002222); + /* + * Select required NAND chip in NDFC + */ + board_nand_select_device(nand, chip); + out32(base + NDFC_BCFG0 + (chip << 2), 0x80002222); } #endif diff --git a/drivers/nand/nand.c b/drivers/nand/nand.c index e1781fcbbf..3899045a72 100644 --- a/drivers/nand/nand.c +++ b/drivers/nand/nand.c @@ -66,8 +66,15 @@ void nand_init(void) size += nand_info[i].size; if (nand_curr_device == -1) nand_curr_device = i; -} + } printf("%lu MiB\n", size / (1024 * 1024)); + +#ifdef CFG_NAND_SELECT_DEVICE + /* + * Select the chip in the board/cpu specific driver + */ + board_nand_select_device(nand_info[nand_curr_device].priv, nand_curr_device); +#endif } #endif diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index f67fd9163d..3a76315b44 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -134,13 +134,6 @@ #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) #endif -/*----------------------------------------------------------------------- - * NAND FLASH - *----------------------------------------------------------------------*/ -#define CFG_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CFG_NAND_BASE CFG_NAND_ADDR - /* * IPL (Initial Program Loader, integrated inside CPU) * Will load first 4k from NAND (SPL) into cache and execute it from there. @@ -405,6 +398,14 @@ #define CFG_EBC_PB2AP 0x24814580 #define CFG_EBC_PB2CR (CFG_CPLD | 0x38000) +/*----------------------------------------------------------------------- + * NAND FLASH + *----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ + /*----------------------------------------------------------------------- * Cache Configuration *----------------------------------------------------------------------*/ diff --git a/include/nand.h b/include/nand.h index 5c7311fd50..23493f7e98 100644 --- a/include/nand.h +++ b/include/nand.h @@ -117,4 +117,8 @@ int nand_lock( nand_info_t *meminfo, int tight ); int nand_unlock( nand_info_t *meminfo, ulong start, ulong length ); int nand_get_lock_status(nand_info_t *meminfo, ulong offset); +#ifdef CFG_NAND_SELECT_DEVICE +void board_nand_select_device(struct nand_chip *nand, int chip); +#endif + #endif From 6a0766ed22b8f65ac9e740a43aed36e35ea8bca5 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 20 Oct 2006 15:18:51 +0200 Subject: [PATCH 11/14] Update CHANGELOG --- CHANGELOG | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 6ff1f9b37e..51af5e6ab2 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,15 +2,15 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Add board/cpu specific NAND chip select function to 440 NDFC + Based on idea and implementation from Jeff Mann + Patch by Stefan Roese, 20 Oct 2006 + * Make 4xx bootup message shorter on 440EPx/GRx platforms Patch by Stefan Roese, 18 Oct 2006 * Add (preliminary) support for V38B board -* Add board/cpu specific NAND chip select function to 440 NDFC - Based on idea and implementation from Jeff Mann - Patch by Stefan Roese, 20 Oct 2006 - * PPC405EP: Add support for board configuration of CPC0_PCI register This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE* Patch by Tolunay Orkun, 07 Apr 2006 From f641471498ddda011f95a840c09907d75259b70a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 20 Oct 2006 15:51:21 +0200 Subject: [PATCH 12/14] MCC200: Fix uninitialized variable problem in LCD driver --- CHANGELOG | 2 ++ common/lcd.c | 7 +++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 51af5e6ab2..7f0b6121ae 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* MCC200: Fix uninitialized variable problem in LCD driver + * Add board/cpu specific NAND chip select function to 440 NDFC Based on idea and implementation from Jeff Mann Patch by Stefan Roese, 20 Oct 2006 diff --git a/common/lcd.c b/common/lcd.c index df31ca9b8c..eaed2abd80 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -578,7 +578,9 @@ void bitmap_plot (int x, int y) */ int lcd_display_bitmap(ulong bmp_image, int x, int y) { +#if !defined(CONFIG_MCC200) ushort *cmap; +#endif ushort i, j; uchar *fb; bmp_image_t *bmp=(bmp_image_t *)bmp_image; @@ -624,13 +626,13 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) debug ("Display-bmp: %d x %d with %d colors\n", (int)width, (int)height, (int)colors); +#if !defined(CONFIG_MCC200) + /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */ if (bpix==8) { #if defined(CONFIG_PXA250) cmap = (ushort *)fbi->palette; #elif defined(CONFIG_MPC823) cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]); -#elif defined(CONFIG_MCC200) - /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */ #else # error "Don't know location of color map" #endif @@ -654,6 +656,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) #endif } } +#endif /* * BMP format for Monochrome assumes that the state of a From f836e4146088a46d9cd18bbd2f36447ea63e039c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 20 Oct 2006 16:12:14 +0200 Subject: [PATCH 13/14] Fix compile problem in include/configs/ep82xxm.h (must have never been tested before!) --- CHANGELOG | 3 +++ include/configs/ep82xxm.h | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/CHANGELOG b/CHANGELOG index 7f0b6121ae..6983b68931 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fix compile problem in include/configs/ep82xxm.h + (must have never been tested before!) + * MCC200: Fix uninitialized variable problem in LCD driver * Add board/cpu specific NAND chip select function to 440 NDFC diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h index 5d7bed611a..372b10c623 100644 --- a/include/configs/ep82xxm.h +++ b/include/configs/ep82xxm.h @@ -28,7 +28,7 @@ #define CONFIG_MPC8260 #define CPU_ID_STR "MPC8270" -#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board /* +#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */ /* 256MB SDRAM / 64MB FLASH */ #undef DEBUG From ba999c531ed16ec749b2b6f4b0133cee38842b91 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 20 Oct 2006 17:54:33 +0200 Subject: [PATCH 14/14] Cleanup compile warnings. Prepare for release 1.1.5 --- CHANGELOG | 4 +++- Makefile | 2 +- board/ep82xxm/ep82xxm.c | 2 -- common/miiphybb.c | 6 +++--- cpu/ppc4xx/cpu.c | 6 +++--- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 6983b68931..727a7b691d 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,7 +1,9 @@ ====================================================================== -Changes since U-Boot 1.1.4: +Changes for U-Boot 1.1.5: ====================================================================== +* Cleanup compile warnings. Prepare for release 1.1.5 + * Fix compile problem in include/configs/ep82xxm.h (must have never been tested before!) diff --git a/Makefile b/Makefile index 37769d40cc..9203494796 100644 --- a/Makefile +++ b/Makefile @@ -23,7 +23,7 @@ VERSION = 1 PATCHLEVEL = 1 -SUBLEVEL = 4 +SUBLEVEL = 5 EXTRAVERSION = U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) VERSION_FILE = $(obj)include/version_autogenerated.h diff --git a/board/ep82xxm/ep82xxm.c b/board/ep82xxm/ep82xxm.c index 35e644df8c..fe3f78e738 100644 --- a/board/ep82xxm/ep82xxm.c +++ b/board/ep82xxm/ep82xxm.c @@ -227,8 +227,6 @@ long int initdram(int board_type) #ifndef CFG_RAMBOOT volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; - vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE; - uchar c = 0xFF; uint psdmr = CFG_PSDMR; int i; diff --git a/common/miiphybb.c b/common/miiphybb.c index adb697ca6b..537c15d29b 100644 --- a/common/miiphybb.c +++ b/common/miiphybb.c @@ -41,7 +41,7 @@ static void miiphy_pre (char read, unsigned char addr, unsigned char reg) { int j; /* counter */ -#ifndef CONFIG_EP8248 +#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); #endif @@ -126,7 +126,7 @@ int bb_miiphy_read (char *devname, unsigned char addr, { short rdreg; /* register working value */ int j; /* counter */ -#ifndef CONFIG_EP8248 +#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); #endif @@ -193,7 +193,7 @@ int bb_miiphy_write (char *devname, unsigned char addr, unsigned char reg, unsigned short value) { int j; /* counter */ -#ifndef CONFIG_EP8248 +#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); #endif diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 6badfb1b24..f4a7208c8f 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -190,9 +190,9 @@ int checkcpu (void) uint pvr = get_pvr(); ulong clock = gd->cpu_clk; char buf[32]; - char addstr[64] = ""; #if !defined(CONFIG_IOP480) + char addstr[64] = ""; sys_info_t sys_info; puts ("CPU: "); @@ -362,8 +362,8 @@ int checkcpu (void) #if defined(SDR0_PINSTP_SHIFT) printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A'); printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]); -#endif -#endif +#endif /* SDR0_PINSTP_SHIFT */ +#endif /* I2C_BOOTROM */ #if defined(CONFIG_PCI) printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");