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Merge branch 'master' of git://git.denx.de/u-boot-uniphier

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This commit is contained in:
Tom Rini 2016-10-29 17:15:24 -04:00
commit 9f375f655f
19 changed files with 876 additions and 429 deletions
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3
arch/arm/mach-uniphier/Kconfig
View File

@ -99,7 +99,8 @@ config CMD_PINMON
config CMD_DDRPHY_DUMP
bool "Enable dump command of DDR PHY parameters"
depends on ARCH_UNIPHIER_LD4 || ARCH_UNIPHIER_PRO4 || ARCH_UNIPHIER_SLD8
depends on ARCH_UNIPHIER_LD4 || ARCH_UNIPHIER_PRO4 || \
ARCH_UNIPHIER_SLD8 || ARCH_UNIPHIER_LD11
default y
help
The command "ddrphy" shows the resulting parameters of DDR PHY

21
arch/arm/mach-uniphier/board_late_init.c
View File

@ -1,5 +1,7 @@
/*
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2014 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -28,15 +30,12 @@ static void nand_denali_wp_disable(void)
#endif
}
#define VENDOR_PREFIX "socionext,"
#define DTB_FILE_PREFIX "uniphier-"
static int uniphier_set_fdt_file(void)
{
DECLARE_GLOBAL_DATA_PTR;
const char *compat;
char dtb_name[256];
int buf_len = 256;
int buf_len = sizeof(dtb_name);
if (getenv("fdt_file"))
return 0; /* do nothing if it is already set */
@ -45,15 +44,13 @@ static int uniphier_set_fdt_file(void)
if (!compat)
return -EINVAL;
if (strncmp(compat, VENDOR_PREFIX, strlen(VENDOR_PREFIX)))
/* rip off the vendor prefix "socionext," */
compat = strchr(compat, ',');
if (!compat)
return -EINVAL;
compat++;
compat += strlen(VENDOR_PREFIX);
strncat(dtb_name, DTB_FILE_PREFIX, buf_len);
buf_len -= strlen(DTB_FILE_PREFIX);
strncat(dtb_name, compat, buf_len);
strncpy(dtb_name, compat, buf_len);
buf_len -= strlen(compat);
strncat(dtb_name, ".dtb", buf_len);

19
arch/arm/mach-uniphier/clk/clk-ld11.c
View File

@ -5,17 +5,20 @@
*/
#include <common.h>
#include <spl.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include "../boot-mode/boot-device.h"
#include "../init.h"
#include "../sc64-regs.h"
#include "../sg-regs.h"
void uniphier_ld11_clk_init(void)
{
if (readl(SG_PINMON0) & BIT(27)) {
/* if booted without stand-by MPU */
/* if booted from a device other than USB, without stand-by MPU */
if ((readl(SG_PINMON0) & BIT(27)) &&
spl_boot_device_raw() != BOOT_DEVICE_USB) {
writel(1, SG_ETPHYPSHUT);
writel(1, SG_ETPHYCNT);
@ -25,4 +28,14 @@ void uniphier_ld11_clk_init(void)
writel(3, SG_ETPHYPSHUT);
writel(7, SG_ETPHYCNT);
}
#ifdef CONFIG_USB_EHCI
{
/* FIXME: the current clk driver can not handle parents */
u32 tmp;
tmp = readl(SC_CLKCTRL4);
tmp |= SC_CLKCTRL4_MIO | SC_CLKCTRL4_STDMAC;
writel(tmp, SC_CLKCTRL4);
}
#endif
}

9
arch/arm/mach-uniphier/clk/dpll-ld20.c
View File

@ -11,12 +11,9 @@
int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd)
{
unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags);
unsigned int dram_freq = bd->dram_freq;
uniphier_ld20_sscpll_init(SC_DPLL0CTRL, dram_freq, dpll_ssc_rate, 2);
uniphier_ld20_sscpll_init(SC_DPLL1CTRL, dram_freq, dpll_ssc_rate, 2);
uniphier_ld20_sscpll_init(SC_DPLL2CTRL, dram_freq, dpll_ssc_rate, 2);
uniphier_ld20_sscpll_init(SC_DPLL0CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
uniphier_ld20_sscpll_init(SC_DPLL1CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
uniphier_ld20_sscpll_init(SC_DPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
return 0;
}

2
arch/arm/mach-uniphier/clk/pll-base-ld20.c
View File

@ -67,8 +67,6 @@ int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)
if (!base)
return -ENOMEM;
mdelay(1);
tmp = readl(base); /* SSCPLLCTRL */
tmp |= SC_PLLCTRL_SSC_EN;
writel(tmp, base);

15
arch/arm/mach-uniphier/clk/pll-ld20.c
View File

@ -13,8 +13,6 @@
int uniphier_ld20_pll_init(const struct uniphier_board_data *bd)
{
unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags);
uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
/* do nothing for SPLL */
uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
@ -24,11 +22,14 @@ int uniphier_ld20_pll_init(const struct uniphier_board_data *bd)
mdelay(1);
if (dpll_ssc_rate > 0) {
uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
}
uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL);
uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_GPPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);

232
arch/arm/mach-uniphier/dram/cmd_ddrphy.c
View File

@ -22,89 +22,107 @@
/* field separator */
#define FS " "
static unsigned long uniphier_ld4_base[] = {
0x5bc01000,
0x5be01000,
0 /* sentinel */
#define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
struct phy_param {
resource_size_t base;
unsigned int nr_dx;
};
static unsigned long uniphier_pro4_base[] = {
0x5bc01000,
0x5be01000,
0 /* sentinel */
static const struct phy_param uniphier_ld4_phy_param[] = {
{ .base = 0x5bc01000, .nr_dx = 2, },
{ .base = 0x5be01000, .nr_dx = 2, },
{ /* sentinel */ }
};
static unsigned long uniphier_sld8_base[] = {
0x5bc01000,
0x5be01000,
0 /* sentinel */
static const struct phy_param uniphier_pro4_phy_param[] = {
{ .base = 0x5bc01000, .nr_dx = 2, },
{ .base = 0x5bc02000, .nr_dx = 2, },
{ .base = 0x5be01000, .nr_dx = 2, },
{ .base = 0x5be02000, .nr_dx = 2, },
{ /* sentinel */ }
};
static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index)
static const struct phy_param uniphier_sld8_phy_param[] = {
{ .base = 0x5bc01000, .nr_dx = 2, },
{ .base = 0x5be01000, .nr_dx = 2, },
{ /* sentinel */ }
};
static const struct phy_param uniphier_ld11_phy_param[] = {
{ .base = 0x5bc01000, .nr_dx = 4, },
{ /* sentinel */ }
};
static void print_bdl(void __iomem *reg, int n)
{
return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f;
u32 val = readl(reg);
int i;
for (i = 0; i < n; i++)
printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f);
}
static void dump_loop(unsigned long *base,
void (*callback)(struct ddrphy_datx8 __iomem *))
static void dump_loop(const struct phy_param *phy_param,
void (*callback)(void __iomem *))
{
struct ddrphy __iomem *phy;
void __iomem *phy_base, *dx_base;
int p, dx;
for (p = 0; *base; base++, p++) {
phy = ioremap(*base, SZ_4K);
for (p = 0; phy_param->base; phy_param++, p++) {
phy_base = ioremap(phy_param->base, SZ_4K);
dx_base = phy_base + PHY_DX_BASE;
for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
for (dx = 0; dx < phy_param->nr_dx; dx++) {
printf("PHY%dDX%d:", p, dx);
(*callback)(&phy->dx[dx]);
(*callback)(dx_base);
dx_base += PHY_DX_STRIDE;
printf("\n");
}
iounmap(phy);
iounmap(phy_base);
}
}
static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx)
static void __wbdl_dump(void __iomem *dx_base)
{
int i;
print_bdl(dx_base + PHY_DX_BDLR0, 5);
print_bdl(dx_base + PHY_DX_BDLR1, 5);
for (i = 0; i < 10; i++)
printf(FS PRINTF_FORMAT, read_bdl(dx, i));
printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
printf(FS "(+" PRINTF_FORMAT ")",
readl(dx_base + PHY_DX_LCDLR1) & 0xff);
}
static void wbdl_dump(unsigned long *base)
static void wbdl_dump(const struct phy_param *phy_param)
{
printf("\n--- Write Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
dump_loop(base, &__wbdl_dump);
dump_loop(phy_param, &__wbdl_dump);
}
static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
static void __rbdl_dump(void __iomem *dx_base)
{
int i;
print_bdl(dx_base + PHY_DX_BDLR3, 5);
print_bdl(dx_base + PHY_DX_BDLR4, 4);
for (i = 15; i < 24; i++)
printf(FS PRINTF_FORMAT, read_bdl(dx, i));
printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
printf(FS "(+" PRINTF_FORMAT ")",
(readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff);
}
static void rbdl_dump(unsigned long *base)
static void rbdl_dump(const struct phy_param *phy_param)
{
printf("\n--- Read Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
dump_loop(base, &__rbdl_dump);
dump_loop(phy_param, &__rbdl_dump);
}
static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
static void __wld_dump(void __iomem *dx_base)
{
int rank;
u32 lcdlr0 = readl(&dx->lcdlr[0]);
u32 gtr = readl(&dx->gtr);
u32 lcdlr0 = readl(dx_base + PHY_DX_LCDLR0);
u32 gtr = readl(dx_base + PHY_DX_GTR);
for (rank = 0; rank < 4; rank++) {
u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
@ -115,19 +133,19 @@ static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
}
}
static void wld_dump(unsigned long *base)
static void wld_dump(const struct phy_param *phy_param)
{
printf("\n--- Write Leveling Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n");
dump_loop(base, &__wld_dump);
dump_loop(phy_param, &__wld_dump);
}
static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
static void __dqsgd_dump(void __iomem *dx_base)
{
int rank;
u32 lcdlr2 = readl(&dx->lcdlr[2]);
u32 gtr = readl(&dx->gtr);
u32 lcdlr2 = readl(dx_base + PHY_DX_LCDLR2);
u32 gtr = readl(dx_base + PHY_DX_GTR);
for (rank = 0; rank < 4; rank++) {
u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
@ -137,94 +155,108 @@ static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
}
}
static void dqsgd_dump(unsigned long *base)
static void dqsgd_dump(const struct phy_param *phy_param)
{
printf("\n--- DQS Gating Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n");
dump_loop(base, &__dqsgd_dump);
dump_loop(phy_param, &__dqsgd_dump);
}
static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
static void __mdl_dump(void __iomem *dx_base)
{
int i;
u32 mdl = readl(&dx->mdlr);
u32 mdl = readl(dx_base + PHY_DX_MDLR);
for (i = 0; i < 3; i++)
printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
}
static void mdl_dump(unsigned long *base)
static void mdl_dump(const struct phy_param *phy_param)
{
printf("\n--- Master Delay Line ---\n");
printf(" IPRD TPRD MDLD\n");
dump_loop(base, &__mdl_dump);
dump_loop(phy_param, &__mdl_dump);
}
#define REG_DUMP(x) \
{ u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
p - (u32 *)phy, #x, p, readl(p)); }
#define REG_DUMP(x) \
{ int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
printf("%3d: %-10s: %08x : %08x\n", \
ofst >> PHY_REG_SHIFT, #x, \
ptr_to_uint(reg), readl(reg)); }
static void reg_dump(unsigned long *base)
#define DX_REG_DUMP(dx, x) \
{ int ofst = PHY_DX_BASE + PHY_DX_STRIDE * (dx) + \
PHY_DX_## x; \
void __iomem *reg = phy_base + ofst; \
printf("%3d: DX%d%-7s: %08x : %08x\n", \
ofst >> PHY_REG_SHIFT, (dx), #x, \
ptr_to_uint(reg), readl(reg)); }
static void reg_dump(const struct phy_param *phy_param)
{
struct ddrphy __iomem *phy;
int p;
void __iomem *phy_base;
int p, dx;
printf("\n--- DDR PHY registers ---\n");
for (p = 0; *base; base++, p++) {
phy = ioremap(*base, SZ_4K);
for (p = 0; phy_param->base; phy_param++, p++) {
phy_base = ioremap(phy_param->base, SZ_4K);
printf("== PHY%d (base: %p) ==\n", p, phy);
printf("== PHY%d (base: %08x) ==\n", p, ptr_to_uint(phy_base));
printf(" No: Name : Address : Data\n");
REG_DUMP(ridr);
REG_DUMP(pir);
REG_DUMP(pgcr[0]);
REG_DUMP(pgcr[1]);
REG_DUMP(pgsr[0]);
REG_DUMP(pgsr[1]);
REG_DUMP(pllcr);
REG_DUMP(ptr[0]);
REG_DUMP(ptr[1]);
REG_DUMP(ptr[2]);
REG_DUMP(ptr[3]);
REG_DUMP(ptr[4]);
REG_DUMP(acmdlr);
REG_DUMP(acbdlr);
REG_DUMP(dxccr);
REG_DUMP(dsgcr);
REG_DUMP(dcr);
REG_DUMP(dtpr[0]);
REG_DUMP(dtpr[1]);
REG_DUMP(dtpr[2]);
REG_DUMP(mr0);
REG_DUMP(mr1);
REG_DUMP(mr2);
REG_DUMP(mr3);
REG_DUMP(dx[0].gcr);
REG_DUMP(dx[0].gtr);
REG_DUMP(dx[1].gcr);
REG_DUMP(dx[1].gtr);
REG_DUMP(RIDR);
REG_DUMP(PIR);
REG_DUMP(PGCR0);
REG_DUMP(PGCR1);
REG_DUMP(PGSR0);
REG_DUMP(PGSR1);
REG_DUMP(PLLCR);
REG_DUMP(PTR0);
REG_DUMP(PTR1);
REG_DUMP(PTR2);
REG_DUMP(PTR3);
REG_DUMP(PTR4);
REG_DUMP(ACMDLR);
REG_DUMP(ACBDLR);
REG_DUMP(DXCCR);
REG_DUMP(DSGCR);
REG_DUMP(DCR);
REG_DUMP(DTPR0);
REG_DUMP(DTPR1);
REG_DUMP(DTPR2);
REG_DUMP(MR0);
REG_DUMP(MR1);
REG_DUMP(MR2);
REG_DUMP(MR3);
iounmap(phy);
for (dx = 0; dx < phy_param->nr_dx; dx++) {
DX_REG_DUMP(dx, GCR);
DX_REG_DUMP(dx, GTR);
}
iounmap(phy_base);
}
}
static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *cmd = argv[1];
unsigned long *base;
const struct phy_param *phy_param;
switch (uniphier_get_soc_type()) {
case SOC_UNIPHIER_LD4:
base = uniphier_ld4_base;
phy_param = uniphier_ld4_phy_param;
break;
case SOC_UNIPHIER_PRO4:
base = uniphier_pro4_base;
phy_param = uniphier_pro4_phy_param;
break;
case SOC_UNIPHIER_SLD8:
base = uniphier_sld8_base;
phy_param = uniphier_sld8_phy_param;
break;
case SOC_UNIPHIER_LD11:
phy_param = uniphier_ld11_phy_param;
break;
default:
printf("unsupported SoC\n");
@ -235,22 +267,22 @@ static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
cmd = "all";
if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
wbdl_dump(base);
wbdl_dump(phy_param);
if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
rbdl_dump(base);
rbdl_dump(phy_param);
if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
wld_dump(base);
wld_dump(phy_param);
if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
dqsgd_dump(base);
dqsgd_dump(phy_param);
if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
mdl_dump(base);
mdl_dump(phy_param);
if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
reg_dump(base);
reg_dump(phy_param);
return CMD_RET_SUCCESS;
}

17
arch/arm/mach-uniphier/dram/ddrphy-init.h Normal file
View File

@ -0,0 +1,17 @@
/*
* Copyright (C) 2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_DDRPHY_INIT_H
#define ARCH_DDRPHY_INTT_H
#include <linux/compiler.h>
#include <linux/types.h>
int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus);
void ddrphy_prepare_training(void __iomem *phy_base, int rank);
int ddrphy_training(void __iomem *phy_base);
#endif /* ARCH_DDRPHY_INT_H */

50
arch/arm/mach-uniphier/dram/ddrphy-ld4.c
View File

@ -1,14 +1,15 @@
/*
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2014 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/types.h>
#include <linux/io.h>
#include "ddrphy-init.h"
#include "ddrphy-regs.h"
enum dram_freq {
@ -27,8 +28,7 @@ static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8};
static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71};
static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298};
int uniphier_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq,
bool ddr3plus)
int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus)
{
enum dram_freq freq_e;
u32 tmp;
@ -45,34 +45,34 @@ int uniphier_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq,
return -EINVAL;
}
writel(0x0300c473, &phy->pgcr[1]);
writel(ddrphy_ptr0[freq_e], &phy->ptr[0]);
writel(ddrphy_ptr1[freq_e], &phy->ptr[1]);
writel(0x00083DEF, &phy->ptr[2]);
writel(ddrphy_ptr3[freq_e], &phy->ptr[3]);
writel(ddrphy_ptr4[freq_e], &phy->ptr[4]);
writel(0xF004001A, &phy->dsgcr);
writel(0x0300c473, phy_base + PHY_PGCR1);
writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0);
writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1);
writel(0x00083DEF, phy_base + PHY_PTR2);
writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3);
writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4);
writel(0xF004001A, phy_base + PHY_DSGCR);
/* change the value of the on-die pull-up/pull-down registors */
tmp = readl(&phy->dxccr);
tmp = readl(phy_base + PHY_DXCCR);
tmp &= ~0x0ee0;
tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
writel(tmp, &phy->dxccr);
tmp |= PHY_DXCCR_DQSNRES_688_OHM | PHY_DXCCR_DQSRES_688_OHM;
writel(tmp, phy_base + PHY_DXCCR);
writel(0x0000040B, &phy->dcr);
writel(ddrphy_dtpr0[freq_e], &phy->dtpr[0]);
writel(ddrphy_dtpr1[freq_e], &phy->dtpr[1]);
writel(ddrphy_dtpr2[freq_e], &phy->dtpr[2]);
writel(ddrphy_mr0[freq_e], &phy->mr0);
writel(0x00000006, &phy->mr1);
writel(ddrphy_mr2[freq_e], &phy->mr2);
writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);
writel(0x0000040B, phy_base + PHY_DCR);
writel(ddrphy_dtpr0[freq_e], phy_base + PHY_DTPR0);
writel(ddrphy_dtpr1[freq_e], phy_base + PHY_DTPR1);
writel(ddrphy_dtpr2[freq_e], phy_base + PHY_DTPR2);
writel(ddrphy_mr0[freq_e], phy_base + PHY_MR0);
writel(0x00000006, phy_base + PHY_MR1);
writel(ddrphy_mr2[freq_e], phy_base + PHY_MR2);
writel(ddr3plus ? 0x00000800 : 0x00000000, phy_base + PHY_MR3);
while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
;
writel(0x0300C473, &phy->pgcr[1]);
writel(0x0000005D, &phy->zq[0].cr[1]);
writel(0x0300C473, phy_base + PHY_PGCR1);
writel(0x0000005D, phy_base + PHY_ZQ_BASE + PHY_ZQ_CR1);
return 0;
}

285
arch/arm/mach-uniphier/dram/ddrphy-regs.h
View File

@ -1,7 +1,8 @@
/*
* UniPhier DDR PHY registers
*
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2014 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -9,160 +10,134 @@
#ifndef ARCH_DDRPHY_REGS_H
#define ARCH_DDRPHY_REGS_H
#include <linux/bitops.h>
#include <linux/compiler.h>
#include <linux/types.h>
#define PHY_REG_SHIFT 2
#ifndef __ASSEMBLY__
struct ddrphy {
u32 ridr; /* Revision Identification Register */
u32 pir; /* PHY Initialixation Register */
u32 pgcr[2]; /* PHY General Configuration Register */
u32 pgsr[2]; /* PHY General Status Register */
u32 pllcr; /* PLL Control Register */
u32 ptr[5]; /* PHY Timing Register */
u32 acmdlr; /* AC Master Delay Line Register */
u32 acbdlr; /* AC Bit Delay Line Register */
u32 aciocr; /* AC I/O Configuration Register */
u32 dxccr; /* DATX8 Common Configuration Register */
u32 dsgcr; /* DDR System General Configuration Register */
u32 dcr; /* DRAM Configuration Register */
u32 dtpr[3]; /* DRAM Timing Parameters Register */
u32 mr0; /* Mode Register 0 */
u32 mr1; /* Mode Register 1 */
u32 mr2; /* Mode Register 2 */
u32 mr3; /* Mode Register 3 */
u32 odtcr; /* ODT Configuration Register */
u32 dtcr; /* Data Training Configuration Register */
u32 dtar[4]; /* Data Training Address Register */
u32 dtdr[2]; /* Data Training Data Register */
u32 dtedr[2]; /* Data Training Eye Data Register */
u32 pgcr2; /* PHY General Configuration Register 2 */
u32 rsv0[8]; /* Reserved */
u32 rdimmgcr[2]; /* RDIMM General Configuration Register */
u32 rdimmcr0[2]; /* RDIMM Control Register */
u32 dcuar; /* DCU Address Register */
u32 dcudr; /* DCU Data Register */
u32 dcurr; /* DCU Run Register */
u32 dculr; /* DCU Loop Register */
u32 dcugcr; /* DCU General Configuration Register */
u32 dcutpr; /* DCU Timing Parameters Register */
u32 dcusr[2]; /* DCU Status Register */
u32 rsv1[8]; /* Reserved */
u32 bistrr; /* BIST Run Register */
u32 bistwcr; /* BIST Word Count Register */
u32 bistmskr[3]; /* BIST Mask Register */
u32 bistlsr; /* BIST LFSR Sed Register */
u32 bistar[3]; /* BIST Address Register */
u32 bistudpr; /* BIST User Data Pattern Register */
u32 bistgsr; /* BIST General Status Register */
u32 bistwer; /* BIST Word Error Register */
u32 bistber[4]; /* BIST Bit Error Register */
u32 bistwcsr; /* BIST Word Count Status Register */
u32 bistfwr[3]; /* BIST Fail Word Register */
u32 rsv2[10]; /* Reserved */
u32 gpr[2]; /* General Purpose Register */
struct ddrphy_zq { /* ZQ */
u32 cr[2]; /* Impedance Control Register */
u32 sr[2]; /* Impedance Status Register */
} zq[4];
struct ddrphy_datx8 { /* DATX8 */
u32 gcr; /* General Configuration Register */
u32 gsr[2]; /* General Status Register */
u32 bdlr[5]; /* Bit Delay Line Register */
u32 lcdlr[3]; /* Local Calibrated Delay Line Register */
u32 mdlr; /* Master Delay Line Register */
u32 gtr; /* General Timing Register */
u32 gsr2; /* General Status Register 2 */
u32 rsv[2]; /* Reserved */
} dx[9];
};
#endif /* __ASSEMBLY__ */
#define PIR_INIT BIT(0) /* Initialization Trigger */
#define PIR_ZCAL BIT(1) /* Impedance Calibration */
#define PIR_PLLINIT BIT(4) /* PLL Initialization */
#define PIR_DCAL BIT(5) /* DDL Calibration */
#define PIR_PHYRST BIT(6) /* PHY Reset */
#define PIR_DRAMRST BIT(7) /* DRAM Reset */
#define PIR_DRAMINIT BIT(8) /* DRAM Initialization */
#define PIR_WL BIT(9) /* Write Leveling */
#define PIR_QSGATE BIT(10) /* Read DQS Gate Training */
#define PIR_WLADJ BIT(11) /* Write Leveling Adjust */
#define PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
#define PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
#define PIR_RDEYE BIT(14) /* Read Data Eye Training */
#define PIR_WREYE BIT(15) /* Write Data Eye Training */
#define PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */
#define PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */
#define PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
#define PIR_INITBYP BIT(31) /* Initialization Bypass */
#define PGSR0_IDONE BIT(0) /* Initialization Done */
#define PGSR0_PLDONE BIT(1) /* PLL Lock Done */
#define PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
#define PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
#define PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
#define PGSR0_WLDONE BIT(5) /* Write Leveling Done */
#define PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
#define PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
#define PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
#define PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
#define PGSR0_REDONE BIT(10) /* Read Eye Training Done */
#define PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
#define PGSR0_IERR BIT(16) /* Initialization Error */
#define PGSR0_PLERR BIT(17) /* PLL Lock Error */
#define PGSR0_DCERR BIT(18) /* DDL Calibration Error */
#define PGSR0_ZCERR BIT(19) /* Impedance Calib Error */
#define PGSR0_DIERR BIT(20) /* DRAM Initialization Error */
#define PGSR0_WLERR BIT(21) /* Write Leveling Error */
#define PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
#define PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
#define PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
#define PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
#define PGSR0_REERR BIT(26) /* Read Eye Training Error */
#define PGSR0_WEERR BIT(27) /* Write Eye Training Error */
#define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/
#define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT))
#define PGSR0_APLOCK BIT(31) /* AC PLL Lock */
#define DXCCR_DQSRES_OPEN (0 << 5)
#define DXCCR_DQSRES_688_OHM (1 << 5)
#define DXCCR_DQSRES_611_OHM (2 << 5)
#define DXCCR_DQSRES_550_OHM (3 << 5)
#define DXCCR_DQSRES_500_OHM (4 << 5)
#define DXCCR_DQSRES_458_OHM (5 << 5)
#define DXCCR_DQSRES_393_OHM (6 << 5)
#define DXCCR_DQSRES_344_OHM (7 << 5)
#define DXCCR_DQSNRES_OPEN (0 << 9)
#define DXCCR_DQSNRES_688_OHM (1 << 9)
#define DXCCR_DQSNRES_611_OHM (2 << 9)
#define DXCCR_DQSNRES_550_OHM (3 << 9)
#define DXCCR_DQSNRES_500_OHM (4 << 9)
#define DXCCR_DQSNRES_458_OHM (5 << 9)
#define DXCCR_DQSNRES_393_OHM (6 << 9)
#define DXCCR_DQSNRES_344_OHM (7 << 9)
#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT))
#define DTCR_DTMPR BIT(6) /* Data Training using MPR */
#define DTCR_RANKEN_SHIFT 24 /* Rank Enable */
#define DTCR_RANKEN_MASK (0xf << (DTCR_RANKEN_SHIFT))
#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT))
/* SoC-specific parameters */
#define NR_DATX8_PER_DDRPHY 2
#ifndef __ASSEMBLY__
int uniphier_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq,
bool ddr3plus);
void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
int ddrphy_training(struct ddrphy __iomem *phy);
#endif
#define PHY_RIDR (0x000 << PHY_REG_SHIFT)
#define PHY_PIR (0x001 << PHY_REG_SHIFT)
#define PHY_PIR_INIT BIT(0) /* Initialization Trigger */
#define PHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
#define PHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
#define PHY_PIR_DCAL BIT(5) /* DDL Calibration */
#define PHY_PIR_PHYRST BIT(6) /* PHY Reset */
#define PHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
#define PHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
#define PHY_PIR_WL BIT(9) /* Write Leveling */
#define PHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
#define PHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */
#define PHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
#define PHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
#define PHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */
#define PHY_PIR_WREYE BIT(15) /* Write Data Eye Training */
#define PHY_PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */
#define PHY_PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */
#define PHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
#define PHY_PIR_INITBYP BIT(31) /* Initialization Bypass */
#define PHY_PGCR0 (0x002 << PHY_REG_SHIFT)
#define PHY_PGCR1 (0x003 << PHY_REG_SHIFT)
#define PHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */
#define PHY_PGSR0 (0x004 << PHY_REG_SHIFT)
#define PHY_PGSR0_IDONE BIT(0) /* Initialization Done */
#define PHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */
#define PHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
#define PHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
#define PHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
#define PHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */
#define PHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
#define PHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
#define PHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
#define PHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
#define PHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */
#define PHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
#define PHY_PGSR0_DIERR BIT(20) /* DRAM Initialization Error */
#define PHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */
#define PHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
#define PHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
#define PHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
#define PHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
#define PHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */
#define PHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */
#define PHY_PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/
#define PHY_PGSR0_DTERR (7 << (PHY_PGSR0_DTERR_SHIFT))
#define PHY_PGSR1 (0x005 << PHY_REG_SHIFT)
#define PHY_PGSR1_VTSTOP BIT(30) /* VT Stop (v3-) */
#define PHY_PLLCR (0x006 << PHY_REG_SHIFT)
#define PHY_PTR0 (0x007 << PHY_REG_SHIFT)
#define PHY_PTR1 (0x008 << PHY_REG_SHIFT)
#define PHY_PTR2 (0x009 << PHY_REG_SHIFT)
#define PHY_PTR3 (0x00A << PHY_REG_SHIFT)
#define PHY_PTR4 (0x00B << PHY_REG_SHIFT)
#define PHY_ACMDLR (0x00C << PHY_REG_SHIFT)
#define PHY_ACBDLR (0x00D << PHY_REG_SHIFT)
#define PHY_ACIOCR (0x00E << PHY_REG_SHIFT)
#define PHY_DXCCR (0x00F << PHY_REG_SHIFT)
#define PHY_DXCCR_DQSRES_OPEN (0 << 5)
#define PHY_DXCCR_DQSRES_688_OHM (1 << 5)
#define PHY_DXCCR_DQSRES_611_OHM (2 << 5)
#define PHY_DXCCR_DQSRES_550_OHM (3 << 5)
#define PHY_DXCCR_DQSRES_500_OHM (4 << 5)
#define PHY_DXCCR_DQSRES_458_OHM (5 << 5)
#define PHY_DXCCR_DQSRES_393_OHM (6 << 5)
#define PHY_DXCCR_DQSRES_344_OHM (7 << 5)
#define PHY_DXCCR_DQSNRES_OPEN (0 << 9)
#define PHY_DXCCR_DQSNRES_688_OHM (1 << 9)
#define PHY_DXCCR_DQSNRES_611_OHM (2 << 9)
#define PHY_DXCCR_DQSNRES_550_OHM (3 << 9)
#define PHY_DXCCR_DQSNRES_500_OHM (4 << 9)
#define PHY_DXCCR_DQSNRES_458_OHM (5 << 9)
#define PHY_DXCCR_DQSNRES_393_OHM (6 << 9)
#define PHY_DXCCR_DQSNRES_344_OHM (7 << 9)
#define PHY_DSGCR (0x010 << PHY_REG_SHIFT)
#define PHY_DCR (0x011 << PHY_REG_SHIFT)
#define PHY_DTPR0 (0x012 << PHY_REG_SHIFT)
#define PHY_DTPR1 (0x013 << PHY_REG_SHIFT)
#define PHY_DTPR2 (0x014 << PHY_REG_SHIFT)
#define PHY_MR0 (0x015 << PHY_REG_SHIFT)
#define PHY_MR1 (0x016 << PHY_REG_SHIFT)
#define PHY_MR2 (0x017 << PHY_REG_SHIFT)
#define PHY_MR3 (0x018 << PHY_REG_SHIFT)
#define PHY_ODTCR (0x019 << PHY_REG_SHIFT)
#define PHY_DTCR (0x01A << PHY_REG_SHIFT)
#define PHY_DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
#define PHY_DTCR_DTRANK_MASK (0x3 << (PHY_DTCR_DTRANK_SHIFT))
#define PHY_DTCR_DTMPR BIT(6) /* Data Training using MPR */
#define PHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */
#define PHY_DTCR_RANKEN_MASK (0xf << (PHY_DTCR_RANKEN_SHIFT))
#define PHY_DTAR0 (0x01B << PHY_REG_SHIFT)
#define PHY_DTAR1 (0x01C << PHY_REG_SHIFT)
#define PHY_DTAR2 (0x01D << PHY_REG_SHIFT)
#define PHY_DTAR3 (0x01E << PHY_REG_SHIFT)
#define PHY_DTDR0 (0x01F << PHY_REG_SHIFT)
#define PHY_DTDR1 (0x020 << PHY_REG_SHIFT)
#define PHY_DTEDR0 (0x021 << PHY_REG_SHIFT)
#define PHY_DTEDR1 (0x022 << PHY_REG_SHIFT)
#define PHY_PGCR2 (0x023 << PHY_REG_SHIFT)
#define PHY_GPR0 (0x05E << PHY_REG_SHIFT)
#define PHY_GPR1 (0x05F << PHY_REG_SHIFT)
/* ZQ */
#define PHY_ZQ_BASE (0x060 << PHY_REG_SHIFT)
#define PHY_ZQ_STRIDE (0x004 << PHY_REG_SHIFT)
#define PHY_ZQ_CR0 (0x000 << PHY_REG_SHIFT)
#define PHY_ZQ_CR1 (0x001 << PHY_REG_SHIFT)
#define PHY_ZQ_SR0 (0x002 << PHY_REG_SHIFT)
#define PHY_ZQ_SR1 (0x003 << PHY_REG_SHIFT)
/* DATX8 */
#define PHY_DX_BASE (0x070 << PHY_REG_SHIFT)
#define PHY_DX_STRIDE (0x010 << PHY_REG_SHIFT)
#define PHY_DX_GCR (0x000 << PHY_REG_SHIFT)
#define PHY_DX_GCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
#define PHY_DX_GCR_WLRKEN_MASK (0xf << (PHY_DX_GCR_WLRKEN_SHIFT))
#define PHY_DX_GSR0 (0x001 << PHY_REG_SHIFT)
#define PHY_DX_GSR1 (0x002 << PHY_REG_SHIFT)
#define PHY_DX_BDLR0 (0x003 << PHY_REG_SHIFT)
#define PHY_DX_BDLR1 (0x004 << PHY_REG_SHIFT)
#define PHY_DX_BDLR2 (0x005 << PHY_REG_SHIFT)
#define PHY_DX_BDLR3 (0x006 << PHY_REG_SHIFT)
#define PHY_DX_BDLR4 (0x007 << PHY_REG_SHIFT)
#define PHY_DX_LCDLR0 (0x008 << PHY_REG_SHIFT)
#define PHY_DX_LCDLR1 (0x009 << PHY_REG_SHIFT)
#define PHY_DX_LCDLR2 (0x00A << PHY_REG_SHIFT)
#define PHY_DX_MDLR (0x00B << PHY_REG_SHIFT)
#define PHY_DX_GTR (0x00C << PHY_REG_SHIFT)
#define PHY_DX_GSR2 (0x00D << PHY_REG_SHIFT)
#endif /* ARCH_DDRPHY_REGS_H */

98
arch/arm/mach-uniphier/dram/ddrphy-training.c
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2011-2014 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -8,35 +9,38 @@
#include <linux/err.h>
#include <linux/io.h>
#include "ddrphy-init.h"
#include "ddrphy-regs.h"
void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
/* for LD4, Pro4, sLD8 */
#define NR_DATX8_PER_DDRPHY 2
void ddrphy_prepare_training(void __iomem *phy_base, int rank)
{
void __iomem *dx_base = phy_base + PHY_DX_BASE;
int dx;
u32 __iomem tmp, *p;
u32 tmp;
for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
p = &phy->dx[dx].gcr;
tmp = readl(p);
tmp = readl(dx_base + PHY_DX_GCR);
/* Specify the rank that should be write leveled */
tmp &= ~DXGCR_WLRKEN_MASK;
tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK;
writel(tmp, p);
tmp &= ~PHY_DX_GCR_WLRKEN_MASK;
tmp |= (1 << (PHY_DX_GCR_WLRKEN_SHIFT + rank)) &
PHY_DX_GCR_WLRKEN_MASK;
writel(tmp, dx_base + PHY_DX_GCR);
dx_base += PHY_DX_STRIDE;
}
p = &phy->dtcr;
tmp = readl(p);
tmp = readl(phy_base + PHY_DTCR);
/* Specify the rank used during data bit deskew and eye centering */
tmp &= ~DTCR_DTRANK_MASK;
tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK;
tmp &= ~PHY_DTCR_DTRANK_MASK;
tmp |= (rank << PHY_DTCR_DTRANK_SHIFT) & PHY_DTCR_DTRANK_MASK;
/* Use Multi-Purpose Register for DQS gate training */
tmp |= DTCR_DTMPR;
tmp |= PHY_DTCR_DTMPR;
/* Specify the rank enabled for data-training */
tmp &= ~DTCR_RANKEN_MASK;
tmp |= (1 << (DTCR_RANKEN_SHIFT + rank)) & DTCR_RANKEN_MASK;
writel(tmp, p);
tmp &= ~PHY_DTCR_RANKEN_MASK;
tmp |= (1 << (PHY_DTCR_RANKEN_SHIFT + rank)) & PHY_DTCR_RANKEN_MASK;
writel(tmp, phy_base + PHY_DTCR);
}
struct ddrphy_init_sequence {
@ -49,60 +53,60 @@ struct ddrphy_init_sequence {
static const struct ddrphy_init_sequence init_sequence[] = {
{
"DRAM Initialization",
PIR_DRAMRST | PIR_DRAMINIT,
PGSR0_DIDONE,
PGSR0_DIERR
PHY_PIR_DRAMRST | PHY_PIR_DRAMINIT,
PHY_PGSR0_DIDONE,
PHY_PGSR0_DIERR
},
{
"Write Leveling",
PIR_WL,
PGSR0_WLDONE,
PGSR0_WLERR
PHY_PIR_WL,
PHY_PGSR0_WLDONE,
PHY_PGSR0_WLERR
},
{
"Read DQS Gate Training",
PIR_QSGATE,
PGSR0_QSGDONE,
PGSR0_QSGERR
PHY_PIR_QSGATE,
PHY_PGSR0_QSGDONE,
PHY_PGSR0_QSGERR
},
{
"Write Leveling Adjustment",
PIR_WLADJ,
PGSR0_WLADONE,
PGSR0_WLAERR
PHY_PIR_WLADJ,
PHY_PGSR0_WLADONE,
PHY_PGSR0_WLAERR
},
{
"Read Bit Deskew",
PIR_RDDSKW,
PGSR0_RDDONE,
PGSR0_RDERR
PHY_PIR_RDDSKW,
PHY_PGSR0_RDDONE,
PHY_PGSR0_RDERR
},
{
"Write Bit Deskew",
PIR_WRDSKW,
PGSR0_WDDONE,
PGSR0_WDERR
PHY_PIR_WRDSKW,
PHY_PGSR0_WDDONE,
PHY_PGSR0_WDERR
},
{
"Read Eye Training",
PIR_RDEYE,
PGSR0_REDONE,
PGSR0_REERR
PHY_PIR_RDEYE,
PHY_PGSR0_REDONE,
PHY_PGSR0_REERR
},
{
"Write Eye Training",
PIR_WREYE,
PGSR0_WEDONE,
PGSR0_WEERR
PHY_PIR_WREYE,
PHY_PGSR0_WEDONE,
PHY_PGSR0_WEERR
}
};
int ddrphy_training(struct ddrphy __iomem *phy)
int ddrphy_training(void __iomem *phy_base)
{
int i;
u32 pgsr0;
u32 init_flag = PIR_INIT;
u32 done_flag = PGSR0_IDONE;
u32 init_flag = PHY_PIR_INIT;
u32 done_flag = PHY_PGSR0_IDONE;
int timeout = 50000; /* 50 msec is long enough */
#ifdef DISPLAY_ELAPSED_TIME
ulong start = get_timer(0);
@ -113,7 +117,7 @@ int ddrphy_training(struct ddrphy __iomem *phy)
done_flag |= init_sequence[i].done_flag;
}
writel(init_flag, &phy->pir);
writel(init_flag, phy_base + PHY_PIR);
do {
if (--timeout < 0) {
@ -122,7 +126,7 @@ int ddrphy_training(struct ddrphy __iomem *phy)
return -ETIMEDOUT;
}
udelay(1);
pgsr0 = readl(&phy->pgsr[0]);
pgsr0 = readl(phy_base + PHY_PGSR0);
} while ((pgsr0 & done_flag) != done_flag);
for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {

7
arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h → arch/arm/mach-uniphier/dram/ddruqphy-regs.h
View File

@ -4,8 +4,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _DDRPHY_LD20_REGS_H
#define _DDRPHY_LD20_REGS_H
#ifndef _DDRUQPHY_REGS_H
#define _DDRUQPHY_REGS_H
#include <linux/bitops.h>
@ -15,6 +15,7 @@
#define PHY_MAS_DLY_WIDTH 8
#define PHY_SCL_START (0x40 << (PHY_REG_SHIFT))
#define PHY_SCL_START_GO_DONE BIT(28)
#define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT))
#define PHY_SCL_DATA_1 (0x42 << (PHY_REG_SHIFT))
#define PHY_SCL_LATENCY (0x43 << (PHY_REG_SHIFT))
@ -75,4 +76,4 @@
#define PHY_VREF_TRAINING (0x72 << (PHY_REG_SHIFT))
#define PHY_SCL_GATE_TIMING (0x78 << (PHY_REG_SHIFT))
#endif /* _DDRPHY_LD20_REGS_H */
#endif /* _DDRUQPHY_REGS_H */

410
arch/arm/mach-uniphier/dram/umc-ld11.c
View File

@ -8,11 +8,13 @@
#include <asm/processor.h>
#include "../init.h"
#include "ddrphy-regs.h"
#include "umc64-regs.h"
#define CONFIG_DDR_FREQ 1866
#define DDR_FREQ 1600
#define DRAM_CH_NR 2
#define RANK_BLOCKS_TR 2
enum dram_freq {
DRAM_FREQ_1600M,
@ -25,26 +27,370 @@ enum dram_size {
DRAM_SZ_NR,
};
/* umc */
static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
static u32 umc_cmdctle[DRAM_FREQ_NR] = {0x0078071D};
static u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
static u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
/* PHY */
const int rof_pos_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
const int rof_neg_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
const int rof_pos_shift[RANK_BLOCKS_TR][2] = { {-35, -35}, {-35, -35} };
const int rof_neg_shift[RANK_BLOCKS_TR][2] = { {-17, -17}, {-17, -17} };
const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} };
static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000810};
static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000810};
static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000004};
static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000004};
static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
static u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
/* Register address */
#define PHY_ZQ0CR1 0x00000184
#define PHY_ZQ1CR1 0x00000194
#define PHY_ZQ2CR1 0x000001A4
#define PHY_DX0GCR 0x000001C0
#define PHY_DX0GTR 0x000001F0
#define PHY_DX1GCR 0x00000200
#define PHY_DX1GTR 0x00000230
#define PHY_DX2GCR 0x00000240
#define PHY_DX2GTR 0x00000270
#define PHY_DX3GCR 0x00000280
#define PHY_DX3GTR 0x000002B0
#define PHY_DXMDLR(dx) (0x000001EC + 0x40 * (dx))
#define PHY_DXLCDLR0(dx) (0x000001E0 + 0x40 * (dx))
#define PHY_DXLCDLR1(dx) (0x000001E4 + 0x40 * (dx))
#define PHY_DXLCDLR2(dx) (0x000001E8 + 0x40 * (dx))
#define PHY_DXBDLR1(dx) (0x000001D0 + 0x40 * (dx))
#define PHY_DXBDLR2(dx) (0x000001D4 + 0x40 * (dx))
/* MASK */
#define PHY_ACBD_MASK 0x00FC0000
#define PHY_CK0BD_MASK 0x0000003F
#define PHY_CK1BD_MASK 0x00000FC0
#define PHY_IPRD_MASK 0x000000FF
#define PHY_WLD_MASK(rank) (0xFF << (8 * (rank)))
#define PHY_DQSGD_MASK(rank) (0xFF << (8 * (rank)))
#define PHY_DQSGX_MASK BIT(6)
#define PHY_DSWBD_MASK 0x3F000000 /* bit[29:24] */
#define PHY_DSDQOE_MASK 0x00000FFF
static void ddrphy_maskwritel(u32 data, u32 mask, void *addr)
{
u32 value;
value = (readl(addr) & ~(mask)) | (data & mask);
writel(value, addr);
}
static u32 ddrphy_maskreadl(u32 mask, void *addr)
{
return readl(addr) & mask;
}
/* step of 0.5T for PUB-byte */
static u8 ddrphy_get_mdl(int dx, void __iomem *phy_base)
{
return ddrphy_maskreadl(PHY_IPRD_MASK, phy_base + PHY_DXMDLR(dx));
}
/* Calculating step for PUB-byte */
static int ddrphy_hpstep(int delay, int dx, void __iomem *phy_base)
{
return delay * ddrphy_get_mdl(dx, phy_base) * DDR_FREQ / 1000000;
}
static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
{
u32 tmp;
tmp = readl(phy_base + PHY_PGCR1);
if (enable)
tmp &= ~PHY_PGCR1_INHVT;
else
tmp |= PHY_PGCR1_INHVT;
writel(tmp, phy_base + PHY_PGCR1);
if (!enable) {
while (!(readl(phy_base + PHY_PGSR1) & PHY_PGSR1_VTSTOP))
cpu_relax();
}
}
static void ddrphy_set_ckoffset_qoffset(int delay_ckoffset0, int delay_ckoffset1,
int delay_qoffset, int enable,
void __iomem *phy_base)
{
u8 ck_step0, ck_step1; /* ckoffset_step for clock */
u8 q_step; /* qoffset_step for clock */
int dx;
dx = 2; /* use dx2 in sLD11 */
ck_step0 = ddrphy_hpstep(delay_ckoffset0, dx, phy_base); /* CK-Offset */
ck_step1 = ddrphy_hpstep(delay_ckoffset1, dx, phy_base); /* CK-Offset */
q_step = ddrphy_hpstep(delay_qoffset, dx, phy_base); /* Q-Offset */
ddrphy_vt_ctrl(phy_base, 0);
/* Q->[23:18], CK1->[11:6], CK0->bit[5:0] */
if (enable == 1)
ddrphy_maskwritel((q_step << 18) + (ck_step1 << 6) + ck_step0,
PHY_ACBD_MASK | PHY_CK1BD_MASK | PHY_CK0BD_MASK,
phy_base + PHY_ACBDLR);
ddrphy_vt_ctrl(phy_base, 1);
}
static void ddrphy_set_wl_delay_dx(int dx, int r0_delay, int r1_delay,
int enable, void __iomem *phy_base)
{
int rank;
int delay_wl[4];
u32 wl_mask = 0; /* WriteLeveling's Mask */
u32 wl_value = 0; /* WriteLeveling's Value */
delay_wl[0] = r0_delay & 0xfff;
delay_wl[1] = r1_delay & 0xfff;
delay_wl[2] = 0;
delay_wl[3] = 0;
ddrphy_vt_ctrl(phy_base, 0);
for (rank = 0; rank < 4; rank++) {
wl_mask |= PHY_WLD_MASK(rank);
/* WriteLeveling's delay */
wl_value |= ddrphy_hpstep(delay_wl[rank], dx, phy_base) << (8 * rank);
}
if (enable == 1)
ddrphy_maskwritel(wl_value, wl_mask, phy_base + PHY_DXLCDLR0(dx));
ddrphy_vt_ctrl(phy_base, 1);
}
static void ddrphy_set_dqsg_delay_dx(int dx, int r0_delay, int r1_delay,
int enable, void __iomem *phy_base)
{
int rank;
int delay_dqsg[4];
u32 dqsg_mask = 0; /* DQSGating_LCDL_delay's Mask */
u32 dqsg_value = 0; /* DQSGating_LCDL_delay's Value */
delay_dqsg[0] = r0_delay;
delay_dqsg[1] = r1_delay;
delay_dqsg[2] = 0;
delay_dqsg[3] = 0;
ddrphy_vt_ctrl(phy_base, 0);
for (rank = 0; rank < 4; rank++) {
dqsg_mask |= PHY_DQSGD_MASK(rank);
/* DQSGating's delay */
dqsg_value |= ddrphy_hpstep(delay_dqsg[rank], dx, phy_base) << (8 * rank);
}
if (enable == 1)
ddrphy_maskwritel(dqsg_value, dqsg_mask, phy_base + PHY_DXLCDLR2(dx));
ddrphy_vt_ctrl(phy_base, 1);
}
static void ddrphy_set_dswb_delay_dx(int dx, int delay, int enable, void __iomem *phy_base)
{
u8 dswb_step;
ddrphy_vt_ctrl(phy_base, 0);
dswb_step = ddrphy_hpstep(delay, dx, phy_base); /* DQS-BDL's delay */
if (enable == 1)
ddrphy_maskwritel(dswb_step << 24, PHY_DSWBD_MASK, phy_base + PHY_DXBDLR1(dx));
ddrphy_vt_ctrl(phy_base, 1);
}
static void ddrphy_set_oe_delay_dx(int dx, int dqs_delay, int dq_delay,
int enable, void __iomem *phy_base)
{
u8 dqs_oe_step, dq_oe_step;
u32 wdata;
ddrphy_vt_ctrl(phy_base, 0);
/* OE(DQS,DQ) */
dqs_oe_step = ddrphy_hpstep(dqs_delay, dx, phy_base); /* DQS-oe's delay */
dq_oe_step = ddrphy_hpstep(dq_delay, dx, phy_base); /* DQ-oe's delay */
wdata = ((dq_oe_step<<6) + dqs_oe_step) & 0xFFF;
if (enable == 1)
ddrphy_maskwritel(wdata, PHY_DSDQOE_MASK, phy_base + PHY_DXBDLR2(dx));
ddrphy_vt_ctrl(phy_base, 1);
}
static void ddrphy_ext_dqsgt(void __iomem *phy_base)
{
/* Extend DQSGating_window min:+1T max:+1T */
ddrphy_maskwritel(PHY_DQSGX_MASK, PHY_DQSGX_MASK, phy_base + PHY_DSGCR);
}
static void ddrphy_shift_tof_hws(void __iomem *phy_base, const int shift[][2])
{
int dx, block, byte;
u32 lcdlr1, wdqd;
ddrphy_vt_ctrl(phy_base, 0);
for (block = 0; block < RANK_BLOCKS_TR; block++) {
for (byte = 0; byte < 2; byte++) {
dx = block * 2 + byte;
lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx));
wdqd = lcdlr1 & 0xff;
wdqd = clamp(wdqd + ddrphy_hpstep(shift[block][byte], dx, phy_base),
0U, 0xffU);
lcdlr1 = (lcdlr1 & ~0xff) | wdqd;
writel(lcdlr1, phy_base + PHY_DXLCDLR1(dx));
readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */
}
}
ddrphy_vt_ctrl(phy_base, 1);
}
static void ddrphy_shift_rof_hws(void __iomem *phy_base, const int pos_shift[][2],
const int neg_shift[][2])
{
int dx, block, byte;
u32 lcdlr1, rdqsd, rdqnsd;
ddrphy_vt_ctrl(phy_base, 0);
for (block = 0; block < RANK_BLOCKS_TR; block++) {
for (byte = 0; byte < 2; byte++) {
dx = block * 2 + byte;
lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx));
/* DQS LCDL RDQNSD->[23:16] RDQSD->[15:8] */
rdqsd = (lcdlr1 >> 8) & 0xff;
rdqnsd = (lcdlr1 >> 16) & 0xff;
rdqsd = clamp(rdqsd + ddrphy_hpstep(pos_shift[block][byte], dx, phy_base),
0U, 0xffU);
rdqnsd = clamp(rdqnsd + ddrphy_hpstep(neg_shift[block][byte], dx, phy_base),
0U, 0xffU);
lcdlr1 = (lcdlr1 & ~(0xffff << 8)) | (rdqsd << 8) | (rdqnsd << 16);
readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */
}
}
ddrphy_vt_ctrl(phy_base, 1);
}
static void ddrphy_boot_run_hws(void __iomem *phy_base)
{
/* Hard Training for DIO */
writel(0x0000f401, phy_base + PHY_PIR);
while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
cpu_relax();
}
static void ddrphy_training(void __iomem *phy_base)
{
/* DIO roffset shift before hard training */
ddrphy_shift_rof_hws(phy_base, rof_pos_shift_pre, rof_neg_shift_pre);
/* Hard Training for each CH */
ddrphy_boot_run_hws(phy_base);
/* DIO toffset shift after training */
ddrphy_shift_tof_hws(phy_base, tof_shift);
/* DIO roffset shift after training */
ddrphy_shift_rof_hws(phy_base, rof_pos_shift, rof_neg_shift);
/* Extend DQSGating window min:+1T max:+1T */
ddrphy_ext_dqsgt(phy_base);
}
static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq)
{
writel(0x40000000, phy_base + PHY_PIR);
writel(0x0300C4F1, phy_base + PHY_PGCR1);
writel(0x0C807D04, phy_base + PHY_PTR0);
writel(0x27100578, phy_base + PHY_PTR1);
writel(0x00083DEF, phy_base + PHY_PTR2);
writel(0x12061A80, phy_base + PHY_PTR3);
writel(0x08027100, phy_base + PHY_PTR4);
writel(0x9D9CBB66, phy_base + PHY_DTPR0);
writel(0x1a878400, phy_base + PHY_DTPR1);
writel(0x50025200, phy_base + PHY_DTPR2);
writel(0xF004641A, phy_base + PHY_DSGCR);
writel(0x0000040B, phy_base + PHY_DCR);
writel(0x00000d71, phy_base + PHY_MR0);
writel(0x00000006, phy_base + PHY_MR1);
writel(0x00000098, phy_base + PHY_MR2);
writel(0x00000000, phy_base + PHY_MR3);
while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
cpu_relax();
writel(0x00000059, phy_base + PHY_ZQ0CR1);
writel(0x00000019, phy_base + PHY_ZQ1CR1);
writel(0x00000019, phy_base + PHY_ZQ2CR1);
writel(0x30FC6C20, phy_base + PHY_PGCR2);
ddrphy_set_ckoffset_qoffset(119, 0, 0, 1, phy_base);
ddrphy_set_wl_delay_dx(0, 220, 220, 1, phy_base);
ddrphy_set_wl_delay_dx(1, 160, 160, 1, phy_base);
ddrphy_set_wl_delay_dx(2, 190, 190, 1, phy_base);
ddrphy_set_wl_delay_dx(3, 150, 150, 1, phy_base);
ddrphy_set_dqsg_delay_dx(0, 750, 750, 1, phy_base);
ddrphy_set_dqsg_delay_dx(1, 750, 750, 1, phy_base);
ddrphy_set_dqsg_delay_dx(2, 750, 750, 1, phy_base);
ddrphy_set_dqsg_delay_dx(3, 750, 750, 1, phy_base);
ddrphy_set_dswb_delay_dx(0, 0, 1, phy_base);
ddrphy_set_dswb_delay_dx(1, 0, 1, phy_base);
ddrphy_set_dswb_delay_dx(2, 0, 1, phy_base);
ddrphy_set_dswb_delay_dx(3, 0, 1, phy_base);
ddrphy_set_oe_delay_dx(0, 0, 0, 1, phy_base);
ddrphy_set_oe_delay_dx(1, 0, 0, 1, phy_base);
ddrphy_set_oe_delay_dx(2, 0, 0, 1, phy_base);
ddrphy_set_oe_delay_dx(3, 0, 0, 1, phy_base);
writel(0x44000E81, phy_base + PHY_DX0GCR);
writel(0x44000E81, phy_base + PHY_DX1GCR);
writel(0x44000E81, phy_base + PHY_DX2GCR);
writel(0x44000E81, phy_base + PHY_DX3GCR);
writel(0x00055002, phy_base + PHY_DX0GTR);
writel(0x00055002, phy_base + PHY_DX1GTR);
writel(0x00055010, phy_base + PHY_DX2GTR);
writel(0x00055010, phy_base + PHY_DX3GTR);
writel(0x930035C7, phy_base + PHY_DTCR);
writel(0x00000003, phy_base + PHY_PIR);
readl(phy_base + PHY_PIR);
while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
cpu_relax();
writel(0x00000181, phy_base + PHY_PIR);
readl(phy_base + PHY_PIR);
while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
cpu_relax();
writel(0x44181884, phy_base + PHY_DXCCR);
writel(0x00000001, phy_base + PHY_GPR1);
}
/* UMC */
static const u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060B0B1C};
static const u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x27201806};
static const u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00120B04};
static const u32 umc_cmdctle[DRAM_FREQ_NR] = {0x00680607};
static const u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
static const u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
static const u32 umc_rdatactl[DRAM_FREQ_NR] = {0x00000810};
static const u32 umc_wdatactl[DRAM_FREQ_NR] = {0x00000004};
static const u32 umc_odtctl[DRAM_FREQ_NR] = {0x02000002};
static const u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
static const u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
unsigned long size, int ch)
{
/* Wait for PHY Init Complete */
writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
@ -52,14 +398,14 @@ static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF);
writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG);
writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D0);
writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D1);
writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D0);
writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D1);
writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D0);
writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D1);
writel(0x00000003, dc_base + UMC_ACSSETA);
writel(0x00000103, dc_base + UMC_FLOWCTLG);
@ -93,6 +439,7 @@ int uniphier_ld11_umc_init(const struct uniphier_board_data *bd)
{
void __iomem *um_base = (void __iomem *)0x5B800000;
void __iomem *umc_ch_base = (void __iomem *)0x5BC00000;
void __iomem *phy_base = (void __iomem *)0x5BC01000;
enum dram_freq freq;
int ch, ret;
@ -105,6 +452,24 @@ int uniphier_ld11_umc_init(const struct uniphier_board_data *bd)
return -EINVAL;
}
writel(0x00000101, umc_ch_base + UMC_DIOCTLA);
while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
cpu_relax();
writel(0x00000000, umc_ch_base + UMC_DIOCTLA);
writel(0x00000001, umc_ch_base + UMC_DEBUGC);
writel(0x00000101, umc_ch_base + UMC_DIOCTLA);
writel(0x00000100, umc_ch_base + UMC_INITSET);
while (readl(umc_ch_base + UMC_INITSTAT) & BIT(8))
cpu_relax();
writel(0x00000100, umc_ch_base + 0x00200000 + UMC_INITSET);
while (readl(umc_ch_base + 0x00200000 + UMC_INITSTAT) & BIT(8))
cpu_relax();
ddrphy_init(phy_base, freq);
for (ch = 0; ch < bd->dram_nr_ch; ch++) {
unsigned long size = bd->dram_ch[ch].size;
unsigned int width = bd->dram_ch[ch].width;
@ -117,6 +482,7 @@ int uniphier_ld11_umc_init(const struct uniphier_board_data *bd)
umc_ch_base += 0x00200000;
}
ddrphy_training(phy_base);
um_init(um_base);

113
arch/arm/mach-uniphier/dram/umc-ld20.c
View File

@ -1,7 +1,7 @@
/*
* Copyright (C) 2016 Socionext Inc.
*
* based on commit 9073035a9860f892f8d1345dfb0ea862b5021145 of Diag
* based on commit a7a36122aa072fe1bb06e02b73b3634b7a6c555a of Diag
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -14,7 +14,7 @@
#include <asm/processor.h>
#include "../init.h"
#include "ddrphy-ld20-regs.h"
#include "ddruqphy-regs.h"
#include "umc64-regs.h"
#define DRAM_CH_NR 3
@ -33,6 +33,7 @@ enum dram_size {
enum dram_board { /* board type */
DRAM_BOARD_LD20_REF, /* LD20 reference */
DRAM_BOARD_LD20_GLOBAL, /* LD20 TV */
DRAM_BOARD_LD20_C1, /* LD20 TV C1 */
DRAM_BOARD_LD21_REF, /* LD21 reference */
DRAM_BOARD_LD21_GLOBAL, /* LD21 TV */
DRAM_BOARD_NR,
@ -42,6 +43,7 @@ enum dram_board { /* board type */
static const int ddrphy_adrctrl[DRAM_BOARD_NR][DRAM_CH_NR] = {
{268 - 262, 268 - 263, 268 - 378}, /* LD20 reference */
{268 - 262, 268 - 263, 268 - 378}, /* LD20 TV */
{268 - 262, 268 - 263, 268 - 378}, /* LD20 TV C1 */
{268 - 212, 268 - 268, /* No CH2 */}, /* LD21 reference */
{268 - 212, 268 - 268, /* No CH2 */}, /* LD21 TV */
};
@ -49,6 +51,7 @@ static const int ddrphy_adrctrl[DRAM_BOARD_NR][DRAM_CH_NR] = {
static const int ddrphy_dlltrimclk[DRAM_BOARD_NR][DRAM_CH_NR] = {
{268, 268, 268}, /* LD20 reference */
{268, 268, 268}, /* LD20 TV */
{189, 189, 189}, /* LD20 TV C1 */
{268, 268 + 252, /* No CH2 */}, /* LD21 reference */
{268, 268 + 202, /* No CH2 */}, /* LD21 TV */
};
@ -56,6 +59,7 @@ static const int ddrphy_dlltrimclk[DRAM_BOARD_NR][DRAM_CH_NR] = {
static const int ddrphy_dllrecalib[DRAM_BOARD_NR][DRAM_CH_NR] = {
{268 - 378, 268 - 263, 268 - 378}, /* LD20 reference */
{268 - 378, 268 - 263, 268 - 378}, /* LD20 TV */
{268 - 378, 268 - 263, 268 - 378}, /* LD20 TV C1 */
{268 - 212, 268 - 536, /* No CH2 */}, /* LD21 reference */
{268 - 212, 268 - 536, /* No CH2 */}, /* LD21 TV */
};
@ -63,6 +67,7 @@ static const int ddrphy_dllrecalib[DRAM_BOARD_NR][DRAM_CH_NR] = {
static const u32 ddrphy_phy_pad_ctrl[DRAM_BOARD_NR][DRAM_CH_NR] = {
{0x50B840B1, 0x50B840B1, 0x50B840B1}, /* LD20 reference */
{0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV */
{0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV C1 */
{0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 reference */
{0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 TV */
};
@ -112,6 +117,26 @@ static const int ddrphy_op_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
1, 1, 1, 0, 2, 2, 1, 2,
},
},
{ /* LD20 TV C1 */
{
2, 1, 0, 1, 2, 1, 1, 1,
2, 1, 1, 2, 1, 1, 1, 1,
1, 2, 1, 1, 1, 2, 1, 1,
2, 2, 0, 1, 1, 2, 2, 1,
},
{
1, 1, 0, 1, 2, 2, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 0, 0, 1, 1, 0, 0,
0, 1, 1, 1, 2, 1, 2, 1,
},
{
2, 2, 0, 2, 1, 1, 2, 1,
1, 1, 0, 1, 1, -1, 1, 1,
2, 2, 2, 2, 1, 1, 1, 1,
1, 1, 1, 0, 2, 2, 1, 2,
},
},
{ /* LD21 reference */
{
1, 1, 0, 1, 1, 1, 1, 1,
@ -183,6 +208,26 @@ static int ddrphy_ip_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
2, 2, 2, 2, 1, 2, 2, 1,
},
},
{ /* LD20 TV C1 */
{
3, 3, 3, 2, 3, 2, 0, 2,
2, 3, 3, 1, 2, 2, 2, 2,
2, 2, 2, 2, 0, 1, 1, 1,
2, 2, 2, 2, 3, 0, 2, 2,
},
{
2, 2, 1, 1, -1, 1, 1, 1,
2, 0, 2, 2, 2, 1, 0, 2,
2, 1, 2, 1, 0, 1, 1, 1,
2, 2, 2, 2, 2, 2, 2, 2,
},
{
2, 2, 3, 2, 1, 2, 2, 2,
2, 3, 4, 2, 3, 4, 3, 3,
2, 2, 1, 2, 1, 1, 1, 1,
2, 2, 2, 2, 1, 2, 2, 1,
},
},
{ /* LD21 reference */
{
2, 2, 2, 2, 1, 2, 2, 2,
@ -387,7 +432,7 @@ static int ddrphy_training(void __iomem *phy_base, enum dram_board board,
writel(0x00010000, phy_base + PHY_DLL_TRIM_2);
writel(0x50000000, phy_base + PHY_SCL_START);
while (readl(phy_base + PHY_SCL_START) & BIT(28))
while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
cpu_relax();
writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL);
@ -396,13 +441,13 @@ static int ddrphy_training(void __iomem *phy_base, enum dram_board board,
writel(0xFBF8FFFF, phy_base + PHY_SCL_START_ADDR);
writel(0x11000000, phy_base + PHY_SCL_START);
while (readl(phy_base + PHY_SCL_START) & BIT(28))
while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
cpu_relax();
writel(0xFBF0FFFF, phy_base + PHY_SCL_START_ADDR);
writel(0x30500000, phy_base + PHY_SCL_START);
while (readl(phy_base + PHY_SCL_START) & BIT(28))
while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
cpu_relax();
writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL);
@ -411,12 +456,12 @@ static int ddrphy_training(void __iomem *phy_base, enum dram_board board,
writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1);
writel(0x11000000, phy_base + PHY_SCL_START);
while (readl(phy_base + PHY_SCL_START) & BIT(28))
while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
cpu_relax();
writel(0x34000000, phy_base + PHY_SCL_START);
while (readl(phy_base + PHY_SCL_START) & BIT(28))
while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
cpu_relax();
writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL);
@ -445,45 +490,42 @@ static int ddrphy_training(void __iomem *phy_base, enum dram_board board,
}
/* UMC */
static u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11};
static u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC};
static u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF};
static u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114};
static u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};
static const u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11};
static const u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC};
static const u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF};
static const u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114};
static const u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};
static u32 umc_memconf0a[DRAM_FREQ_NR][DRAM_SZ_NR] = {
static const u32 umc_memconf0a[DRAM_FREQ_NR][DRAM_SZ_NR] = {
/* 256MB 512MB */
{0x00000601, 0x00000801}, /* 1866 MHz */
};
static u32 umc_memconf0b[DRAM_FREQ_NR][DRAM_SZ_NR] = {
static const u32 umc_memconf0b[DRAM_FREQ_NR][DRAM_SZ_NR] = {
/* 256MB 512MB */
{0x00000120, 0x00000130}, /* 1866 MHz */
};
static u32 umc_memconfch[DRAM_FREQ_NR][DRAM_SZ_NR] = {
static const u32 umc_memconfch[DRAM_FREQ_NR][DRAM_SZ_NR] = {
/* 256MB 512MB */
{0x00033603, 0x00033803}, /* 1866 MHz */
};
static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
static u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = {
static const u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
static const u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
static const u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
static const u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = {
/* 256MB 512MB */
{0x0049071D, 0x0078071D}, /* 1866 MHz */
};
static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000610};
static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000610};
static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000204};
static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000204};
static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
static u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000};
static const u32 umc_rdatactl[DRAM_FREQ_NR] = {0x00000610};
static const u32 umc_wdatactl[DRAM_FREQ_NR] = {0x00000204};
static const u32 umc_odtctl[DRAM_FREQ_NR] = {0x02000002};
static const u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000};
static u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E};
static u32 umc_directbusctrla[DRAM_CH_NR] = {
static const u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E};
static const u32 umc_directbusctrla[DRAM_CH_NR] = {
0x00000000, 0x00000001, 0x00000001
};
@ -546,13 +588,13 @@ static int umc_dc_init(void __iomem *dc_base, unsigned int freq,
writel(umc_cmdctlc[freq_e], dc_base + UMC_CMDCTLC);
writel(umc_cmdctle[freq_e][size_e], dc_base + UMC_CMDCTLE);
writel(umc_rdatactl_d0[freq_e], dc_base + UMC_RDATACTL_D0);
writel(umc_rdatactl_d1[freq_e], dc_base + UMC_RDATACTL_D1);
writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D1);
writel(umc_wdatactl_d0[freq_e], dc_base + UMC_WDATACTL_D0);
writel(umc_wdatactl_d1[freq_e], dc_base + UMC_WDATACTL_D1);
writel(umc_odtctl_d0[freq_e], dc_base + UMC_ODTCTL_D0);
writel(umc_odtctl_d1[freq_e], dc_base + UMC_ODTCTL_D1);
writel(umc_wdatactl[freq_e], dc_base + UMC_WDATACTL_D0);
writel(umc_wdatactl[freq_e], dc_base + UMC_WDATACTL_D1);
writel(umc_odtctl[freq_e], dc_base + UMC_ODTCTL_D0);
writel(umc_odtctl[freq_e], dc_base + UMC_ODTCTL_D1);
writel(umc_dataset[freq_e], dc_base + UMC_DATASET);
writel(0x00400020, dc_base + UMC_DCCGCTL);
@ -644,6 +686,9 @@ int uniphier_ld20_umc_init(const struct uniphier_board_data *bd)
case UNIPHIER_BD_BOARD_LD20_GLOBAL:
board = DRAM_BOARD_LD20_GLOBAL;
break;
case UNIPHIER_BD_BOARD_LD20_C1:
board = DRAM_BOARD_LD20_C1;
break;
case UNIPHIER_BD_BOARD_LD21_REF:
board = DRAM_BOARD_LD21_REF;
break;

4
arch/arm/mach-uniphier/dram/umc-ld4.c
View File

@ -13,7 +13,7 @@
#include <asm/processor.h>
#include "../init.h"
#include "ddrphy-regs.h"
#include "ddrphy-init.h"
#include "umc-regs.h"
#define DRAM_CH_NR 2
@ -149,7 +149,7 @@ static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
int ret;
writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
cpu_relax();
writel(0x00000101, dc_base + UMC_DIOCTLA);

4
arch/arm/mach-uniphier/dram/umc-pro4.c
View File

@ -13,7 +13,7 @@
#include <asm/processor.h>
#include "../init.h"
#include "ddrphy-regs.h"
#include "ddrphy-init.h"
#include "umc-regs.h"
#define DRAM_CH_NR 2
@ -137,7 +137,7 @@ static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
int phy, ret;
writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
cpu_relax();
for (phy = 0; phy < nr_phy; phy++) {

4
arch/arm/mach-uniphier/dram/umc-sld8.c
View File

@ -13,7 +13,7 @@
#include <asm/processor.h>
#include "../init.h"
#include "ddrphy-regs.h"
#include "ddrphy-init.h"
#include "umc-regs.h"
#define DRAM_CH_NR 2
@ -152,7 +152,7 @@ static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
int ret;
writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
cpu_relax();
writel(0x00000101, dc_base + UMC_DIOCTLA);

10
arch/arm/mach-uniphier/init.h
View File

@ -24,16 +24,14 @@ struct uniphier_board_data {
struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH];
unsigned int flags;
#define UNIPHIER_BD_DPLL_SSC_GET_RATE(f) (((f) >> 8) & 0x3)
#define UNIPHIER_BD_DPLL_SSC_RATE(r) (((r) & 0x3) << 8)
#define UNIPHIER_BD_DDR3PLUS BIT(2)
#define UNIPHIER_BD_BOARD_GET_TYPE(f) ((f) & 0x3)
#define UNIPHIER_BD_BOARD_GET_TYPE(f) ((f) & 0x7)
#define UNIPHIER_BD_BOARD_LD20_REF 0 /* LD20 reference */
#define UNIPHIER_BD_BOARD_LD20_GLOBAL 1 /* LD20 TV Set */
#define UNIPHIER_BD_BOARD_LD21_REF 2 /* LD21 reference */
#define UNIPHIER_BD_BOARD_LD21_GLOBAL 3 /* LD21 TV Set */
#define UNIPHIER_BD_BOARD_LD20_C1 2 /* LD20 TV Set C1 */
#define UNIPHIER_BD_BOARD_LD21_REF 3 /* LD21 reference */
#define UNIPHIER_BD_BOARD_LD21_GLOBAL 4 /* LD21 TV Set */
};
const struct uniphier_board_data *uniphier_get_board_param(void);

2
arch/arm/mach-uniphier/sc64-regs.h
View File

@ -52,6 +52,8 @@
#define SC_CLKCTRL (SC_BASE_ADDR | 0x2100)
#define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108)
#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
#define SC_CLKCTRL4_MIO (1 << 10)
#define SC_CLKCTRL4_STDMAC (1 << 8)
#define SC_CLKCTRL4_PERI (1 << 7)
#define SC_CLKCTRL4_ETHER (1 << 6)
#define SC_CLKCTRL4_NAND (1 << 0)