mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
ARM: dts: k3-am65: Add OSPI DT nodes
Add OSPI DT nodes to enable OSPI at U-Boot prompt and also to support OSPI boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Vignesh Raghavendra
Lokesh Vutla
parent
7d0866b9be
commit
9e9dfc1fc4
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@ -64,4 +64,42 @@
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loczrama = <1>;
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};
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};
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fss: fss@47000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ospi0: spi@47040000 {
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compatible = "ti,am654-ospi", "cdns,qspi-nor";
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reg = <0x0 0x47040000 0x0 0x100>,
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<0x5 0x00000000 0x1 0x0000000>;
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interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
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cdns,fifo-depth = <256>;
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x0>;
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clocks = <&k3_clks 248 0>;
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assigned-clocks = <&k3_clks 248 0>;
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assigned-clock-parents = <&k3_clks 248 2>;
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assigned-clock-rates = <166666666>;
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power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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ospi1: spi@47050000 {
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compatible = "ti,am654-ospi", "cdns,qspi-nor";
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reg = <0x0 0x47050000 0x0 0x100>,
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<0x7 0x00000000 0x1 0x00000000>;
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interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
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cdns,fifo-depth = <256>;
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x0>;
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clocks = <&k3_clks 249 6>;
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power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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@ -30,6 +30,8 @@
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i2c3 = &main_i2c1;
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i2c4 = &main_i2c2;
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i2c5 = &main_i2c3;
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spi0 = &ospi0;
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spi1 = &ospi1;
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};
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chosen { };
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@ -79,7 +81,11 @@
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<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
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<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
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<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
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<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>;
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<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
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<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
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<0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
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<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
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<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
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cbass_mcu: interconnect@28380000 {
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compatible = "simple-bus";
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@ -93,7 +99,10 @@
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<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
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<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
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<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
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<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */
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<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
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<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /* FSS OSPI0 data region 1 */
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<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
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<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
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cbass_wakeup: interconnect@42040000 {
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compatible = "simple-bus";
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@ -43,6 +43,7 @@
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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u-boot,dm-spl;
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ti,sci-dev-id = <119>;
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@ -59,6 +60,7 @@
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ti,dma-ring-reset-quirk;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <195>;
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u-boot,dm-spl;
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};
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mcu_udmap: udmap@285c0000 {
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@ -81,6 +83,7 @@
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<0x4>; /* RX_CHAN */
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ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
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dma-coherent;
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u-boot,dm-spl;
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};
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};
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@ -305,6 +308,10 @@
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AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
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>;
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};
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mcu-fss0-ospi0-pins-default {
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u-boot,dm-spl;
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};
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};
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&main_uart0 {
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@ -365,3 +372,15 @@
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&usb1 {
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dr_mode = "peripheral";
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};
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&fss {
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u-boot,dm-spl;
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};
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&ospi0 {
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u-boot,dm-spl;
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flash@0{
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u-boot,dm-spl;
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};
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};
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@ -73,6 +73,22 @@
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AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
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>;
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};
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mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
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AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
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AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */
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AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */
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AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */
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AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */
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AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */
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AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */
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AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */
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AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
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AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
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>;
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};
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};
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&sdhci0 {
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@ -117,3 +133,23 @@
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&usb0_phy {
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status = "disabled";
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};
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&ospi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
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flash@0{
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <8>;
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spi-max-frequency = <40000000>;
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cdns,tshsl-ns = <60>;
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cdns,tsd2d-ns = <60>;
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cdns,tchsh-ns = <60>;
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cdns,tslch-ns = <60>;
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cdns,read-delay = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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@ -179,6 +179,22 @@
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AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
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>;
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};
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mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
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AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
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AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */
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AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */
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AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */
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AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */
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AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */
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AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */
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AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */
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AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
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AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
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>;
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};
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};
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&main_pmx0 {
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@ -239,3 +255,26 @@
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u-boot,dm-spl;
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};
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};
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&ospi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
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reg = <0x0 0x47040000 0x0 0x100>,
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<0x0 0x50000000 0x0 0x8000000>;
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flash@0{
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <8>;
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spi-max-frequency = <40000000>;
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cdns,tshsl-ns = <60>;
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cdns,tsd2d-ns = <60>;
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cdns,tchsh-ns = <60>;
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cdns,tslch-ns = <60>;
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cdns,read-delay = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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