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ARM: tegra: add I2C controllers to Tegra186 DT
Tegra186 has 8 I2C controllers including BPMP I2C. This patch adds the other 7 generic controllers to Tegra186's DT. Signed-off-by: Bryan Wu <pengw@nvidia.com> (swarren, fixed DT node sort order, tweak patch description) Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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@ -38,6 +38,84 @@
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status = "disabled";
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status = "disabled";
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};
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};
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gen1_i2c: i2c@3160000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x3160000 0x0 0x100>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C1>;
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clock-names = "i2c";
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resets = <&bpmp TEGRA186_RESET_I2C1>;
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reset-names = "i2c";
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status = "disabled";
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};
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cam_i2c: i2c@3180000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x3180000 0x0 0x100>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C3>;
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clock-names = "i2c";
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resets = <&bpmp TEGRA186_RESET_I2C3>;
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reset-names = "i2c";
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status = "disabled";
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};
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dp_aux_ch1_i2c: i2c@3190000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x3190000 0x0 0x100>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C4>;
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clock-names = "i2c";
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resets = <&bpmp TEGRA186_RESET_I2C4>;
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reset-names = "i2c";
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status = "disabled";
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};
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dp_aux_ch0_i2c: i2c@31b0000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x31b0000 0x0 0x100>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C6>;
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clock-names = "i2c";
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resets = <&bpmp TEGRA186_RESET_I2C6>;
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reset-names = "i2c";
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status = "disabled";
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};
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gen7_i2c: i2c@31c0000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x31c0000 0x0 0x100>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C7>;
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clock-names = "i2c";
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resets = <&bpmp TEGRA186_RESET_I2C7>;
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reset-names = "i2c";
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status = "disabled";
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};
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gen9_i2c: i2c@31e0000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x31e0000 0x0 0x100>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C9>;
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clock-names = "i2c";
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resets = <&bpmp TEGRA186_RESET_I2C9>;
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reset-names = "i2c";
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status = "disabled";
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};
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sdhci@3400000 {
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sdhci@3400000 {
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compatible = "nvidia,tegra186-sdhci";
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03400000 0x0 0x200>;
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reg = <0x0 0x03400000 0x0 0x200>;
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@ -81,6 +159,32 @@
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#mbox-cells = <2>;
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#mbox-cells = <2>;
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};
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};
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gen2_i2c: i2c@c240000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0xc240000 0x0 0x100>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C2>;
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clock-names = "i2c";
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resets = <&bpmp TEGRA186_RESET_I2C2>;
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reset-names = "i2c";
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status = "disabled";
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};
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gen8_i2c: i2c@c250000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0xc250000 0x0 0x100>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C8>;
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clock-names = "i2c";
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resets = <&bpmp TEGRA186_RESET_I2C8>;
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reset-names = "i2c";
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status = "disabled";
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};
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gpio_aon: gpio@c2f0000 {
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gpio_aon: gpio@c2f0000 {
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compatible = "nvidia,tegra186-gpio-aon";
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compatible = "nvidia,tegra186-gpio-aon";
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reg-names = "security", "gpio";
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reg-names = "security", "gpio";
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