mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
Drop PCMCIA
This is no-longer used in U-Boot and has not been converted to driver model. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
Tom Rini
parent
f3998fdc4d
commit
9e5616dea9
2
README
2
README
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@ -83,7 +83,7 @@ Where we come from:
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* Provide extended interface to Linux boot loader
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* S-Record download
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* network boot
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* PCMCIA / CompactFlash / ATA disk / SCSI ... boot
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* ATA disk / SCSI ... boot
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- create ARMBoot project (http://sourceforge.net/projects/armboot)
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- add other CPU families (starting with ARM)
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- create U-Boot project (http://sourceforge.net/projects/u-boot)
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@ -1042,14 +1042,6 @@ config CMD_PCI
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peripherals. Sub-commands allow bus enumeration, displaying and
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changing configuration space and a few other features.
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config CMD_PCMCIA
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bool "pinit - Set up PCMCIA device"
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help
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Provides a means to initialise a PCMCIA (Personal Computer Memory
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Card International Association) device. This is an old standard from
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about 1990. These devices are typically removable memory or network
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cards using a standard 68-pin connector.
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config CMD_PINMUX
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bool "pinmux - show pins muxing"
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default y if PINCTRL
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@ -106,7 +106,6 @@ obj-$(CONFIG_CMD_PART) += part.o
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ifdef CONFIG_PCI
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obj-$(CONFIG_CMD_PCI) += pci.o
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endif
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obj-$(CONFIG_CMD_PCMCIA) += pcmcia.o
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obj-$(CONFIG_CMD_PINMUX) += pinmux.o
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obj-$(CONFIG_CMD_PXE) += pxe.o
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obj-$(CONFIG_CMD_WOL) += wol.o
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@ -17,10 +17,6 @@
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#if defined(CONFIG_IDE_PCMCIA)
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# include <pcmcia.h>
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#endif
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#include <ide.h>
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#include <ata.h>
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341
cmd/pcmcia.c
341
cmd/pcmcia.c
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@ -1,341 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2000-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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********************************************************************
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*
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* Lots of code copied from:
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*
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* m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
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* (C) 1999-2000 Magnus Damm <damm@bitsmart.com>
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*
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* "The ExCA standard specifies that socket controllers should provide
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* two IO and five memory windows per socket, which can be independently
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* configured and positioned in the host address space and mapped to
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* arbitrary segments of card address space. " - David A Hinds. 1999
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*
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* This controller does _not_ meet the ExCA standard.
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*
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* m8xx pcmcia controller brief info:
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* + 8 windows (attrib, mem, i/o)
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* + up to two slots (SLOT_A and SLOT_B)
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* + inputpins, outputpins, event and mask registers.
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* - no offset register. sigh.
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*
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* Because of the lacking offset register we must map the whole card.
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* We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
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* Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
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* * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
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* The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
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* They are maximum 64KByte each...
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*/
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/* #define DEBUG 1 */
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/*
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* PCMCIA support
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*/
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#include <common.h>
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#include <command.h>
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#include <config.h>
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#include <pcmcia.h>
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#include <asm/io.h>
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/* -------------------------------------------------------------------- */
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#if defined(CONFIG_CMD_PCMCIA)
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extern int pcmcia_on (void);
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extern int pcmcia_off (void);
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int do_pinit (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int rcode = 0;
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if (argc != 2) {
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printf ("Usage: pinit {on | off}\n");
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return 1;
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}
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if (strcmp(argv[1],"on") == 0) {
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rcode = pcmcia_on ();
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} else if (strcmp(argv[1],"off") == 0) {
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rcode = pcmcia_off ();
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} else {
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printf ("Usage: pinit {on | off}\n");
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return 1;
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}
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return rcode;
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}
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U_BOOT_CMD(
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pinit, 2, 0, do_pinit,
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"PCMCIA sub-system",
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"on - power on PCMCIA socket\n"
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"pinit off - power off PCMCIA socket"
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);
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#endif
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/* -------------------------------------------------------------------- */
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#undef CHECK_IDE_DEVICE
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#if defined(CONFIG_PXA_PCMCIA)
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#define CHECK_IDE_DEVICE
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#endif
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#ifdef CHECK_IDE_DEVICE
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int ide_devices_found;
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static uchar *known_cards[] = {
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(uchar *)"ARGOSY PnPIDE D5",
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NULL
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};
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#define MAX_TUPEL_SZ 512
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#define MAX_FEATURES 4
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#define MAX_IDENT_CHARS 64
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#define MAX_IDENT_FIELDS 4
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#define indent "\t "
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static void print_funcid (int func)
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{
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puts (indent);
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switch (func) {
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case CISTPL_FUNCID_MULTI:
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puts (" Multi-Function");
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break;
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case CISTPL_FUNCID_MEMORY:
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puts (" Memory");
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break;
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case CISTPL_FUNCID_SERIAL:
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puts (" Serial Port");
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break;
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case CISTPL_FUNCID_PARALLEL:
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puts (" Parallel Port");
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break;
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case CISTPL_FUNCID_FIXED:
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puts (" Fixed Disk");
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break;
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case CISTPL_FUNCID_VIDEO:
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puts (" Video Adapter");
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break;
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case CISTPL_FUNCID_NETWORK:
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puts (" Network Adapter");
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break;
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case CISTPL_FUNCID_AIMS:
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puts (" AIMS Card");
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break;
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case CISTPL_FUNCID_SCSI:
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puts (" SCSI Adapter");
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break;
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default:
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puts (" Unknown");
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break;
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}
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puts (" Card\n");
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}
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static void print_fixed (volatile uchar *p)
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{
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if (p == NULL)
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return;
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puts(indent);
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switch (*p) {
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case CISTPL_FUNCE_IDE_IFACE:
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{ uchar iface = *(p+2);
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puts ((iface == CISTPL_IDE_INTERFACE) ? " IDE" : " unknown");
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puts (" interface ");
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break;
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}
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case CISTPL_FUNCE_IDE_MASTER:
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case CISTPL_FUNCE_IDE_SLAVE:
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{ uchar f1 = *(p+2);
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uchar f2 = *(p+4);
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puts ((f1 & CISTPL_IDE_SILICON) ? " [silicon]" : " [rotating]");
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if (f1 & CISTPL_IDE_UNIQUE)
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puts (" [unique]");
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puts ((f1 & CISTPL_IDE_DUAL) ? " [dual]" : " [single]");
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if (f2 & CISTPL_IDE_HAS_SLEEP)
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puts (" [sleep]");
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if (f2 & CISTPL_IDE_HAS_STANDBY)
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puts (" [standby]");
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if (f2 & CISTPL_IDE_HAS_IDLE)
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puts (" [idle]");
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if (f2 & CISTPL_IDE_LOW_POWER)
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puts (" [low power]");
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if (f2 & CISTPL_IDE_REG_INHIBIT)
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puts (" [reg inhibit]");
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if (f2 & CISTPL_IDE_HAS_INDEX)
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puts (" [index]");
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if (f2 & CISTPL_IDE_IOIS16)
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puts (" [IOis16]");
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break;
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}
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}
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putc ('\n');
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}
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static int identify (volatile uchar *p)
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{
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uchar id_str[MAX_IDENT_CHARS];
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uchar data;
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uchar *t;
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uchar **card;
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int i, done;
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if (p == NULL)
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return (0); /* Don't know */
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t = id_str;
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done =0;
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for (i=0; i<=4 && !done; ++i, p+=2) {
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while ((data = *p) != '\0') {
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if (data == 0xFF) {
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done = 1;
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break;
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}
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*t++ = data;
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if (t == &id_str[MAX_IDENT_CHARS-1]) {
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done = 1;
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break;
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}
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p += 2;
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}
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if (!done)
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*t++ = ' ';
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}
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*t = '\0';
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while (--t > id_str) {
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if (*t == ' ')
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*t = '\0';
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else
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break;
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}
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puts ((char *)id_str);
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putc ('\n');
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for (card=known_cards; *card; ++card) {
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debug ("## Compare against \"%s\"\n", *card);
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if (strcmp((char *)*card, (char *)id_str) == 0) { /* found! */
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debug ("## CARD FOUND ##\n");
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return (1);
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}
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}
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return (0); /* don't know */
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}
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int check_ide_device (int slot)
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{
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volatile uchar *ident = NULL;
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volatile uchar *feature_p[MAX_FEATURES];
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volatile uchar *p, *start, *addr;
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int n_features = 0;
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uchar func_id = ~0;
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uchar code, len;
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ushort config_base = 0;
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int found = 0;
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int i;
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addr = (volatile uchar *)(CONFIG_SYS_PCMCIA_MEM_ADDR +
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CONFIG_SYS_PCMCIA_MEM_SIZE * (slot * 4));
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debug ("PCMCIA MEM: %08lX\n", (ulong)addr);
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start = p = (volatile uchar *) addr;
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while ((p - start) < MAX_TUPEL_SZ) {
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code = *p; p += 2;
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if (code == 0xFF) { /* End of chain */
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break;
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}
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len = *p; p += 2;
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#if defined(DEBUG) && (DEBUG > 1)
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{ volatile uchar *q = p;
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printf ("\nTuple code %02x length %d\n\tData:",
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code, len);
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for (i = 0; i < len; ++i) {
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printf (" %02x", *q);
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q+= 2;
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}
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}
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#endif /* DEBUG */
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switch (code) {
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case CISTPL_VERS_1:
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ident = p + 4;
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break;
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case CISTPL_FUNCID:
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/* Fix for broken SanDisk which may have 0x80 bit set */
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func_id = *p & 0x7F;
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break;
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case CISTPL_FUNCE:
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if (n_features < MAX_FEATURES)
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feature_p[n_features++] = p;
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break;
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case CISTPL_CONFIG:
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config_base = (*(p+6) << 8) + (*(p+4));
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debug ("\n## Config_base = %04x ###\n", config_base);
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default:
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break;
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}
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p += 2 * len;
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}
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found = identify (ident);
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if (func_id != ((uchar)~0)) {
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print_funcid (func_id);
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if (func_id == CISTPL_FUNCID_FIXED)
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found = 1;
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else
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return (1); /* no disk drive */
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}
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for (i=0; i<n_features; ++i) {
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print_fixed (feature_p[i]);
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}
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if (!found) {
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printf ("unknown card type\n");
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return (1);
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}
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ide_devices_found |= (1 << slot);
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/* set I/O area in config reg -> only valid for ARGOSY D5!!! */
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*((uchar *)(addr + config_base)) = 1;
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#if 0
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printf("\n## Config_base = %04x ###\n", config_base);
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printf("Configuration Option Register: %02x @ %x\n", readb(addr + config_base), addr + config_base);
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printf("Card Configuration and Status Register: %02x\n", readb(addr + config_base + 2));
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printf("Pin Replacement Register Register: %02x\n", readb(addr + config_base + 4));
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printf("Socket and Copy Register: %02x\n", readb(addr + config_base + 6));
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#endif
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return (0);
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}
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#endif /* CHECK_IDE_DEVICE */
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@ -583,15 +583,6 @@ static int initr_post(void)
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}
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#endif
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#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_IDE)
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static int initr_pcmcia(void)
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{
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puts("PCMCIA:");
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pcmcia_init();
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return 0;
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}
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#endif
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#if defined(CONFIG_IDE) && !defined(CONFIG_BLK)
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static int initr_ide(void)
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{
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@ -820,9 +811,6 @@ static init_fnc_t init_sequence_r[] = {
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#ifdef CONFIG_POST
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initr_post,
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#endif
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#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_IDE)
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initr_pcmcia,
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#endif
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#if defined(CONFIG_IDE) && !defined(CONFIG_BLK)
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initr_ide,
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#endif
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|
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@ -1,65 +0,0 @@
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U-Boot MARUBUN MR-SHPC-01 PCMCIA controller driver
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Last update 21/11/2007 by Nobuhiro Iwamatsu
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========================================================================================
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0. What's this?
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This driver supports MARUBUN MR-SHPC-01.
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url: http://www.marubun.co.jp/product/semicon/devices/qgc18e0000002n2z.html
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(Sorry Japanese only.)
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This chip is used with SuperH well, and adopted by the
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reference board.
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ex. * MS7750SE01
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* MS7722SE01
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* other
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This chip doesn't support CardBus.
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1. base source code
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The code is based on sources from the Linux kernel
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( arch/sh/kernel/cf-enabler.c ).
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2. How to use
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The options you have to specify in the config file are (with the
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value for my board as an example):
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* CONFIG_MARUBUN_PCCARD
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If you want to use this device driver, should define CONFIG_MARUBUN_PCCARD.
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ex. #define CONFIG_MARUBUN_PCCARD
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* CONFIG_PCMCIA_SLOT_A
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Most devices have only one slot. You should define CONFIG_PCMCIA_SLOT_A .
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ex. #define CONFIG_PCMCIA_SLOT_A 1
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* CONFIG_SYS_MARUBUN_MRSHPC
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This is MR-SHPC-01 PCMCIA controller base address.
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You should do the setting matched to your environment.
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ex. #define CONFIG_SYS_MARUBUN_MRSHPC 0xb03fffe0
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( for MS7722SE01 environment )
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* CONFIG_SYS_MARUBUN_MW1
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This is MR-SHPC-01 memory window base address.
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You should do the setting matched to your environment.
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ex. #define CONFIG_SYS_MARUBUN_MW1 0xb0400000
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( for MS7722SE01 environment )
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* CONFIG_SYS_MARUBUN_MW1
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This is MR-SHPC-01 attribute window base address.
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You should do the setting matched to your environment.
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ex. #define CONFIG_SYS_MARUBUN_MW2 0xb0500000
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( for MS7722SE01 environment )
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* CONFIG_SYS_MARUBUN_MW1
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This is MR-SHPC-01 I/O window base address.
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You should do the setting matched to your environment.
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ex. #define CONFIG_SYS_MARUBUN_IO 0xb0600000
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( for MS7722SE01 environment )
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3. Other
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* Check Compact Flash only.
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* Maybe, NE2000 compatible NIC is sure to move.
|
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|
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Copyright (c) 2007
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Nobuhiro Iwamatsu <iwamatsu@nigaur.org>
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|
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@ -21,17 +21,6 @@ value for my board as an example):
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- Address where the board is mapped
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#define CONFIG_DRIVER_NE2000_CCR (0x28000000+0x3f8)
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- Address of the CCR (card configuration register). It could be found
|
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by enabling DEBUG in cmd_pcmcia.c. If this is not defined nothing is
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done as far as PCMCIA support is concerned.
|
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#define CONFIG_DRIVER_NE2000_VAL (0x20)
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|
||||
- The value to be written in the CCR. It selects among different I/O
|
||||
spaces that could be used by the card.
|
||||
|
||||
|
||||
Enjoy!
|
||||
|
||||
|
|
|
|||
|
|
@ -70,8 +70,6 @@ source "drivers/pci_endpoint/Kconfig"
|
|||
|
||||
source "drivers/pch/Kconfig"
|
||||
|
||||
source "drivers/pcmcia/Kconfig"
|
||||
|
||||
source "drivers/phy/Kconfig"
|
||||
|
||||
source "drivers/phy/allwinner/Kconfig"
|
||||
|
|
|
|||
|
|
@ -88,7 +88,6 @@ obj-y += misc/
|
|||
obj-$(CONFIG_MMC) += mmc/
|
||||
obj-$(CONFIG_NVME) += nvme/
|
||||
obj-$(CONFIG_PCI_ENDPOINT) += pci_endpoint/
|
||||
obj-y += pcmcia/
|
||||
obj-y += dfu/
|
||||
obj-$(CONFIG_PCH) += pch/
|
||||
obj-y += phy/allwinner/
|
||||
|
|
|
|||
|
|
@ -693,16 +693,6 @@ static int ne2k_setup_driver(struct eth_device *dev)
|
|||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DRIVER_NE2000_CCR
|
||||
{
|
||||
vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR;
|
||||
|
||||
PRINTK("CCR before is %x\n", *p);
|
||||
*p = CONFIG_DRIVER_NE2000_VAL;
|
||||
PRINTK("CCR after is %x\n", *p);
|
||||
}
|
||||
#endif
|
||||
|
||||
nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE;
|
||||
|
||||
nic.data = nic.base + DP_DATA;
|
||||
|
|
|
|||
|
|
@ -1,6 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2000-2007
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
||||
obj-$(CONFIG_MARUBUN_PCCARD) += marubun_pcmcia.o
|
||||
|
|
@ -1,99 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Marubun MR-SHPC-01 PCMCIA controller device driver
|
||||
*
|
||||
* (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <pcmcia.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#undef CONFIG_PCMCIA
|
||||
|
||||
#if defined(CONFIG_CMD_PCMCIA)
|
||||
#define CONFIG_PCMCIA
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_IDE)
|
||||
#define CONFIG_PCMCIA
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCMCIA)
|
||||
|
||||
/* MR-SHPC-01 register */
|
||||
#define MRSHPC_MODE (CONFIG_SYS_MARUBUN_MRSHPC + 4)
|
||||
#define MRSHPC_OPTION (CONFIG_SYS_MARUBUN_MRSHPC + 6)
|
||||
#define MRSHPC_CSR (CONFIG_SYS_MARUBUN_MRSHPC + 8)
|
||||
#define MRSHPC_ISR (CONFIG_SYS_MARUBUN_MRSHPC + 10)
|
||||
#define MRSHPC_ICR (CONFIG_SYS_MARUBUN_MRSHPC + 12)
|
||||
#define MRSHPC_CPWCR (CONFIG_SYS_MARUBUN_MRSHPC + 14)
|
||||
#define MRSHPC_MW0CR1 (CONFIG_SYS_MARUBUN_MRSHPC + 16)
|
||||
#define MRSHPC_MW1CR1 (CONFIG_SYS_MARUBUN_MRSHPC + 18)
|
||||
#define MRSHPC_IOWCR1 (CONFIG_SYS_MARUBUN_MRSHPC + 20)
|
||||
#define MRSHPC_MW0CR2 (CONFIG_SYS_MARUBUN_MRSHPC + 22)
|
||||
#define MRSHPC_MW1CR2 (CONFIG_SYS_MARUBUN_MRSHPC + 24)
|
||||
#define MRSHPC_IOWCR2 (CONFIG_SYS_MARUBUN_MRSHPC + 26)
|
||||
#define MRSHPC_CDCR (CONFIG_SYS_MARUBUN_MRSHPC + 28)
|
||||
#define MRSHPC_PCIC_INFO (CONFIG_SYS_MARUBUN_MRSHPC + 30)
|
||||
|
||||
int pcmcia_on (void)
|
||||
{
|
||||
printf("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
|
||||
|
||||
/* Init */
|
||||
outw( 0x0000 , MRSHPC_MODE );
|
||||
|
||||
if ((inw(MRSHPC_CSR) & 0x000c) == 0){ /* if card detect is true */
|
||||
if ((inw(MRSHPC_CSR) & 0x0080) == 0){
|
||||
outw(0x0674 ,MRSHPC_CPWCR); /* Card Vcc is 3.3v? */
|
||||
}else{
|
||||
outw(0x0678 ,MRSHPC_CPWCR); /* Card Vcc is 5V */
|
||||
}
|
||||
udelay( 100000 ); /* wait for power on */
|
||||
}else{
|
||||
return 1;
|
||||
}
|
||||
/*
|
||||
* PC-Card window open
|
||||
* flag == COMMON/ATTRIBUTE/IO
|
||||
*/
|
||||
/* common window open */
|
||||
outw(0x8a84,MRSHPC_MW0CR1); /* window 0xb8400000 */
|
||||
if ((inw(MRSHPC_CSR) & 0x4000) != 0)
|
||||
outw(0x0b00,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 1 */
|
||||
else
|
||||
outw(0x0300,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 0 */
|
||||
|
||||
/* attribute window open */
|
||||
outw(0x8a85,MRSHPC_MW1CR1); /* window 0xb8500000 */
|
||||
if ((inw(MRSHPC_CSR) & 0x4000) != 0)
|
||||
outw(0x0a00,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 1 */
|
||||
else
|
||||
outw(0x0200,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 0 */
|
||||
|
||||
/* I/O window open */
|
||||
outw(0x8a86,MRSHPC_IOWCR1); /* I/O window 0xb8600000 */
|
||||
outw(0x0008,MRSHPC_CDCR); /* I/O card mode */
|
||||
if ((inw(MRSHPC_CSR) & 0x4000) != 0)
|
||||
outw(0x0a00,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1 */
|
||||
else
|
||||
outw(0x0200,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0 */
|
||||
|
||||
outw(0x0000,MRSHPC_ISR);
|
||||
outw(0x2000,MRSHPC_ICR);
|
||||
outb(0x00,(CONFIG_SYS_MARUBUN_MW2 + 0x206));
|
||||
outb(0x42,(CONFIG_SYS_MARUBUN_MW2 + 0x200));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int pcmcia_off (void)
|
||||
{
|
||||
printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PCMCIA */
|
||||
|
|
@ -339,8 +339,6 @@ static inline struct in_addr env_get_ip(char *var)
|
|||
return string_to_ip(env_get(var));
|
||||
}
|
||||
|
||||
int pcmcia_init (void);
|
||||
|
||||
#ifdef CONFIG_LED_STATUS
|
||||
# include <status_led.h>
|
||||
#endif
|
||||
|
|
|
|||
137
include/pcmcia.h
137
include/pcmcia.h
|
|
@ -1,137 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*/
|
||||
|
||||
#ifndef _PCMCIA_H
|
||||
#define _PCMCIA_H
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
|
||||
/*
|
||||
* Allow configuration to select PCMCIA slot,
|
||||
* or try to generate a useful default
|
||||
*/
|
||||
#if defined(CONFIG_CMD_PCMCIA)
|
||||
|
||||
#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
|
||||
# error "PCMCIA Slot not configured"
|
||||
#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
|
||||
|
||||
/* Make sure exactly one slot is defined - we support only one for now */
|
||||
#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
|
||||
#error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
|
||||
#error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
|
||||
#endif
|
||||
|
||||
#ifndef PCMCIA_SOCKETS_NO
|
||||
#define PCMCIA_SOCKETS_NO 1
|
||||
#endif
|
||||
#ifndef PCMCIA_MEM_WIN_NO
|
||||
#define PCMCIA_MEM_WIN_NO 4
|
||||
#endif
|
||||
#define PCMCIA_IO_WIN_NO 2
|
||||
|
||||
/* define _slot_ to be able to optimize macros */
|
||||
#ifdef CONFIG_PCMCIA_SLOT_A
|
||||
# define _slot_ 0
|
||||
# define PCMCIA_SLOT_MSG "slot A"
|
||||
# define PCMCIA_SLOT_x PCMCIA_PSLOT_A
|
||||
#else
|
||||
# define _slot_ 1
|
||||
# define PCMCIA_SLOT_MSG "slot B"
|
||||
# define PCMCIA_SLOT_x PCMCIA_PSLOT_B
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This structure is used to address each window in the PCMCIA controller.
|
||||
*
|
||||
* Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
|
||||
* after pcmcia_win_t[n]...
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
ulong br;
|
||||
ulong or;
|
||||
} pcmcia_win_t;
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
/*
|
||||
* CIS Tupel codes
|
||||
*/
|
||||
#define CISTPL_NULL 0x00
|
||||
#define CISTPL_DEVICE 0x01
|
||||
#define CISTPL_LONGLINK_CB 0x02
|
||||
#define CISTPL_INDIRECT 0x03
|
||||
#define CISTPL_CONFIG_CB 0x04
|
||||
#define CISTPL_CFTABLE_ENTRY_CB 0x05
|
||||
#define CISTPL_LONGLINK_MFC 0x06
|
||||
#define CISTPL_BAR 0x07
|
||||
#define CISTPL_PWR_MGMNT 0x08
|
||||
#define CISTPL_EXTDEVICE 0x09
|
||||
#define CISTPL_CHECKSUM 0x10
|
||||
#define CISTPL_LONGLINK_A 0x11
|
||||
#define CISTPL_LONGLINK_C 0x12
|
||||
#define CISTPL_LINKTARGET 0x13
|
||||
#define CISTPL_NO_LINK 0x14
|
||||
#define CISTPL_VERS_1 0x15
|
||||
#define CISTPL_ALTSTR 0x16
|
||||
#define CISTPL_DEVICE_A 0x17
|
||||
#define CISTPL_JEDEC_C 0x18
|
||||
#define CISTPL_JEDEC_A 0x19
|
||||
#define CISTPL_CONFIG 0x1a
|
||||
#define CISTPL_CFTABLE_ENTRY 0x1b
|
||||
#define CISTPL_DEVICE_OC 0x1c
|
||||
#define CISTPL_DEVICE_OA 0x1d
|
||||
#define CISTPL_DEVICE_GEO 0x1e
|
||||
#define CISTPL_DEVICE_GEO_A 0x1f
|
||||
#define CISTPL_MANFID 0x20
|
||||
#define CISTPL_FUNCID 0x21
|
||||
#define CISTPL_FUNCE 0x22
|
||||
#define CISTPL_SWIL 0x23
|
||||
#define CISTPL_END 0xff
|
||||
|
||||
/*
|
||||
* CIS Function ID codes
|
||||
*/
|
||||
#define CISTPL_FUNCID_MULTI 0x00
|
||||
#define CISTPL_FUNCID_MEMORY 0x01
|
||||
#define CISTPL_FUNCID_SERIAL 0x02
|
||||
#define CISTPL_FUNCID_PARALLEL 0x03
|
||||
#define CISTPL_FUNCID_FIXED 0x04
|
||||
#define CISTPL_FUNCID_VIDEO 0x05
|
||||
#define CISTPL_FUNCID_NETWORK 0x06
|
||||
#define CISTPL_FUNCID_AIMS 0x07
|
||||
#define CISTPL_FUNCID_SCSI 0x08
|
||||
|
||||
/*
|
||||
* Fixed Disk FUNCE codes
|
||||
*/
|
||||
#define CISTPL_IDE_INTERFACE 0x01
|
||||
|
||||
#define CISTPL_FUNCE_IDE_IFACE 0x01
|
||||
#define CISTPL_FUNCE_IDE_MASTER 0x02
|
||||
#define CISTPL_FUNCE_IDE_SLAVE 0x03
|
||||
|
||||
/* First feature byte */
|
||||
#define CISTPL_IDE_SILICON 0x04
|
||||
#define CISTPL_IDE_UNIQUE 0x08
|
||||
#define CISTPL_IDE_DUAL 0x10
|
||||
|
||||
/* Second feature byte */
|
||||
#define CISTPL_IDE_HAS_SLEEP 0x01
|
||||
#define CISTPL_IDE_HAS_STANDBY 0x02
|
||||
#define CISTPL_IDE_HAS_IDLE 0x04
|
||||
#define CISTPL_IDE_LOW_POWER 0x08
|
||||
#define CISTPL_IDE_REG_INHIBIT 0x10
|
||||
#define CISTPL_IDE_HAS_INDEX 0x20
|
||||
#define CISTPL_IDE_IOIS16 0x40
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* _PCMCIA_H */
|
||||
|
|
@ -1,156 +0,0 @@
|
|||
/*
|
||||
* yenta.h 1.20 2001/08/24 12:15:34
|
||||
*
|
||||
* The contents of this file are subject to the Mozilla Public License
|
||||
* Version 1.1 (the "License"); you may not use this file except in
|
||||
* compliance with the License. You may obtain a copy of the License
|
||||
* at http://www.mozilla.org/MPL/
|
||||
*
|
||||
* Software distributed under the License is distributed on an "AS IS"
|
||||
* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
|
||||
* the License for the specific language governing rights and
|
||||
* limitations under the License.
|
||||
*
|
||||
* The initial developer of the original code is David A. Hinds
|
||||
* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
|
||||
* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
|
||||
*
|
||||
* Alternatively, the contents of this file may be used under the
|
||||
* terms of the GNU General Public License version 2 (the "GPL"), in
|
||||
* which case the provisions of the GPL are applicable instead of the
|
||||
* above. If you wish to allow the use of your version of this file
|
||||
* only under the terms of the GPL and not to allow others to use
|
||||
* your version of this file under the MPL, indicate your decision by
|
||||
* deleting the provisions above and replace them with the notice and
|
||||
* other provisions required by the GPL. If you do not delete the
|
||||
* provisions above, a recipient may use your version of this file
|
||||
* under either the MPL or the GPL.
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_YENTA_H
|
||||
#define _LINUX_YENTA_H
|
||||
|
||||
/* PCI Configuration Registers */
|
||||
|
||||
#define PCI_STATUS_CAPLIST 0x10
|
||||
#define PCI_CB_CAPABILITY_POINTER 0x14 /* 8 bit */
|
||||
#define PCI_CAPABILITY_ID 0x00 /* 8 bit */
|
||||
#define PCI_CAPABILITY_PM 0x01
|
||||
#define PCI_NEXT_CAPABILITY 0x01 /* 8 bit */
|
||||
#define PCI_PM_CAPABILITIES 0x02 /* 16 bit */
|
||||
#define PCI_PMCAP_PME_D3COLD 0x8000
|
||||
#define PCI_PMCAP_PME_D3HOT 0x4000
|
||||
#define PCI_PMCAP_PME_D2 0x2000
|
||||
#define PCI_PMCAP_PME_D1 0x1000
|
||||
#define PCI_PMCAP_PME_D0 0x0800
|
||||
#define PCI_PMCAP_D2_CAP 0x0400
|
||||
#define PCI_PMCAP_D1_CAP 0x0200
|
||||
#define PCI_PMCAP_DYN_DATA 0x0100
|
||||
#define PCI_PMCAP_DSI 0x0020
|
||||
#define PCI_PMCAP_AUX_PWR 0x0010
|
||||
#define PCI_PMCAP_PMECLK 0x0008
|
||||
#define PCI_PMCAP_VERSION_MASK 0x0007
|
||||
#define PCI_PM_CONTROL_STATUS 0x04 /* 16 bit */
|
||||
#define PCI_PMCS_PME_STATUS 0x8000
|
||||
#define PCI_PMCS_DATASCALE_MASK 0x6000
|
||||
#define PCI_PMCS_DATASCALE_SHIFT 13
|
||||
#define PCI_PMCS_DATASEL_MASK 0x1e00
|
||||
#define PCI_PMCS_DATASEL_SHIFT 9
|
||||
#define PCI_PMCS_PME_ENABLE 0x0100
|
||||
#define PCI_PMCS_PWR_STATE_MASK 0x0003
|
||||
#define PCI_PMCS_PWR_STATE_D0 0x0000
|
||||
#define PCI_PMCS_PWR_STATE_D1 0x0001
|
||||
#define PCI_PMCS_PWR_STATE_D2 0x0002
|
||||
#define PCI_PMCS_PWR_STATE_D3 0x0003
|
||||
#define PCI_PM_BRIDGE_EXT 0x06 /* 8 bit */
|
||||
#define PCI_PM_DATA 0x07 /* 8 bit */
|
||||
|
||||
#define CB_PRIMARY_BUS 0x18 /* 8 bit */
|
||||
#define CB_CARDBUS_BUS 0x19 /* 8 bit */
|
||||
#define CB_SUBORD_BUS 0x1a /* 8 bit */
|
||||
#define CB_LATENCY_TIMER 0x1b /* 8 bit */
|
||||
|
||||
#define CB_MEM_BASE(m) (0x1c + 8*(m))
|
||||
#define CB_MEM_LIMIT(m) (0x20 + 8*(m))
|
||||
#define CB_IO_BASE(m) (0x2c + 8*(m))
|
||||
#define CB_IO_LIMIT(m) (0x30 + 8*(m))
|
||||
|
||||
#define CB_BRIDGE_CONTROL 0x3e /* 16 bit */
|
||||
#define CB_BCR_PARITY_ENA 0x0001
|
||||
#define CB_BCR_SERR_ENA 0x0002
|
||||
#define CB_BCR_ISA_ENA 0x0004
|
||||
#define CB_BCR_VGA_ENA 0x0008
|
||||
#define CB_BCR_MABORT 0x0020
|
||||
#define CB_BCR_CB_RESET 0x0040
|
||||
#define CB_BCR_ISA_IRQ 0x0080
|
||||
#define CB_BCR_PREFETCH(m) (0x0100 << (m))
|
||||
#define CB_BCR_WRITE_POST 0x0400
|
||||
|
||||
#define CB_LEGACY_MODE_BASE 0x44
|
||||
|
||||
/* Memory mapped registers */
|
||||
|
||||
#define CB_SOCKET_EVENT 0x0000
|
||||
#define CB_SE_CSTSCHG 0x00000001
|
||||
#define CB_SE_CCD 0x00000006
|
||||
#define CB_SE_CCD1 0x00000002
|
||||
#define CB_SE_CCD2 0x00000004
|
||||
#define CB_SE_PWRCYCLE 0x00000008
|
||||
|
||||
#define CB_SOCKET_MASK 0x0004
|
||||
#define CB_SM_CSTSCHG 0x00000001
|
||||
#define CB_SM_CCD 0x00000006
|
||||
#define CB_SM_PWRCYCLE 0x00000008
|
||||
|
||||
#define CB_SOCKET_STATE 0x0008
|
||||
#define CB_SS_CSTSCHG 0x00000001
|
||||
#define CB_SS_CCD 0x00000006
|
||||
#define CB_SS_CCD1 0x00000002
|
||||
#define CB_SS_CCD2 0x00000004
|
||||
#define CB_SS_PWRCYCLE 0x00000008
|
||||
#define CB_SS_16BIT 0x00000010
|
||||
#define CB_SS_32BIT 0x00000020
|
||||
#define CB_SS_CINT 0x00000040
|
||||
#define CB_SS_BADCARD 0x00000080
|
||||
#define CB_SS_DATALOST 0x00000100
|
||||
#define CB_SS_BADVCC 0x00000200
|
||||
#define CB_SS_5VCARD 0x00000400
|
||||
#define CB_SS_3VCARD 0x00000800
|
||||
#define CB_SS_XVCARD 0x00001000
|
||||
#define CB_SS_YVCARD 0x00002000
|
||||
#define CB_SS_VSENSE 0x00003c86
|
||||
#define CB_SS_5VSOCKET 0x10000000
|
||||
#define CB_SS_3VSOCKET 0x20000000
|
||||
#define CB_SS_XVSOCKET 0x40000000
|
||||
#define CB_SS_YVSOCKET 0x80000000
|
||||
|
||||
#define CB_SOCKET_FORCE 0x000c
|
||||
#define CB_SF_CVSTEST 0x00004000
|
||||
|
||||
#define CB_SOCKET_CONTROL 0x0010
|
||||
#define CB_SC_VPP_MASK 0x00000007
|
||||
#define CB_SC_VPP_OFF 0x00000000
|
||||
#define CB_SC_VPP_12V 0x00000001
|
||||
#define CB_SC_VPP_5V 0x00000002
|
||||
#define CB_SC_VPP_3V 0x00000003
|
||||
#define CB_SC_VPP_XV 0x00000004
|
||||
#define CB_SC_VPP_YV 0x00000005
|
||||
#define CB_SC_VCC_MASK 0x00000070
|
||||
#define CB_SC_VCC_OFF 0x00000000
|
||||
#define CB_SC_VCC_5V 0x00000020
|
||||
#define CB_SC_VCC_3V 0x00000030
|
||||
#define CB_SC_VCC_XV 0x00000040
|
||||
#define CB_SC_VCC_YV 0x00000050
|
||||
#define CB_SC_CCLK_STOP 0x00000080
|
||||
|
||||
#define CB_SOCKET_POWER 0x0020
|
||||
#define CB_SP_CLK_CTRL 0x00000001
|
||||
#define CB_SP_CLK_CTRL_ENA 0x00010000
|
||||
#define CB_SP_CLK_MODE 0x01000000
|
||||
#define CB_SP_ACCESS 0x02000000
|
||||
|
||||
/* Address bits 31..24 for memory windows for 16-bit cards,
|
||||
accessable only by memory mapping the 16-bit register set */
|
||||
#define CB_MEM_PAGE(map) (0x40 + (map))
|
||||
|
||||
#endif /* _LINUX_YENTA_H */
|
||||
|
|
@ -362,8 +362,6 @@ CONFIG_DRIVER_DM9000
|
|||
CONFIG_DRIVER_EP93XX_MAC
|
||||
CONFIG_DRIVER_NE2000
|
||||
CONFIG_DRIVER_NE2000_BASE
|
||||
CONFIG_DRIVER_NE2000_CCR
|
||||
CONFIG_DRIVER_NE2000_VAL
|
||||
CONFIG_DRIVER_SMC911X_BASE
|
||||
CONFIG_DRIVER_TI_EMAC_USE_RMII
|
||||
CONFIG_DSP_CLUSTER_START
|
||||
|
|
@ -1357,9 +1355,6 @@ CONFIG_PCI_SKIP_HOST_BRIDGE
|
|||
CONFIG_PCI_SYS_BUS
|
||||
CONFIG_PCI_SYS_PHYS
|
||||
CONFIG_PCI_SYS_SIZE
|
||||
CONFIG_PCMCIA
|
||||
CONFIG_PCMCIA_SLOT_A
|
||||
CONFIG_PCMCIA_SLOT_B
|
||||
CONFIG_PCNET
|
||||
CONFIG_PCNET_79C973
|
||||
CONFIG_PCNET_79C975
|
||||
|
|
@ -3704,7 +3699,6 @@ CONFIG_SYS_PCI_TBATR3
|
|||
CONFIG_SYS_PCI_TBATR4
|
||||
CONFIG_SYS_PCI_TBATR5
|
||||
CONFIG_SYS_PCI_VIRT
|
||||
CONFIG_SYS_PCMCIA_MEM_SIZE
|
||||
CONFIG_SYS_PDCNT
|
||||
CONFIG_SYS_PEHLPAR
|
||||
CONFIG_SYS_PEPAR
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user