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ARM: uniphier: refactor SBC init code

Browse Source 
Merge sbc-admulti.c and sbc-savepin.c into a single file to avoid
code duplication.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2017-01-15 14:59:05 +09:00
parent 8d6c99c66f
commit 9e3bb84bd8
15 changed files with 95 additions and 111 deletions
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27
arch/arm/mach-uniphier/init.h
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@ -46,31 +46,30 @@ int uniphier_ld11_init(const struct uniphier_board_data *bd);
int uniphier_ld20_init(const struct uniphier_board_data *bd);
#if defined(CONFIG_MICRO_SUPPORT_CARD)
int uniphier_sbc_init_admulti(const struct uniphier_board_data *bd);
int uniphier_sbc_init_savepin(const struct uniphier_board_data *bd);
int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_sbc_init(const struct uniphier_board_data *bd);
void uniphier_sbc_init_admulti(void);
void uniphier_sbc_init_savepin(void);
void uniphier_ld4_sbc_init(void);
void uniphier_pxs2_sbc_init(void);
void uniphier_ld11_sbc_init(void);
#else
static inline int uniphier_sbc_init_admulti(
const struct uniphier_board_data *bd)
static inline void uniphier_sbc_init_admulti(void)
{
return 0;
}
static inline int uniphier_sbc_init_savepin(
const struct uniphier_board_data *bd)
static inline void uniphier_sbc_init_savepin(void)
{
return 0;
}
static inline int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd)
static inline void uniphier_ld4_sbc_init(void)
{
return 0;
}
static inline int uniphier_pxs2_sbc_init(const struct uniphier_board_data *bd)
static inline void uniphier_pxs2_sbc_init(void)
{
}
static inline void uniphier_ld11_sbc_init(void)
{
return 0;
}
#endif

6
arch/arm/mach-uniphier/init/init-ld11.c
View File

@ -13,11 +13,7 @@
int uniphier_ld11_init(const struct uniphier_board_data *bd)
{
uniphier_sbc_init_savepin(bd);
uniphier_pxs2_sbc_init(bd);
/* pins for NAND and System Bus are multiplexed */
if (spl_boot_device() != BOOT_DEVICE_NAND)
uniphier_pin_init("system_bus_grp");
uniphier_ld11_sbc_init();
support_card_reset();

6
arch/arm/mach-uniphier/init/init-ld20.c
View File

@ -13,11 +13,7 @@
int uniphier_ld20_init(const struct uniphier_board_data *bd)
{
uniphier_sbc_init_savepin(bd);
uniphier_pxs2_sbc_init(bd);
/* pins for NAND and System Bus are multiplexed */
if (spl_boot_device() != BOOT_DEVICE_NAND)
uniphier_pin_init("system_bus_grp");
uniphier_ld11_sbc_init();
support_card_reset();

3
arch/arm/mach-uniphier/init/init-ld4.c
View File

@ -16,8 +16,7 @@ int uniphier_ld4_init(const struct uniphier_board_data *bd)
{
uniphier_ld4_bcu_init(bd);
uniphier_sbc_init_savepin(bd);
uniphier_ld4_sbc_init(bd);
uniphier_ld4_sbc_init();
support_card_reset();

2
arch/arm/mach-uniphier/init/init-pro4.c
View File

@ -14,7 +14,7 @@
int uniphier_pro4_init(const struct uniphier_board_data *bd)
{
uniphier_sbc_init_savepin(bd);
uniphier_sbc_init_savepin();
support_card_reset();

2
arch/arm/mach-uniphier/init/init-pro5.c
View File

@ -12,7 +12,7 @@
int uniphier_pro5_init(const struct uniphier_board_data *bd)
{
uniphier_sbc_init_savepin(bd);
uniphier_sbc_init_savepin();
support_card_reset();

3
arch/arm/mach-uniphier/init/init-pxs2.c
View File

@ -14,8 +14,7 @@ int uniphier_pxs2_init(const struct uniphier_board_data *bd)
{
int ret;
uniphier_sbc_init_savepin(bd);
uniphier_pxs2_sbc_init(bd);
uniphier_pxs2_sbc_init();
support_card_reset();

2
arch/arm/mach-uniphier/init/init-sld3.c
View File

@ -16,7 +16,7 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd)
{
uniphier_sld3_bcu_init(bd);
uniphier_sbc_init_admulti(bd);
uniphier_sbc_init_admulti();
support_card_reset();

3
arch/arm/mach-uniphier/init/init-sld8.c
View File

@ -16,8 +16,7 @@ int uniphier_sld8_init(const struct uniphier_board_data *bd)
{
uniphier_ld4_bcu_init(bd);
uniphier_sbc_init_savepin(bd);
uniphier_ld4_sbc_init(bd);
uniphier_ld4_sbc_init();
support_card_reset();

17
arch/arm/mach-uniphier/sbc/Makefile
View File

@ -2,12 +2,11 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += sbc-admulti.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += sbc-savepin.o sbc-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += sbc-savepin.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += sbc-savepin.o sbc-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += sbc-savepin.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-savepin.o sbc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-savepin.o sbc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += sbc-savepin.o sbc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-savepin.o sbc-pxs2.o
obj-y += sbc.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += sbc-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += sbc-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += sbc-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-ld11.o

53
arch/arm/mach-uniphier/sbc/sbc-admulti.c
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@ -1,53 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include "../init.h"
#include "../sg-regs.h"
#include "sbc-regs.h"
#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
int uniphier_sbc_init_admulti(const struct uniphier_board_data *bd)
{
/*
* Only CS1 is connected to support card.
* BKSZ[1:0] should be set to "01".
*/
writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
if (boot_is_swapped()) {
/*
* Boot Swap On: boot from external NOR/SRAM
* 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
*
* 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
* 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
*/
writel(0x0000bc01, SBBASE0);
} else {
/*
* Boot Swap Off: boot from mask ROM
* 0x40000000-0x41ffffff: mask ROM
* 0x42000000-0x43efffff: memory bank (31MB)
* 0x43f00000-0x43ffffff: peripherals (1MB)
*/
writel(0x0000be01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);
}
return 0;
}

25
arch/arm/mach-uniphier/sbc/sbc-ld11.c Normal file
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@ -0,0 +1,25 @@
/*
* Copyright (C) 2016-2017 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <linux/io.h>
#include "../init.h"
#include "sbc-regs.h"
void uniphier_ld11_sbc_init(void)
{
uniphier_sbc_init_savepin();
/* necessary for ROM boot ?? */
/* system bus output enable */
writel(0x17, PC0CTRL);
/* pins for NAND and System Bus are multiplexed */
if (spl_boot_device() != BOOT_DEVICE_NAND)
uniphier_pin_init("system_bus_grp");
}

9
arch/arm/mach-uniphier/sbc/sbc-ld4.c
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2011-2016 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2011-2015 Panasonic Corporation
* Copyright (C) 2015-2017 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -9,14 +10,14 @@
#include "../init.h"
#include "sbc-regs.h"
int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd)
void uniphier_ld4_sbc_init(void)
{
u32 tmp;
uniphier_sbc_init_savepin();
/* system bus output enable */
tmp = readl(PC0CTRL);
tmp &= 0xfffffcff;
writel(tmp, PC0CTRL);
return 0;
}

8
arch/arm/mach-uniphier/sbc/sbc-pxs2.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2015-2016 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2016-2017 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -9,11 +9,11 @@
#include "../init.h"
#include "sbc-regs.h"
int uniphier_pxs2_sbc_init(const struct uniphier_board_data *bd)
void uniphier_pxs2_sbc_init(void)
{
uniphier_sbc_init_savepin();
/* necessary for ROM boot ?? */
/* system bus output enable */
writel(0x17, PC0CTRL);
return 0;
}

40
arch/arm/mach-uniphier/sbc/sbc-savepin.c → arch/arm/mach-uniphier/sbc/sbc.c
View File

@ -1,5 +1,7 @@
/*
* Copyright (C) 2011-2016 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2011-2015 Panasonic Corporation
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -9,6 +11,14 @@
#include "../init.h"
#include "sbc-regs.h"
#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
/* slower but LED works */
#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
@ -22,16 +32,22 @@
#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
int uniphier_sbc_init_savepin(const struct uniphier_board_data *bd)
static void __uniphier_sbc_init(int savepin)
{
/*
* Only CS1 is connected to support card.
* BKSZ[1:0] should be set to "01".
*/
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
if (savepin) {
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
} else {
writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
}
if (boot_is_swapped()) {
/*
@ -52,6 +68,14 @@ int uniphier_sbc_init_savepin(const struct uniphier_board_data *bd)
writel(0x0000be01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);
}
return 0;
}
void uniphier_sbc_init_admulti(void)
{
__uniphier_sbc_init(0);
}
void uniphier_sbc_init_savepin(void)
{
__uniphier_sbc_init(1);
}