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Exynos5: Fix exynos5_get_periph_rate calculations

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exynos5_get_periph_rate function reads incorrect div for
SDMMC2 & 3. It also reads prediv and does division only for
SDMMC0 & 2 when actually various other peripherals need that.
Adding changes to fix these mistakes in periph rate calculation.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Akshay Saraswat 2015-02-04 16:00:02 +05:30 committed by Minkyu Kang
parent ecdfb4e9d2
commit 9deff10746
1 changed files with 13 additions and 8 deletions
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21
arch/arm/cpu/armv7/exynos/clock.c
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@ -362,8 +362,8 @@ static struct clk_bit_info *get_clk_bit_info(int peripheral)
static unsigned long exynos5_get_periph_rate(int peripheral) static unsigned long exynos5_get_periph_rate(int peripheral)
{ {
struct clk_bit_info *bit_info = get_clk_bit_info(peripheral); struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
unsigned long sclk, sub_clk; unsigned long sclk, sub_clk = 0;
unsigned int src, div, sub_div; unsigned int src, div, sub_div = 0;
struct exynos5_clock *clk = struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock(); (struct exynos5_clock *)samsung_get_base_clock();
@ -402,10 +402,13 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
break; break;
case PERIPH_ID_SDMMC0: case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC1:
src = readl(&clk->src_fsys);
div = readl(&clk->div_fsys1);
break;
case PERIPH_ID_SDMMC2: case PERIPH_ID_SDMMC2:
case PERIPH_ID_SDMMC3: case PERIPH_ID_SDMMC3:
src = readl(&clk->src_fsys); src = readl(&clk->src_fsys);
div = readl(&clk->div_fsys1); div = readl(&clk->div_fsys2);
break; break;
case PERIPH_ID_I2C0: case PERIPH_ID_I2C0:
case PERIPH_ID_I2C1: case PERIPH_ID_I2C1:
@ -426,7 +429,8 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
return -1; return -1;
}; };
src = (src >> bit_info->src_bit) & 0xf; if (bit_info->src_bit >= 0)
src = (src >> bit_info->src_bit) & 0xf;
switch (src) { switch (src) {
case EXYNOS_SRC_MPLL: case EXYNOS_SRC_MPLL:
@ -443,11 +447,12 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
} }
/* Ratio clock division for this peripheral */ /* Ratio clock division for this peripheral */
sub_div = (div >> bit_info->div_bit) & 0xf; if (bit_info->div_bit >= 0) {
sub_clk = sclk / (sub_div + 1); sub_div = (div >> bit_info->div_bit) & 0xf;
sub_clk = sclk / (sub_div + 1);
}
/* Pre-ratio clock division for SDMMC0 and 2 */ if (bit_info->prediv_bit >= 0) {
if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
div = (div >> bit_info->prediv_bit) & 0xff; div = (div >> bit_info->prediv_bit) & 0xff;
return sub_clk / (div + 1); return sub_clk / (div + 1);
} }