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pxa: fix memory coherency problem after relocation

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On the xscale, the icache must be invalidated and the write buffers drained
after writing code over the data bus, even if the caches are disabled.  Tested
on the pxa270.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
This commit is contained in:
Mike Dunn 2013-06-21 09:12:28 -07:00 committed by Marek Vasut
parent 84c617beb2
commit 9dc8fef258
1 changed files with 9 additions and 0 deletions
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9
arch/arm/lib/relocate.S
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@ -70,6 +70,15 @@ fixnext:
relocate_done:
#ifdef __XSCALE__
/*
* On xscale, icache must be invalidated and write buffers drained,
* even with cache disabled - 4.2.7 of xscale core developer's manual
*/
mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */
mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
#endif
/* ARMv4- don't know bx lr but the assembler fails to see that */
#ifdef __ARM_ARCH_4__