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https://github.com/brain-hackers/u-boot-brain
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ARM: uniphier: add simple eMMC load APIs instead of ROM API
Re-use of routines embedded in the Boot ROM requires a function pointer table for each SoC. This is not nice in terms of the maintainability in a long run. Implement simple eMMC load APIs that are commonly used for LD11, LD20, and hopefully future SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada
parent
2af94aafa5
commit
9d35873161
@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Copyright (C) 2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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@ -7,87 +7,218 @@
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#include <common.h>
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#include <spl.h>
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#include <linux/bitops.h>
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#include <linux/compat.h>
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#include <linux/io.h>
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#include <asm/processor.h>
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#include "../soc-info.h"
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struct uniphier_romfunc_table {
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void *mmc_send_cmd;
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void *mmc_card_blockaddr;
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void *mmc_switch_part;
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void *mmc_load_image;
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#define MMC_CMD_SWITCH 6
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#define MMC_CMD_SELECT_CARD 7
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#define MMC_CMD_SEND_CSD 9
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#define MMC_CMD_READ_MULTIPLE_BLOCK 18
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#define EXT_CSD_PART_CONF 179 /* R/W */
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#define MMC_RSP_PRESENT BIT(0)
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#define MMC_RSP_136 BIT(1) /* 136 bit response */
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#define MMC_RSP_CRC BIT(2) /* expect valid crc */
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#define MMC_RSP_BUSY BIT(3) /* card may send busy */
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#define MMC_RSP_OPCODE BIT(4) /* response contains opcode */
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#define MMC_RSP_NONE (0)
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#define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
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#define MMC_RSP_R1b (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | \
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MMC_RSP_BUSY)
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#define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
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#define MMC_RSP_R3 (MMC_RSP_PRESENT)
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#define MMC_RSP_R4 (MMC_RSP_PRESENT)
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#define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
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#define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
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#define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
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#define SDHCI_DMA_ADDRESS 0x00
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#define SDHCI_BLOCK_SIZE 0x04
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#define SDHCI_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF))
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#define SDHCI_BLOCK_COUNT 0x06
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#define SDHCI_ARGUMENT 0x08
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#define SDHCI_TRANSFER_MODE 0x0C
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#define SDHCI_TRNS_DMA BIT(0)
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#define SDHCI_TRNS_BLK_CNT_EN BIT(1)
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#define SDHCI_TRNS_ACMD12 BIT(2)
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#define SDHCI_TRNS_READ BIT(4)
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#define SDHCI_TRNS_MULTI BIT(5)
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#define SDHCI_COMMAND 0x0E
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#define SDHCI_CMD_RESP_MASK 0x03
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#define SDHCI_CMD_CRC 0x08
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#define SDHCI_CMD_INDEX 0x10
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#define SDHCI_CMD_DATA 0x20
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#define SDHCI_CMD_ABORTCMD 0xC0
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#define SDHCI_CMD_RESP_NONE 0x00
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#define SDHCI_CMD_RESP_LONG 0x01
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#define SDHCI_CMD_RESP_SHORT 0x02
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#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
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#define SDHCI_MAKE_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff))
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#define SDHCI_RESPONSE 0x10
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#define SDHCI_HOST_CONTROL 0x28
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#define SDHCI_CTRL_DMA_MASK 0x18
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#define SDHCI_CTRL_SDMA 0x00
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#define SDHCI_BLOCK_GAP_CONTROL 0x2A
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#define SDHCI_SOFTWARE_RESET 0x2F
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#define SDHCI_RESET_CMD 0x02
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#define SDHCI_RESET_DATA 0x04
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#define SDHCI_INT_STATUS 0x30
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#define SDHCI_INT_RESPONSE BIT(0)
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#define SDHCI_INT_DATA_END BIT(1)
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#define SDHCI_INT_ERROR BIT(15)
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#define SDHCI_SIGNAL_ENABLE 0x38
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/* RCA assigned by Boot ROM */
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#define UNIPHIER_EMMC_RCA 0x1000
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struct uniphier_mmc_cmd {
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unsigned int cmdidx;
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unsigned int resp_type;
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unsigned int cmdarg;
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unsigned int is_data;
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};
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static const struct uniphier_romfunc_table uniphier_ld11_romfunc_table = {
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.mmc_send_cmd = (void *)0x20d8,
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.mmc_card_blockaddr = (void *)0x1b68,
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.mmc_switch_part = (void *)0x1c38,
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.mmc_load_image = (void *)0x2e48,
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};
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static const struct uniphier_romfunc_table uniphier_ld20_romfunc_table = {
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.mmc_send_cmd = (void *)0x2130,
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.mmc_card_blockaddr = (void *)0x1ba0,
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.mmc_switch_part = (void *)0x1c70,
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.mmc_load_image = (void *)0x2ef0,
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};
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int uniphier_rom_get_mmc_funcptr(int (**send_cmd)(u32, u32),
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int (**card_blockaddr)(u32),
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int (**switch_part)(int),
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int (**load_image)(u32, uintptr_t, u32))
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static int uniphier_emmc_send_cmd(void __iomem *host_base,
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struct uniphier_mmc_cmd *cmd)
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{
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const struct uniphier_romfunc_table *table;
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u32 mode = 0;
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u32 mask = SDHCI_INT_RESPONSE;
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u32 stat, flags;
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switch (uniphier_get_soc_id()) {
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case UNIPHIER_LD11_ID:
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table = &uniphier_ld11_romfunc_table;
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break;
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case UNIPHIER_LD20_ID:
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table = &uniphier_ld20_romfunc_table;
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break;
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default:
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printf("unsupported SoC\n");
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return -EINVAL;
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}
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writel(U32_MAX, host_base + SDHCI_INT_STATUS);
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writel(0, host_base + SDHCI_SIGNAL_ENABLE);
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writel(cmd->cmdarg, host_base + SDHCI_ARGUMENT);
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*send_cmd = table->mmc_send_cmd;
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*card_blockaddr = table->mmc_card_blockaddr;
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*switch_part = table->mmc_switch_part;
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*load_image = table->mmc_load_image;
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if (cmd->is_data)
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mode = SDHCI_TRNS_DMA | SDHCI_TRNS_BLK_CNT_EN |
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SDHCI_TRNS_ACMD12 | SDHCI_TRNS_READ |
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SDHCI_TRNS_MULTI;
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writew(mode, host_base + SDHCI_TRANSFER_MODE);
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if (!(cmd->resp_type & MMC_RSP_PRESENT))
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flags = SDHCI_CMD_RESP_NONE;
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else if (cmd->resp_type & MMC_RSP_136)
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flags = SDHCI_CMD_RESP_LONG;
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else if (cmd->resp_type & MMC_RSP_BUSY)
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flags = SDHCI_CMD_RESP_SHORT_BUSY;
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else
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flags = SDHCI_CMD_RESP_SHORT;
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if (cmd->resp_type & MMC_RSP_CRC)
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flags |= SDHCI_CMD_CRC;
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if (cmd->resp_type & MMC_RSP_OPCODE)
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flags |= SDHCI_CMD_INDEX;
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if (cmd->is_data)
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flags |= SDHCI_CMD_DATA;
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if (cmd->resp_type & MMC_RSP_BUSY || cmd->is_data)
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mask |= SDHCI_INT_DATA_END;
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writew(SDHCI_MAKE_CMD(cmd->cmdidx, flags), host_base + SDHCI_COMMAND);
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do {
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stat = readl(host_base + SDHCI_INT_STATUS);
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if (stat & SDHCI_INT_ERROR)
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return -EIO;
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} while ((stat & mask) != mask);
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return 0;
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}
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static int uniphier_emmc_switch_part(void __iomem *host_base, int part_num)
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{
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struct uniphier_mmc_cmd cmd = {};
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cmd.cmdidx = MMC_CMD_SWITCH;
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cmd.resp_type = MMC_RSP_R1b;
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cmd.cmdarg = (EXT_CSD_PART_CONF << 16) | (part_num << 8) | (3 << 24);
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return uniphier_emmc_send_cmd(host_base, &cmd);
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}
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static int uniphier_emmc_is_over_2gb(void __iomem *host_base)
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{
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struct uniphier_mmc_cmd cmd = {};
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u32 csd40, csd72; /* CSD[71:40], CSD[103:72] */
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int ret;
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cmd.cmdidx = MMC_CMD_SEND_CSD;
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cmd.resp_type = MMC_RSP_R2;
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cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
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ret = uniphier_emmc_send_cmd(host_base, &cmd);
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if (ret)
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return ret;
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csd40 = readl(host_base + SDHCI_RESPONSE + 4);
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csd72 = readl(host_base + SDHCI_RESPONSE + 8);
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return !(~csd40 & 0xffc00380) && !(~csd72 & 0x3);
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}
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static int uniphier_emmc_load_image(void __iomem *host_base, u32 dev_addr,
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unsigned long load_addr, u32 block_cnt)
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{
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struct uniphier_mmc_cmd cmd = {};
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u8 tmp;
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WARN_ON(load_addr >> 32);
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writel(load_addr, host_base + SDHCI_DMA_ADDRESS);
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writew(SDHCI_MAKE_BLKSZ(7, 512), host_base + SDHCI_BLOCK_SIZE);
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writew(block_cnt, host_base + SDHCI_BLOCK_COUNT);
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tmp = readb(host_base + SDHCI_HOST_CONTROL);
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tmp &= ~SDHCI_CTRL_DMA_MASK;
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tmp |= SDHCI_CTRL_SDMA;
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writeb(tmp, host_base + SDHCI_HOST_CONTROL);
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tmp = readb(host_base + SDHCI_BLOCK_GAP_CONTROL);
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tmp &= ~1; /* clear Stop At Block Gap Request */
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writeb(tmp, host_base + SDHCI_BLOCK_GAP_CONTROL);
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cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
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cmd.resp_type = MMC_RSP_R1;
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cmd.cmdarg = dev_addr;
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cmd.is_data = 1;
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return uniphier_emmc_send_cmd(host_base, &cmd);
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}
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static int spl_board_load_image(struct spl_image_info *spl_image,
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struct spl_boot_device *bootdev)
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{
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int (*send_cmd)(u32 cmd, u32 arg);
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int (*card_blockaddr)(u32 rca);
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int (*switch_part)(int part);
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int (*load_image)(u32 dev_addr, uintptr_t load_addr, u32 block_cnt);
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u32 dev_addr = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
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const u32 rca = 0x1000; /* RCA assigned by Boot ROM */
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void __iomem *host_base = (void __iomem *)0x5a000200;
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struct uniphier_mmc_cmd cmd = {};
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int ret;
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ret = uniphier_rom_get_mmc_funcptr(&send_cmd, &card_blockaddr,
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&switch_part, &load_image);
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if (ret)
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return ret;
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/*
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* deselect card before SEND_CSD command.
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* Do not check the return code. It fails, but it is OK.
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*/
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(*send_cmd)(0x071a0000, 0); /* CMD7 (arg=0) */
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cmd.cmdidx = MMC_CMD_SELECT_CARD;
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cmd.resp_type = MMC_RSP_R1;
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uniphier_emmc_send_cmd(host_base, &cmd); /* CMD7 (arg=0) */
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/* reset CMD Line */
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writeb(0x6, 0x5a00022f);
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while (readb(0x5a00022f))
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writeb(SDHCI_RESET_CMD | SDHCI_RESET_DATA,
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host_base + SDHCI_SOFTWARE_RESET);
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while (readb(host_base + SDHCI_SOFTWARE_RESET))
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cpu_relax();
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ret = (*card_blockaddr)(rca);
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ret = uniphier_emmc_is_over_2gb(host_base);
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if (ret < 0)
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return ret;
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if (ret) {
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debug("card is block addressing\n");
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} else {
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@ -95,15 +226,20 @@ static int spl_board_load_image(struct spl_image_info *spl_image,
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dev_addr *= 512;
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}
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ret = (*send_cmd)(0x071a0000, rca << 16); /* CMD7: select card again */
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cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
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/* select card again */
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ret = uniphier_emmc_send_cmd(host_base, &cmd);
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if (ret)
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printf("failed to select card\n");
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ret = (*switch_part)(1); /* Switch to Boot Partition 1 */
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/* Switch to Boot Partition 1 */
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ret = uniphier_emmc_switch_part(host_base, 1);
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if (ret)
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printf("failed to switch partition\n");
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ret = (*load_image)(dev_addr, CONFIG_SYS_TEXT_BASE, 1);
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ret = uniphier_emmc_load_image(host_base, dev_addr,
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CONFIG_SYS_TEXT_BASE, 1);
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if (ret) {
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printf("failed to load image\n");
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return ret;
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@ -113,8 +249,9 @@ static int spl_board_load_image(struct spl_image_info *spl_image,
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if (ret)
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return ret;
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ret = (*load_image)(dev_addr, spl_image->load_addr,
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spl_image->size / 512);
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ret = uniphier_emmc_load_image(host_base, dev_addr,
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spl_image->load_addr,
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spl_image->size / 512);
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if (ret) {
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printf("failed to load image\n");
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return ret;
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