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ARM: tegra: rename OUT_CLK_SOURCE_*
OUT_CLK_SOURCE_ are currently named after the number of bits the mask they represent includes. However, bit count is not the only possible variable; bit position may also vary. Rename OUT_CLK_SOURCE_ to OUT_CLK_SOURCE_31_30_ and OUT_CLK_SOURCE4_ to OUT_CLK_SOURCE_31_28 to more completely describe exactly what they represent, without having to go look up the definitions. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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@ -142,8 +142,8 @@ void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
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value = readl(reg);
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value = readl(reg);
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value &= ~OUT_CLK_SOURCE_MASK;
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value &= ~OUT_CLK_SOURCE_31_30_MASK;
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value |= source << OUT_CLK_SOURCE_SHIFT;
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value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
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value &= ~OUT_CLK_DIVISOR_MASK;
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value &= ~OUT_CLK_DIVISOR_MASK;
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value |= divisor << OUT_CLK_DIVISOR_SHIFT;
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value |= divisor << OUT_CLK_DIVISOR_SHIFT;
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@ -155,8 +155,8 @@ void clock_ll_set_source(enum periph_id periph_id, unsigned source)
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{
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{
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u32 *reg = get_periph_source_reg(periph_id);
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u32 *reg = get_periph_source_reg(periph_id);
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clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
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clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
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source << OUT_CLK_SOURCE_SHIFT);
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source << OUT_CLK_SOURCE_31_30_SHIFT);
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}
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}
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/**
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/**
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@ -305,11 +305,11 @@ static int adjust_periph_pll(enum periph_id periph_id, int source,
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if (source < 0)
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if (source < 0)
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return -1;
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return -1;
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if (mux_bits == 4) {
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if (mux_bits == 4) {
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clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
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clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
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source << OUT_CLK_SOURCE4_SHIFT);
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source << OUT_CLK_SOURCE_31_28_SHIFT);
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} else {
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} else {
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clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
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clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
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source << OUT_CLK_SOURCE_SHIFT);
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source << OUT_CLK_SOURCE_31_30_SHIFT);
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}
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}
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udelay(2);
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udelay(2);
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return 0;
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return 0;
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@ -233,11 +233,12 @@ enum {
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#define OUT_CLK_DIVISOR_SHIFT 0
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#define OUT_CLK_DIVISOR_SHIFT 0
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#define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT)
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#define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT)
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#define OUT_CLK_SOURCE_SHIFT 30
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#define OUT_CLK_SOURCE_31_30_SHIFT 30
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#define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT)
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#define OUT_CLK_SOURCE_31_30_MASK (3U << OUT_CLK_SOURCE_31_30_SHIFT)
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#define OUT_CLK_SOURCE4_SHIFT 28
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/* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */
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#define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT)
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#define OUT_CLK_SOURCE_31_28_SHIFT 28
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#define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT)
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/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
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/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
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#define SCLK_SYS_STATE_SHIFT 28U
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#define SCLK_SYS_STATE_SHIFT 28U
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