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ARM: DRA72: sdram: Update sdram ext phy configuration for SR2.0
Based on data from EMIF configuration tool 1.1.1. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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parent
3d042e468a
commit
9c90f5135e
@ -398,6 +398,45 @@ dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
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0x0
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0x0
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};
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};
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const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = {
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0x04040100,
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0x006B009F,
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0x006B00A2,
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0x006B00A8,
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0x006B00A8,
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0x006B00B2,
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0x002F002F,
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0x002F002F,
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0x002F002F,
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0x002F002F,
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0x002F002F,
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0x00600073,
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0x00600071,
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0x0060007C,
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0x0060007E,
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0x00600084,
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0x00400053,
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0x00400051,
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0x0040005C,
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0x0040005E,
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0x00400064,
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0x00800080,
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0x00800080,
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0x40010080,
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0x08102040,
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0x005B008F,
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0x005B0092,
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0x005B0098,
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0x005B0098,
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0x005B00A2,
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0x00300043,
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0x00300041,
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0x0030004C,
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0x0030004E,
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0x00300054,
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0x00000077
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};
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const struct lpddr2_mr_regs mr_regs = {
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const struct lpddr2_mr_regs mr_regs = {
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.mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
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.mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
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.mr2 = 0x6,
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.mr2 = 0x6,
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@ -438,10 +477,13 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
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}
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}
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break;
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break;
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case DRA722_ES1_0:
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case DRA722_ES1_0:
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case DRA722_ES2_0:
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*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
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*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
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*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
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*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
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break;
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break;
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case DRA722_ES2_0:
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*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
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*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
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break;
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default:
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default:
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*regs = ddr3_ext_phy_ctrl_const_base_es2;
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*regs = ddr3_ext_phy_ctrl_const_base_es2;
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*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
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*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
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