mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
gdsys: mpc8308: Fix style violations
Fix some style violations in the gdsys MPC8308 board files, and make the code more readable. Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
Mario Six
parent
3f902185f0
commit
9c454827f1
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@ -35,11 +35,11 @@
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#define MAX_MUX_CHANNELS 2
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enum {
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MCFPGA_DONE = 1 << 0,
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MCFPGA_INIT_N = 1 << 1,
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MCFPGA_PROGRAM_N = 1 << 2,
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MCFPGA_UPDATE_ENABLE_N = 1 << 3,
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MCFPGA_RESET_N = 1 << 4,
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MCFPGA_DONE = BIT(0),
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MCFPGA_INIT_N = BIT(1),
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MCFPGA_PROGRAM_N = BIT(2),
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MCFPGA_UPDATE_ENABLE_N = BIT(3),
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MCFPGA_RESET_N = BIT(4),
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};
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enum {
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@ -47,7 +47,7 @@ enum {
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GPIO_MDIO = 1 << 15,
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};
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unsigned int mclink_fpgacount;
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uint mclink_fpgacount;
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struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
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struct {
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@ -107,7 +107,7 @@ int checkboard(void)
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printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
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if (s != NULL) {
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if (s) {
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puts(", serial# ");
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puts(s);
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}
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@ -120,12 +120,11 @@ int checkboard(void)
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int last_stage_init(void)
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{
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int slaves;
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unsigned int k;
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unsigned int mux_ch;
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unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
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uint k;
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uchar mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
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u16 fpga_features;
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bool hw_type_cat = pca9698_get_value(0x20, 20);
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bool ch0_rgmii2_present = false;
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bool ch0_rgmii2_present;
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FPGA_GET_REG(0, fpga_features, &fpga_features);
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@ -137,16 +136,16 @@ int last_stage_init(void)
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/* wait for FPGA done, then reset FPGA */
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for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
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unsigned int ctr = 0;
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uint ctr = 0;
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if (i2c_probe(mclink_controllers[k]))
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continue;
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while (!(pca953x_get_val(mclink_controllers[k])
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& MCFPGA_DONE)) {
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udelay(100000);
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mdelay(100);
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if (ctr++ > 5) {
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printf("no done for mclink_controller %d\n", k);
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printf("no done for mclink_controller %u\n", k);
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break;
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}
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}
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@ -159,8 +158,10 @@ int last_stage_init(void)
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}
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if (hw_type_cat) {
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uint mux_ch;
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int retval;
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struct mii_dev *mdiodev = mdio_alloc();
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if (!mdiodev)
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return -ENOMEM;
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strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
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@ -179,7 +180,7 @@ int last_stage_init(void)
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}
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/* give slave-PLLs and Parade DP501 some time to be up and running */
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udelay(500000);
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mdelay(500);
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mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
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slaves = mclink_probe();
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@ -207,6 +208,7 @@ int last_stage_init(void)
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if (hw_type_cat) {
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int retval;
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struct mii_dev *mdiodev = mdio_alloc();
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if (!mdiodev)
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return -ENOMEM;
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strncpy(mdiodev->name, bb_miiphy_buses[k].name,
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@ -233,17 +235,17 @@ int last_stage_init(void)
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* provide access to fpga gpios and controls (for I2C bitbang)
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* (these may look all too simple but make iocon.h much more readable)
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*/
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void fpga_gpio_set(unsigned int bus, int pin)
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void fpga_gpio_set(uint bus, int pin)
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{
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FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
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}
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void fpga_gpio_clear(unsigned int bus, int pin)
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void fpga_gpio_clear(uint bus, int pin)
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{
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FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
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}
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int fpga_gpio_get(unsigned int bus, int pin)
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int fpga_gpio_get(uint bus, int pin)
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{
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u16 val;
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@ -252,7 +254,7 @@ int fpga_gpio_get(unsigned int bus, int pin)
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return val & pin;
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}
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void fpga_control_set(unsigned int bus, int pin)
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void fpga_control_set(uint bus, int pin)
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{
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u16 val;
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@ -260,7 +262,7 @@ void fpga_control_set(unsigned int bus, int pin)
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FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin);
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}
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void fpga_control_clear(unsigned int bus, int pin)
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void fpga_control_clear(uint bus, int pin)
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{
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u16 val;
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@ -273,7 +275,7 @@ void mpc8308_init(void)
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pca9698_direction_output(0x20, 4, 1);
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}
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void mpc8308_set_fpga_reset(unsigned state)
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void mpc8308_set_fpga_reset(uint state)
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{
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pca9698_set_value(0x20, 4, state ? 0 : 1);
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}
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@ -285,11 +287,11 @@ void mpc8308_setup_hw(void)
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/*
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* set "startup-finished"-gpios
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*/
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setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
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setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
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setbits_be32(&immr->gpio[0].dir, (BIT(31 - 11) | BIT(31 - 12)));
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setbits_be32(&immr->gpio[0].dat, BIT(31 - 12));
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}
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int mpc8308_get_fpga_done(unsigned fpga)
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int mpc8308_get_fpga_done(uint fpga)
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{
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return pca9698_get_value(0x20, 19);
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}
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@ -367,7 +369,7 @@ int ft_board_setup(void *blob, bd_t *bd)
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*/
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struct fpga_mii {
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unsigned fpga;
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uint fpga;
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int mdio;
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} fpga_mii[] = {
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{ 0, 1},
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@ -494,5 +496,4 @@ struct bb_miiphy_bus bb_miiphy_buses[] = {
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},
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};
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int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
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sizeof(bb_miiphy_buses[0]);
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int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
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@ -24,14 +24,14 @@
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DECLARE_GLOBAL_DATA_PTR;
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int get_fpga_state(unsigned dev)
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int get_fpga_state(uint dev)
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{
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return gd->arch.fpga_state[dev];
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}
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int board_early_init_f(void)
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{
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unsigned k;
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uint k;
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
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gd->arch.fpga_state[k] = 0;
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@ -41,8 +41,8 @@ int board_early_init_f(void)
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int board_early_init_r(void)
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{
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unsigned k;
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unsigned ctr;
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uint k;
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uint ctr;
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
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gd->arch.fpga_state[k] = 0;
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@ -59,7 +59,7 @@ int board_early_init_r(void)
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
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ctr = 0;
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while (!mpc8308_get_fpga_done(k)) {
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udelay(100000);
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mdelay(100);
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if (ctr++ > 5) {
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gd->arch.fpga_state[k] |=
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FPGA_STATE_DONE_FAILED;
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@ -86,7 +86,7 @@ int board_early_init_r(void)
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if (val == REFLECTION_TESTPATTERN_INV)
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break;
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udelay(100000);
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mdelay(100);
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if (ctr++ > 5) {
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gd->arch.fpga_state[k] |=
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FPGA_STATE_REFLECTION_FAILED;
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@ -50,7 +50,7 @@ enum {
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GPIO_MDIO = 1 << 15,
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};
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unsigned int mclink_fpgacount;
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uint mclink_fpgacount;
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struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
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struct {
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@ -110,7 +110,7 @@ int checkboard(void)
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printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
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if (s != NULL) {
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if (s) {
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puts(", serial# ");
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puts(s);
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}
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@ -123,17 +123,17 @@ int checkboard(void)
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int last_stage_init(void)
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{
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int slaves;
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unsigned int k;
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unsigned int mux_ch;
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unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
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uint k;
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uint mux_ch;
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uchar mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
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#ifdef CONFIG_STRIDER_CPU
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unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
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uchar mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
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#endif
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bool hw_type_cat = pca9698_get_value(0x20, 18);
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#ifdef CONFIG_STRIDER_CON_DP
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bool is_dh = pca9698_get_value(0x20, 25);
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#endif
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bool ch0_sgmii2_present = false;
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bool ch0_sgmii2_present;
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/* Turn on Analog Devices ADV7611 */
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pca9698_direction_output(0x20, 8, 0);
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@ -146,8 +146,8 @@ int last_stage_init(void)
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/* wait for FPGA done, then reset FPGA */
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for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
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unsigned int ctr = 0;
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unsigned char *mclink_controllers = mclink_controllers_dvi;
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uint ctr = 0;
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uchar *mclink_controllers = mclink_controllers_dvi;
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#ifdef CONFIG_STRIDER_CPU
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if (i2c_probe(mclink_controllers[k])) {
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@ -161,7 +161,7 @@ int last_stage_init(void)
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#endif
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while (!(pca953x_get_val(mclink_controllers[k])
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& MCFPGA_DONE)) {
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udelay(100000);
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mdelay(100);
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if (ctr++ > 5) {
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printf("no done for mclink_controller %d\n", k);
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break;
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@ -178,6 +178,7 @@ int last_stage_init(void)
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if (hw_type_cat) {
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int retval;
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struct mii_dev *mdiodev = mdio_alloc();
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if (!mdiodev)
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return -ENOMEM;
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strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
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@ -196,7 +197,7 @@ int last_stage_init(void)
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}
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/* give slave-PLLs and Parade DP501 some time to be up and running */
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udelay(500000);
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mdelay(500);
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mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
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slaves = mclink_probe();
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@ -235,7 +236,7 @@ int last_stage_init(void)
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for (k = 1; k <= slaves; ++k)
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FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
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udelay(500000);
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mdelay(500);
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#endif
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for (k = 1; k <= slaves; ++k) {
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@ -260,6 +261,7 @@ int last_stage_init(void)
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if (hw_type_cat) {
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int retval;
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struct mii_dev *mdiodev = mdio_alloc();
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if (!mdiodev)
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return -ENOMEM;
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strncpy(mdiodev->name, bb_miiphy_buses[k].name,
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@ -286,17 +288,17 @@ int last_stage_init(void)
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* provide access to fpga gpios (for I2C bitbang)
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* (these may look all too simple but make iocon.h much more readable)
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*/
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void fpga_gpio_set(unsigned int bus, int pin)
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void fpga_gpio_set(uint bus, int pin)
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{
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FPGA_SET_REG(bus, gpio.set, pin);
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}
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void fpga_gpio_clear(unsigned int bus, int pin)
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void fpga_gpio_clear(uint bus, int pin)
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{
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FPGA_SET_REG(bus, gpio.clear, pin);
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}
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int fpga_gpio_get(unsigned int bus, int pin)
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int fpga_gpio_get(uint bus, int pin)
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{
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u16 val;
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@ -306,7 +308,7 @@ int fpga_gpio_get(unsigned int bus, int pin)
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}
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#ifdef CONFIG_STRIDER_CON_DP
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void fpga_control_set(unsigned int bus, int pin)
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void fpga_control_set(uint bus, int pin)
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{
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u16 val;
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@ -314,7 +316,7 @@ void fpga_control_set(unsigned int bus, int pin)
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FPGA_SET_REG(bus, control, val | pin);
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}
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void fpga_control_clear(unsigned int bus, int pin)
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void fpga_control_clear(uint bus, int pin)
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{
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u16 val;
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@ -328,7 +330,7 @@ void mpc8308_init(void)
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pca9698_direction_output(0x20, 26, 1);
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}
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void mpc8308_set_fpga_reset(unsigned state)
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void mpc8308_set_fpga_reset(uint state)
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{
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pca9698_set_value(0x20, 26, state ? 0 : 1);
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}
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@ -340,11 +342,11 @@ void mpc8308_setup_hw(void)
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/*
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* set "startup-finished"-gpios
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*/
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setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
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setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
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setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
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setbits_be32(&immr->gpio[0].dat, BIT(31 - 12));
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}
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int mpc8308_get_fpga_done(unsigned fpga)
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int mpc8308_get_fpga_done(uint fpga)
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{
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return pca9698_get_value(0x20, 20);
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}
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@ -422,7 +424,7 @@ int ft_board_setup(void *blob, bd_t *bd)
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*/
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struct fpga_mii {
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unsigned fpga;
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uint fpga;
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int mdio;
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} fpga_mii[] = {
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{ 0, 1},
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@ -549,5 +551,4 @@ struct bb_miiphy_bus bb_miiphy_buses[] = {
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},
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};
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int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
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sizeof(bb_miiphy_buses[0]);
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int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
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