clk: zynq: Add dummy clock enable function
A lot of Xilinx drivers are checking -ENOSYS which means that clock driver
doesn't have enable function. Remove this checking from drivers and create
dummy enable function as was done for clk_fixed_rate driver by
commit 6bf6d81c11
("clk: fixed_rate: add dummy enable() function").
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
parent
3aba25bc38
commit
9b7aac7536
|
@ -444,11 +444,21 @@ static ulong zynq_clk_get_rate(struct clk *clk)
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
static int dummy_enable(struct clk *clk)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* Add implementation but by default all clocks are enabled
|
||||||
|
* after power up which is only one supported case now.
|
||||||
|
*/
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
static struct clk_ops zynq_clk_ops = {
|
static struct clk_ops zynq_clk_ops = {
|
||||||
.get_rate = zynq_clk_get_rate,
|
.get_rate = zynq_clk_get_rate,
|
||||||
#ifndef CONFIG_SPL_BUILD
|
#ifndef CONFIG_SPL_BUILD
|
||||||
.set_rate = zynq_clk_set_rate,
|
.set_rate = zynq_clk_set_rate,
|
||||||
#endif
|
#endif
|
||||||
|
.enable = dummy_enable,
|
||||||
};
|
};
|
||||||
|
|
||||||
static int zynq_clk_probe(struct udevice *dev)
|
static int zynq_clk_probe(struct udevice *dev)
|
||||||
|
|
|
@ -577,7 +577,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
|
||||||
debug("%s: CLK %ld\n", __func__, clock);
|
debug("%s: CLK %ld\n", __func__, clock);
|
||||||
|
|
||||||
ret = clk_enable(&clk);
|
ret = clk_enable(&clk);
|
||||||
if (ret && ret != -ENOSYS) {
|
if (ret) {
|
||||||
dev_err(dev, "failed to enable clock\n");
|
dev_err(dev, "failed to enable clock\n");
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
|
@ -477,13 +477,13 @@ static int zynq_gem_init(struct udevice *dev)
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = clk_set_rate(&priv->clk, clk_rate);
|
ret = clk_set_rate(&priv->clk, clk_rate);
|
||||||
if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
|
if (IS_ERR_VALUE(ret)) {
|
||||||
dev_err(dev, "failed to set tx clock rate\n");
|
dev_err(dev, "failed to set tx clock rate\n");
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = clk_enable(&priv->clk);
|
ret = clk_enable(&priv->clk);
|
||||||
if (ret && ret != -ENOSYS) {
|
if (ret) {
|
||||||
dev_err(dev, "failed to enable tx clock\n");
|
dev_err(dev, "failed to enable tx clock\n");
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
|
@ -127,7 +127,7 @@ static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
|
||||||
debug("%s: CLK %ld\n", __func__, clock);
|
debug("%s: CLK %ld\n", __func__, clock);
|
||||||
|
|
||||||
ret = clk_enable(&clk);
|
ret = clk_enable(&clk);
|
||||||
if (ret && ret != -ENOSYS) {
|
if (ret) {
|
||||||
dev_err(dev, "failed to enable clock\n");
|
dev_err(dev, "failed to enable clock\n");
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
|
@ -193,7 +193,7 @@ static int zynq_qspi_probe(struct udevice *bus)
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = clk_enable(&clk);
|
ret = clk_enable(&clk);
|
||||||
if (ret && ret != -ENOSYS) {
|
if (ret) {
|
||||||
dev_err(bus, "failed to enable clock\n");
|
dev_err(bus, "failed to enable clock\n");
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
|
@ -143,7 +143,7 @@ static int zynq_spi_probe(struct udevice *bus)
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = clk_enable(&clk);
|
ret = clk_enable(&clk);
|
||||||
if (ret && ret != -ENOSYS) {
|
if (ret) {
|
||||||
dev_err(bus, "failed to enable clock\n");
|
dev_err(bus, "failed to enable clock\n");
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
|
@ -373,7 +373,7 @@ static int zynqmp_qspi_probe(struct udevice *bus)
|
||||||
debug("%s: CLK %ld\n", __func__, clock);
|
debug("%s: CLK %ld\n", __func__, clock);
|
||||||
|
|
||||||
ret = clk_enable(&clk);
|
ret = clk_enable(&clk);
|
||||||
if (ret && ret != -ENOSYS) {
|
if (ret) {
|
||||||
dev_err(bus, "failed to enable clock\n");
|
dev_err(bus, "failed to enable clock\n");
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
|
@ -90,9 +90,8 @@ static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags)
|
||||||
/* Calculate timeout count */
|
/* Calculate timeout count */
|
||||||
count = timeout * clock_f;
|
count = timeout * clock_f;
|
||||||
|
|
||||||
/* clk_enable will return -ENOSYS when it is not implemented */
|
|
||||||
ret = clk_enable(&wdt->clk);
|
ret = clk_enable(&wdt->clk);
|
||||||
if (ret && ret != -ENOSYS) {
|
if (ret) {
|
||||||
dev_err(dev, "failed to enable clock\n");
|
dev_err(dev, "failed to enable clock\n");
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue