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arm: Remove s32v234evb board

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This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.

Cc: Eddy Petrișor <eddy.petrisor@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-02-20 20:05:49 -05:00
parent 56124508ce
commit 9ac8368071
25 changed files with 2 additions and 2707 deletions
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6
arch/arm/Kconfig
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@ -932,11 +932,6 @@ config ARCH_RMOBILE
imply SYS_THUMB_BUILD imply SYS_THUMB_BUILD
imply ARCH_MISC_INIT if DISPLAY_CPUINFO imply ARCH_MISC_INIT if DISPLAY_CPUINFO
config TARGET_S32V234EVB
bool "Support s32v234evb"
select ARM64
select SYS_FSL_ERRATUM_ESDHC111
config ARCH_SNAPDRAGON config ARCH_SNAPDRAGON
bool "Qualcomm Snapdragon SoCs" bool "Qualcomm Snapdragon SoCs"
select ARM64 select ARM64
@ -1979,7 +1974,6 @@ source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig" source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/lx2160a/Kconfig" source "board/freescale/lx2160a/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
source "board/grinn/chiliboard/Kconfig" source "board/grinn/chiliboard/Kconfig"
source "board/hisilicon/hikey/Kconfig" source "board/hisilicon/hikey/Kconfig"
source "board/hisilicon/hikey960/Kconfig" source "board/hisilicon/hikey960/Kconfig"

2
arch/arm/cpu/armv8/Kconfig
View File

@ -116,7 +116,7 @@ config PSCI_RESET
!TARGET_LS1046AFRWY && \ !TARGET_LS1046AFRWY && \
!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
!TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \ !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
!ARCH_UNIPHIER && !TARGET_S32V234EVB !ARCH_UNIPHIER
help help
Most armv8 systems have PSCI support enabled in EL3, either through Most armv8 systems have PSCI support enabled in EL3, either through
ARM Trusted Firmware or other firmware. ARM Trusted Firmware or other firmware.

6
arch/arm/cpu/armv8/s32v234/Makefile
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@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
obj-y += generic.o
obj-y += cpu.o

102
arch/arm/cpu/armv8/s32v234/cpu.c
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@ -1,102 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch/mc_me_regs.h>
#include <linux/bitops.h>
#include "cpu.h"
u32 cpu_mask(void)
{
return readl(MC_ME_CS);
}
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define S32V234_IRAM_BASE 0x3e800000UL
#define S32V234_IRAM_SIZE 0x800000UL
#define S32V234_DRAM_BASE1 0x80000000UL
#define S32V234_DRAM_SIZE1 0x40000000UL
#define S32V234_DRAM_BASE2 0xC0000000UL
#define S32V234_DRAM_SIZE2 0x20000000UL
#define S32V234_PERIPH_BASE 0x40000000UL
#define S32V234_PERIPH_SIZE 0x40000000UL
static struct mm_region s32v234_mem_map[] = {
{
.virt = S32V234_IRAM_BASE,
.phys = S32V234_IRAM_BASE,
.size = S32V234_IRAM_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
}, {
.virt = S32V234_DRAM_BASE1,
.phys = S32V234_DRAM_BASE1,
.size = S32V234_DRAM_SIZE1,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
}, {
.virt = S32V234_PERIPH_BASE,
.phys = S32V234_PERIPH_BASE,
.size = S32V234_PERIPH_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE
/* TODO: Do we need these? */
/* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */
}, {
.virt = S32V234_DRAM_BASE2,
.phys = S32V234_DRAM_BASE2,
.size = S32V234_DRAM_SIZE2,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_OUTER_SHARE
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = s32v234_mem_map;
#endif
/*
* Return the number of cores on this SOC.
*/
int cpu_numcores(void)
{
int numcores;
u32 mask;
mask = cpu_mask();
numcores = hweight32(cpu_mask());
/* Verify if M4 is deactivated */
if (mask & 0x1)
numcores--;
return numcores;
}
#if defined(CONFIG_ARCH_EARLY_INIT_R)
int arch_early_init_r(void)
{
int rv;
asm volatile ("dsb sy");
rv = fsl_s32v234_wake_seconday_cores();
if (rv)
printf("Did not wake secondary cores\n");
asm volatile ("sev");
return 0;
}
#endif /* CONFIG_ARCH_EARLY_INIT_R */

7
arch/arm/cpu/armv8/s32v234/cpu.h
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@ -1,7 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
*/
u32 cpu_mask(void);
int cpu_numcores(void);

354
arch/arm/cpu/armv8/s32v234/generic.c
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@ -1,354 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <clock_legacy.h>
#include <cpu_func.h>
#include <init.h>
#include <net.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/mc_cgm_regs.h>
#include <asm/arch/mc_me_regs.h>
#include <asm/arch/mc_rgm_regs.h>
#include <netdev.h>
#include <div64.h>
#include <errno.h>
u32 get_cpu_rev(void)
{
struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
u32 cpu = readl(&mscmir->cpxtype);
return cpu;
}
DECLARE_GLOBAL_DATA_PTR;
static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv,
u32 pllfd, u32 selected_output)
{
u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0;
u32 plldv_rfdphi_div = 0, fout = 0;
u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0;
if (selected_output > DFS_MAXNUMBER) {
return -1;
}
plldv_prediv =
(plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET;
plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK);
pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK);
plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv;
/* The formula for VCO is from TR manual, rev. D */
vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481);
if (selected_output != 0) {
/* Determine the RFDPHI for PHI1 */
plldv_rfdphi_div =
(plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >>
PLLDIG_PLLDV_RFDPHI1_OFFSET;
plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div;
if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) {
dfs_portn =
readl(DFS_DVPORTn(pll, selected_output - 1));
dfs_mfi =
(dfs_portn & DFS_DVPORTn_MFI_MASK) >>
DFS_DVPORTn_MFI_OFFSET;
dfs_mfn =
(dfs_portn & DFS_DVPORTn_MFI_MASK) >>
DFS_DVPORTn_MFI_OFFSET;
fout = vco / (dfs_mfi + (dfs_mfn / 256));
} else {
fout = vco / plldv_rfdphi_div;
}
} else {
/* Determine the RFDPHI for PHI0 */
plldv_rfdphi_div =
(plldv & PLLDIG_PLLDV_RFDPHI_MASK) >>
PLLDIG_PLLDV_RFDPHI_OFFSET;
fout = vco / plldv_rfdphi_div;
}
return fout;
}
/* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */
static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq,
u32 selected_output)
{
u32 plldv, pllfd;
plldv = readl(PLLDIG_PLLDV(pll));
pllfd = readl(PLLDIG_PLLFD(pll));
return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output);
}
static u32 get_mcu_main_clk(void)
{
u32 coreclk_div;
u32 sysclk_sel;
u32 freq = 0;
sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
coreclk_div =
readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK;
coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
coreclk_div += 1;
switch (sysclk_sel) {
case MC_CGM_SC_SEL_FIRC:
freq = FIRC_CLK_FREQ;
break;
case MC_CGM_SC_SEL_XOSC:
freq = XOSC_CLK_FREQ;
break;
case MC_CGM_SC_SEL_ARMPLL:
/* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */
freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0);
break;
case MC_CGM_SC_SEL_CLKDISABLE:
printf("Sysclk is disabled\n");
break;
default:
printf("unsupported system clock select\n");
}
return freq / coreclk_div;
}
static u32 get_sys_clk(u32 number)
{
u32 sysclk_div, sysclk_div_number;
u32 sysclk_sel;
u32 freq = 0;
switch (number) {
case 3:
sysclk_div_number = 0;
break;
case 6:
sysclk_div_number = 1;
break;
default:
printf("unsupported system clock \n");
return -1;
}
sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
sysclk_div =
readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) &
MC_CGM_SC_DCn_PREDIV_MASK;
sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
sysclk_div += 1;
switch (sysclk_sel) {
case MC_CGM_SC_SEL_FIRC:
freq = FIRC_CLK_FREQ;
break;
case MC_CGM_SC_SEL_XOSC:
freq = XOSC_CLK_FREQ;
break;
case MC_CGM_SC_SEL_ARMPLL:
/* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */
freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1);
break;
case MC_CGM_SC_SEL_CLKDISABLE:
printf("Sysclk is disabled\n");
break;
default:
printf("unsupported system clock select\n");
}
return freq / sysclk_div;
}
static u32 get_peripherals_clk(void)
{
u32 aux5clk_div;
u32 freq = 0;
aux5clk_div =
readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) &
MC_CGM_ACn_DCm_PREDIV_MASK;
aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
aux5clk_div += 1;
freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0);
return freq / aux5clk_div;
}
static u32 get_uart_clk(void)
{
u32 auxclk3_div, auxclk3_sel, freq = 0;
auxclk3_sel =
readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK;
auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET;
auxclk3_div =
readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) &
MC_CGM_ACn_DCm_PREDIV_MASK;
auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
auxclk3_div += 1;
switch (auxclk3_sel) {
case MC_CGM_ACn_SEL_FIRC:
freq = FIRC_CLK_FREQ;
break;
case MC_CGM_ACn_SEL_XOSC:
freq = XOSC_CLK_FREQ;
break;
case MC_CGM_ACn_SEL_PERPLLDIVX:
freq = get_peripherals_clk() / 3;
break;
case MC_CGM_ACn_SEL_SYSCLK:
freq = get_sys_clk(6);
break;
default:
printf("unsupported system clock select\n");
}
return freq / auxclk3_div;
}
static u32 get_fec_clk(void)
{
u32 aux2clk_div;
u32 freq = 0;
aux2clk_div =
readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) &
MC_CGM_ACn_DCm_PREDIV_MASK;
aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
aux2clk_div += 1;
freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0);
return freq / aux2clk_div;
}
static u32 get_usdhc_clk(void)
{
u32 aux15clk_div;
u32 freq = 0;
aux15clk_div =
readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) &
MC_CGM_ACn_DCm_PREDIV_MASK;
aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
aux15clk_div += 1;
freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4);
return freq / aux15clk_div;
}
static u32 get_i2c_clk(void)
{
return get_peripherals_clk();
}
/* return clocks in Hz */
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
case MXC_ARM_CLK:
return get_mcu_main_clk();
case MXC_PERIPHERALS_CLK:
return get_peripherals_clk();
case MXC_UART_CLK:
return get_uart_clk();
case MXC_FEC_CLK:
return get_fec_clk();
case MXC_I2C_CLK:
return get_i2c_clk();
case MXC_USDHC_CLK:
return get_usdhc_clk();
default:
break;
}
printf("Error: Unsupported function to read the frequency! \
Please define it correctly!");
return -1;
}
/* Not yet implemented - int soc_clk_dump(); */
#if defined(CONFIG_DISPLAY_CPUINFO)
static char *get_reset_cause(void)
{
u32 cause = readl(MC_RGM_BASE_ADDR + 0x300);
switch (cause) {
case F_SWT4:
return "WDOG";
case F_JTAG:
return "JTAG";
case F_FCCU_SOFT:
return "FCCU soft reaction";
case F_FCCU_HARD:
return "FCCU hard reaction";
case F_SOFT_FUNC:
return "Software Functional reset";
case F_ST_DONE:
return "Self Test done reset";
case F_EXT_RST:
return "External reset";
default:
return "unknown reset";
}
}
#define SRC_SCR_SW_RST (1<<12)
void reset_cpu(void)
{
printf("Feature not supported.\n");
};
int print_cpuinfo(void)
{
printf("CPU: Freescale Treerunner S32V234 at %d MHz\n",
mxc_get_clock(MXC_ARM_CLK) / 1000000);
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
#endif
int cpu_eth_init(struct bd_info * bis)
{
int rc = -ENODEV;
#if defined(CONFIG_FEC_MXC)
rc = fecmxc_initialize(bis);
#endif
return rc;
}
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
#endif
return 0;
}

31
arch/arm/include/asm/arch-s32v234/clock.h
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@ -1,31 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
enum mxc_clock {
MXC_ARM_CLK = 0,
MXC_BUS_CLK,
MXC_PERIPHERALS_CLK,
MXC_UART_CLK,
MXC_USDHC_CLK,
MXC_FEC_CLK,
MXC_I2C_CLK,
};
enum pll_type {
ARM_PLL = 0,
PERIPH_PLL,
ENET_PLL,
DDR_PLL,
VIDEO_PLL,
};
unsigned int mxc_get_clock(enum mxc_clock clk);
void clock_init(void);
#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
#endif /* __ASM_ARCH_CLOCK_H */

156
arch/arm/include/asm/arch-s32v234/ddr.h
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@ -1,156 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
*/
#ifndef __ARCH_ARM_MACH_S32V234_DDR_H__
#define __ARCH_ARM_MACH_S32V234_DDR_H__
#define DDR0 0
#define DDR1 1
/* DDR offset in MSCR register */
#define _DDR0_RESET 168
#define _DDR0_CLK0 169
#define _DDR0_CAS 170
#define _DDR0_RAS 171
#define _DDR0_WE_B 172
#define _DDR0_CKE0 173
#define _DDR0_CKE1 174
#define _DDR0_CS_B0 175
#define _DDR0_CS_B1 176
#define _DDR0_BA0 177
#define _DDR0_BA1 178
#define _DDR0_BA2 179
#define _DDR0_A0 180
#define _DDR0_A1 181
#define _DDR0_A2 182
#define _DDR0_A3 183
#define _DDR0_A4 184
#define _DDR0_A5 185
#define _DDR0_A6 186
#define _DDR0_A7 187
#define _DDR0_A8 188
#define _DDR0_A9 189
#define _DDR0_A10 190
#define _DDR0_A11 191
#define _DDR0_A12 192
#define _DDR0_A13 193
#define _DDR0_A14 194
#define _DDR0_A15 195
#define _DDR0_DM0 196
#define _DDR0_DM1 197
#define _DDR0_DM2 198
#define _DDR0_DM3 199
#define _DDR0_DQS0 200
#define _DDR0_DQS1 201
#define _DDR0_DQS2 202
#define _DDR0_DQS3 203
#define _DDR0_D0 204
#define _DDR0_D1 205
#define _DDR0_D2 206
#define _DDR0_D3 207
#define _DDR0_D4 208
#define _DDR0_D5 209
#define _DDR0_D6 210
#define _DDR0_D7 211
#define _DDR0_D8 212
#define _DDR0_D9 213
#define _DDR0_D10 214
#define _DDR0_D11 215
#define _DDR0_D12 216
#define _DDR0_D13 217
#define _DDR0_D14 218
#define _DDR0_D15 219
#define _DDR0_D16 220
#define _DDR0_D17 221
#define _DDR0_D18 222
#define _DDR0_D19 223
#define _DDR0_D20 224
#define _DDR0_D21 225
#define _DDR0_D22 226
#define _DDR0_D23 227
#define _DDR0_D24 228
#define _DDR0_D25 229
#define _DDR0_D26 230
#define _DDR0_D27 231
#define _DDR0_D28 232
#define _DDR0_D29 233
#define _DDR0_D30 234
#define _DDR0_D31 235
#define _DDR0_ODT0 236
#define _DDR0_ODT1 237
#define _DDR0_ZQ 238
#define _DDR1_RESET 239
#define _DDR1_CLK0 240
#define _DDR1_CAS 241
#define _DDR1_RAS 242
#define _DDR1_WE_B 243
#define _DDR1_CKE0 244
#define _DDR1_CKE1 245
#define _DDR1_CS_B0 246
#define _DDR1_CS_B1 247
#define _DDR1_BA0 248
#define _DDR1_BA1 249
#define _DDR1_BA2 250
#define _DDR1_A0 251
#define _DDR1_A1 252
#define _DDR1_A2 253
#define _DDR1_A3 254
#define _DDR1_A4 255
#define _DDR1_A5 256
#define _DDR1_A6 257
#define _DDR1_A7 258
#define _DDR1_A8 259
#define _DDR1_A9 260
#define _DDR1_A10 261
#define _DDR1_A11 262
#define _DDR1_A12 263
#define _DDR1_A13 264
#define _DDR1_A14 265
#define _DDR1_A15 266
#define _DDR1_DM0 267
#define _DDR1_DM1 268
#define _DDR1_DM2 269
#define _DDR1_DM3 270
#define _DDR1_DQS0 271
#define _DDR1_DQS1 272
#define _DDR1_DQS2 273
#define _DDR1_DQS3 274
#define _DDR1_D0 275
#define _DDR1_D1 276
#define _DDR1_D2 277
#define _DDR1_D3 278
#define _DDR1_D4 279
#define _DDR1_D5 280
#define _DDR1_D6 281
#define _DDR1_D7 282
#define _DDR1_D8 283
#define _DDR1_D9 284
#define _DDR1_D10 285
#define _DDR1_D11 286
#define _DDR1_D12 287
#define _DDR1_D13 288
#define _DDR1_D14 289
#define _DDR1_D15 290
#define _DDR1_D16 291
#define _DDR1_D17 292
#define _DDR1_D18 293
#define _DDR1_D19 294
#define _DDR1_D20 295
#define _DDR1_D21 296
#define _DDR1_D22 297
#define _DDR1_D23 298
#define _DDR1_D24 299
#define _DDR1_D25 300
#define _DDR1_D26 301
#define _DDR1_D27 302
#define _DDR1_D28 303
#define _DDR1_D29 304
#define _DDR1_D30 305
#define _DDR1_D31 306
#define _DDR1_ODT0 307
#define _DDR1_ODT1 308
#define _DDR1_ZQ 309
#endif

328
arch/arm/include/asm/arch-s32v234/imx-regs.h
View File

@ -1,328 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
*/
#ifndef __ASM_ARCH_IMX_REGS_H__
#define __ASM_ARCH_IMX_REGS_H__
#define ARCH_MXC
#define IRAM_BASE_ADDR 0x3E800000 /* internal ram */
#define IRAM_SIZE 0x00400000 /* 4MB */
#define AIPS0_BASE_ADDR (0x40000000UL)
#define AIPS1_BASE_ADDR (0x40080000UL)
/* AIPS 0 */
#define AXBS_BASE_ADDR (AIPS0_BASE_ADDR + 0x00000000)
#define CSE3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
#define EDMA_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
#define XRDC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00004000)
#define SWT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
#define SWT1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
#define STM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000)
#define NIC301_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000)
#define GC3000_BASE_ADDR (AIPS0_BASE_ADDR + 0x00020000)
#define DEC200_DECODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00026000)
#define DEC200_ENCODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00027000)
#define TWOD_ACE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00028000)
#define MIPI_CSI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000)
#define DMAMUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
#define ENET_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
#define FLEXRAY_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000)
#define MMDC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
#define MEW0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
#define MONITOR_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
#define MONITOR_CCI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000)
#define PIT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003A000)
#define MC_CGM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003C000)
#define MC_CGM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003F000)
#define MC_CGM2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000)
#define MC_CGM3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00045000)
#define MC_RGM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
#define MC_ME_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004A000)
#define MC_PCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004B000)
#define ADC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004D000)
#define FLEXTIMER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004F000)
#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00051000)
#define LINFLEXD0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00053000)
#define FLEXCAN0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00055000)
#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00057000)
#define SPI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00059000)
#define CRC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005B000)
#define USDHC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005D000)
#define OCOTP_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005F000)
#define WKPU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
#define VIU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00064000)
#define HPSMI_SRAM_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00068000)
#define SIUL2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
#define SIPI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00074000)
#define LFAST_BASE_ADDR (AIPS0_BASE_ADDR + 0x00078000)
#define SSE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00079000)
#define SRC_SOC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0007C000)
/* AIPS 1 */
#define ERM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000000000)
#define MSCM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000001000)
#define SEMA42_BASE_ADDR (AIPS1_BASE_ADDR + 0X000002000)
#define INTC_MON_BASE_ADDR (AIPS1_BASE_ADDR + 0X000003000)
#define SWT2_BASE_ADDR (AIPS1_BASE_ADDR + 0X000004000)
#define SWT3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000005000)
#define SWT4_BASE_ADDR (AIPS1_BASE_ADDR + 0X000006000)
#define STM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000007000)
#define EIM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000008000)
#define APB_BASE_ADDR (AIPS1_BASE_ADDR + 0X000009000)
#define XBIC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000012000)
#define MIPI_BASE_ADDR (AIPS1_BASE_ADDR + 0X000020000)
#define DMAMUX1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000021000)
#define MMDC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000022000)
#define MEW1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000023000)
#define DDR1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000024000)
#define CCI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000025000)
#define QUADSPI0_BASE_ADDR (AIPS1_BASE_ADDR + 0X000026000)
#define PIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00002A000)
#define FCCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000030000)
#define FLEXTIMER_FTM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000036000)
#define I2C1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000038000)
#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003A000)
#define LINFLEXD1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003C000)
#define FLEXCAN1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003E000)
#define SPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000040000)
#define SPI3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000042000)
#define IPL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000043000)
#define CGM_CMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000044000)
#define PMC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000048000)
#define CRC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004C000)
#define TMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004E000)
#define VIU1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000050000)
#define JPEG_BASE_ADDR (AIPS1_BASE_ADDR + 0X000054000)
#define H264_DEC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000058000)
#define H264_ENC_BASE_ADDR (AIPS1_BASE_ADDR + 0X00005C000)
#define MEMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000060000)
#define STCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000064000)
#define SLFTST_CTRL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000066000)
#define MCT_BASE_ADDR (AIPS1_BASE_ADDR + 0X000068000)
#define REP_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006A000)
#define MBIST_CONTROLLER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006C000)
#define BOOT_LOADER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006F000)
/* TODO Remove this after the IOMUX framework is implemented */
#define IOMUXC_BASE_ADDR SIUL2_BASE_ADDR
/* MUX mode and PAD ctrl are in one register */
#define CONFIG_IOMUX_SHARE_CONF_REG
#define FEC_QUIRK_ENET_MAC
#define I2C_QUIRK_REG
/* MSCM interrupt router */
#define MSCM_IRSPRC_CPn_EN 3
#define MSCM_IRSPRC_NUM 176
#define MSCM_CPXTYPE_RYPZ_MASK 0xFF
#define MSCM_CPXTYPE_RYPZ_OFFSET 0
#define MSCM_CPXTYPE_PERS_MASK 0xFFFFFF00
#define MSCM_CPXTYPE_PERS_OFFSET 8
#define MSCM_CPXTYPE_PERS_A53 0x413533
#define MSCM_CPXTYPE_PERS_CM4 0x434d34
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
/* System Reset Controller (SRC) */
struct src {
u32 bmr1;
u32 bmr2;
u32 gpr1_boot;
u32 reserved_0x00C[61];
u32 gpr1;
u32 gpr2;
u32 gpr3;
u32 gpr4;
u32 gpr5;
u32 gpr6;
u32 gpr7;
u32 reserved_0x11C[1];
u32 gpr9;
u32 gpr10;
u32 gpr11;
u32 gpr12;
u32 gpr13;
u32 gpr14;
u32 gpr15;
u32 gpr16;
u32 reserved_0x140[1];
u32 gpr17;
u32 gpr18;
u32 gpr19;
u32 gpr20;
u32 gpr21;
u32 gpr22;
u32 gpr23;
u32 gpr24;
u32 gpr25;
u32 gpr26;
u32 gpr27;
u32 reserved_0x16C[5];
u32 pcie_config1;
u32 ddr_self_ref_ctrl;
u32 pcie_config0;
u32 reserved_0x18C[4];
u32 soc_misc_config2;
};
/* SRC registers definitions */
/* SRC_GPR1 */
#define SRC_GPR1_PLL_SOURCE(pll,val)( ((val) & SRC_GPR1_PLL_SOURCE_MASK) << \
(SRC_GPR1_PLL_OFFSET + (pll)) )
#define SRC_GPR1_PLL_SOURCE_MASK (0x1)
#define SRC_GPR1_PLL_OFFSET (27)
#define SRC_GPR1_FIRC_CLK_SOURCE (0x0)
#define SRC_GPR1_XOSC_CLK_SOURCE (0x1)
/* Periodic Interrupt Timer (PIT) */
struct pit_reg {
u32 mcr;
u32 recv0[55];
u32 ltmr64h;
u32 ltmr64l;
u32 recv1[6];
u32 ldval0;
u32 cval0;
u32 tctrl0;
u32 tflg0;
u32 ldval1;
u32 cval1;
u32 tctrl1;
u32 tflg1;
u32 ldval2;
u32 cval2;
u32 tctrl2;
u32 tflg2;
u32 ldval3;
u32 cval3;
u32 tctrl3;
u32 tflg3;
u32 ldval4;
u32 cval4;
u32 tctrl4;
u32 tflg4;
u32 ldval5;
u32 cval5;
u32 tctrl5;
u32 tflg5;
};
/* Watchdog Timer (WDOG) */
struct wdog_regs {
u32 cr;
u32 ir;
u32 to;
u32 wn;
u32 sr;
u32 co;
u32 sk;
};
/* UART */
struct linflex_fsl {
u32 lincr1;
u32 linier;
u32 linsr;
u32 linesr;
u32 uartcr;
u32 uartsr;
u32 lintcsr;
u32 linocr;
u32 lintocr;
u32 linfbrr;
u32 linibrr;
u32 lincfr;
u32 lincr2;
u32 bidr;
u32 bdrl;
u32 bdrm;
u32 ifer;
u32 ifmi;
u32 ifmr;
u32 ifcr0;
u32 ifcr1;
u32 ifcr2;
u32 ifcr3;
u32 ifcr4;
u32 ifcr5;
u32 ifcr6;
u32 ifcr7;
u32 ifcr8;
u32 ifcr9;
u32 ifcr10;
u32 ifcr11;
u32 ifcr12;
u32 ifcr13;
u32 ifcr14;
u32 ifcr15;
u32 gcr;
u32 uartpto;
u32 uartcto;
u32 dmatxe;
u32 dmarxe;
};
/* MSCM Interrupt Router */
struct mscm_ir {
u32 cpxtype; /* Processor x Type Register */
u32 cpxnum; /* Processor x Number Register */
u32 cpxmaster; /* Processor x Master Number Register */
u32 cpxcount; /* Processor x Count Register */
u32 cpxcfg0; /* Processor x Configuration 0 Register */
u32 cpxcfg1; /* Processor x Configuration 1 Register */
u32 cpxcfg2; /* Processor x Configuration 2 Register */
u32 cpxcfg3; /* Processor x Configuration 3 Register */
u32 cp0type; /* Processor 0 Type Register */
u32 cp0num; /* Processor 0 Number Register */
u32 cp0master; /* Processor 0 Master Number Register */
u32 cp0count; /* Processor 0 Count Register */
u32 cp0cfg0; /* Processor 0 Configuration 0 Register */
u32 cp0cfg1; /* Processor 0 Configuration 1 Register */
u32 cp0cfg2; /* Processor 0 Configuration 2 Register */
u32 cp0cfg3; /* Processor 0 Configuration 3 Register */
u32 cp1type; /* Processor 1 Type Register */
u32 cp1num; /* Processor 1 Number Register */
u32 cp1master; /* Processor 1 Master Number Register */
u32 cp1count; /* Processor 1 Count Register */
u32 cp1cfg0; /* Processor 1 Configuration 0 Register */
u32 cp1cfg1; /* Processor 1 Configuration 1 Register */
u32 cp1cfg2; /* Processor 1 Configuration 2 Register */
u32 cp1cfg3; /* Processor 1 Configuration 3 Register */
u32 reserved_0x060[232];
u32 ocmdr0; /* On-Chip Memory Descriptor Register */
u32 reserved_0x404[2];
u32 ocmdr3; /* On-Chip Memory Descriptor Register */
u32 reserved_0x410[28];
u32 tcmdr[4]; /* Generic Tightly Coupled Memory Descriptor Register */
u32 reserved_0x490[28];
u32 cpce0; /* Core Parity Checking Enable Register 0 */
u32 reserved_0x504[191];
u32 ircp0ir; /* Interrupt Router CP0 Interrupt Register */
u32 ircp1ir; /* Interrupt Router CP1 Interrupt Register */
u32 reserved_0x808[6];
u32 ircpgir; /* Interrupt Router CPU Generate Interrupt Register */
u32 reserved_0x824[23];
u16 irsprc[176]; /* Interrupt Router Shared Peripheral Routing Control Register */
u32 reserved_0x9e0[136];
u32 iahbbe0; /* Gasket Burst Enable Register */
u32 reserved_0xc04[63];
u32 ipcge; /* Interconnect Parity Checking Global Enable Register */
u32 reserved_0xd04[3];
u32 ipce[4]; /* Interconnect Parity Checking Enable Register */
u32 reserved_0xd20[8];
u32 ipcgie; /* Interconnect Parity Checking Global Injection Enable Register */
u32 reserved_0xd44[3];
u32 ipcie[4]; /* Interconnect Parity Checking Injection Enable Register */
};
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_IMX_REGS_H__ */

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arch/arm/include/asm/arch-s32v234/lpddr2.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
*/
#ifndef __ARCH_ARM_MACH_S32V234_LPDDR2_H__
#define __ARCH_ARM_MACH_S32V234_LPDDR2_H__
/* definitions for LPDDR2 PAD values */
#define LPDDR2_CLK0_PAD \
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_CRPOINT_TRIM_1 | \
SIUL2_MSCR_DCYCLE_TRIM_NONE)
#define LPDDR2_CKEn_PAD \
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
#define LPDDR2_CS_Bn_PAD \
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
#define LPDDR2_DMn_PAD \
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
#define LPDDR2_DQSn_PAD \
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \
SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUE_EN | SIUL2_MSCR_PUS_100K_DOWN | \
SIUL2_MSCR_PKE_EN | SIUL2_MSCR_CRPOINT_TRIM_1 | SIUL2_MSCR_DCYCLE_TRIM_NONE)
#define LPDDR2_An_PAD \
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \
SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT | \
SIUL2_MSCR_PUS_100K_UP)
#define LPDDR2_Dn_PAD \
(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \
SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT | \
SIUL2_MSCR_PUS_100K_UP)
#define _MDCTL 0x03010000
#define MMDC_MDSCR_CFG_VALUE 0x00008000 /* Set MDSCR[CON_REQ] (configuration request) */
#define MMDC_MDCFG0_VALUE 0x464F61A5 /* tRFCab=70 (=130ns),tXSR=80 (=tRFCab+10ns),tXP=4 (=7.5ns),tXPDLL=n/a,tFAW=27 (50 ns),tCL(RL)=8 */
#define MMDC_MDCFG1_VALUE 0x00180E63 /* tRCD=n/a,tRPpb=n/a,tRC=n/a ,tRAS=25 (=47ns),tRPA=n/a,tWR=8 (=15.0ns),tMRD=3,tWL=4 */
#define MMDC_MDCFG2_VALUE 0x000000DD /* tDLLK=n/a,tRTP=4 (=7.5ns),tWTR=4 (=7.5ns),tRRD=6 (=10ns) */
#define MMDC_MDCFG3LP_VALUE 0x001F099B /* RC_LP=tRAS+tRPab=32 (>60ns), tRCD_LP=10 (18ns) , tRPpb_LP=10 (18ns), tRPab_LP=12 (21ns) */
#define MMDC_MDOTC_VALUE 0x00000000 /* tAOFPD=n/a,tAONPD=n/a,tANPD=n/a,tAXPD=n/a,tODTLon=n/a,tODT_idle_off=n/a */
#define MMDC_MDMISC_VALUE 0x00001688 /* WALAT=0, BI bank interleave on, LPDDR2_S2=0, MIF3=3, RALAT=2, 8 banks, LPDDR2 */
#define MMDC_MDOR_VALUE 0x00000010 /* tXPR=n/a , SDE_to_RST=n/a, RST_to_CKE=14 */
#define MMDC_MPMUR0_VALUE 0x00000800 /* Force delay line initialisation */
#define MMDC_MDSCR_RST_VALUE 0x003F8030 /* Reset command CS0 */
#define MMDC_MPZQLP2CTL_VALUE 0x1B5F0109 /* ZQ_LP2_HW_ZQCS=0x1B (90ns spec), ZQ_LP2_HW_ZQCL=0x5F (160ns spec), ZQ_LP2_HW_ZQINIT=0x109 (1us spec) */
#define MMDC_MPZQHWCTRL_VALUE 0xA0010003 /* ZQ_EARLY_COMPARATOR_EN_TIMER=0x14, TZQ_CS=n/a, TZQ_OPER=n/a, TZQ_INIT=n/a, ZQ_HW_FOR=1, ZQ_HW_PER=0, ZQ_MODE=3 */
#define MMDC_MDSCR_MR1_VALUE 0xC2018030 /* Configure MR1: BL 4, burst type interleaved, wrap control no wrap, tWR cycles 8 */
#define MMDC_MDSCR_MR2_VALUE 0x06028030 /* Configure MR2: RL=8, WL=4 */
#define MMDC_MDSCR_MR3_VALUE 0x01038030 /* Configure MR3: DS=34R */
#define MMDC_MDSCR_MR10_VALUE 0xFF0A8030 /* Configure MR10: Calibration at init */
#define MMDC_MDASP_MODULE0_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0x90000000) */
#define MMDC_MPRDDLCTL_MODULE0_VALUE 0x4D4B4F4B /* Read delay line offsets */
#define MMDC_MPWRDLCTL_MODULE0_VALUE 0x38383737 /* Write delay line offsets */
#define MMDC_MPDGCTRL0_MODULE0_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */
#define MMDC_MPDGCTRL1_MODULE0_VALUE 0x00000000 /* Read DQS gating control 1 */
#define MMDC_MDASP_MODULE1_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0xD0000000) */
#define MMDC_MPRDDLCTL_MODULE1_VALUE 0x4D4B4F4B /* Read delay line offsets */
#define MMDC_MPWRDLCTL_MODULE1_VALUE 0x38383737 /* Write delay line offsets */
#define MMDC_MPDGCTRL0_MODULE1_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */
#define MMDC_MPDGCTRL1_MODULE1_VALUE 0x00000000 /* Read DQS gating control 1 */
#define MMDC_MDRWD_VALUE 0x0F9F26D2 /* Read/write command delay - default used */
#define MMDC_MDPDC_VALUE 0x00020024 /* Power down control */
#define MMDC_MDREF_VALUE 0x30B01800 /* Refresh control */
#define MMDC_MPODTCTRL_VALUE 0x00000000 /* No ODT */
#define MMDC_MDSCR_DEASSERT_VALUE 0x00000000 /* Deassert the configuration request */
/* set I/O pads for DDR */
void lpddr2_config_iomux(uint8_t module);
void config_mmdc(uint8_t module);
#endif

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arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015, Freescale Semiconductor, Inc.
*/
#ifndef __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
#define __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
#ifndef __ASSEMBLY__
/* MC_CGM registers definitions */
/* MC_CGM_SC_SS */
#define CGM_SC_SS(cgm_addr) ( ((cgm_addr) + 0x000007E4) )
#define MC_CGM_SC_SEL_FIRC (0x0)
#define MC_CGM_SC_SEL_XOSC (0x1)
#define MC_CGM_SC_SEL_ARMPLL (0x2)
#define MC_CGM_SC_SEL_CLKDISABLE (0xF)
/* MC_CGM_SC_DCn */
#define CGM_SC_DCn(cgm_addr,dc) ( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) )
#define MC_CGM_SC_DCn_PREDIV(val) (MC_CGM_SC_DCn_PREDIV_MASK & ((val) << MC_CGM_SC_DCn_PREDIV_OFFSET))
#define MC_CGM_SC_DCn_PREDIV_MASK (0x00070000)
#define MC_CGM_SC_DCn_PREDIV_OFFSET (16)
#define MC_CGM_SC_DCn_DE (1 << 31)
#define MC_CGM_SC_SEL_MASK (0x0F000000)
#define MC_CGM_SC_SEL_OFFSET (24)
/* MC_CGM_ACn_DCm */
#define CGM_ACn_DCm(cgm_addr,ac,dc) ( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) )
#define MC_CGM_ACn_DCm_PREDIV(val) (MC_CGM_ACn_DCm_PREDIV_MASK & ((val) << MC_CGM_ACn_DCm_PREDIV_OFFSET))
/*
* MC_CGM_ACn_DCm_PREDIV_MASK is on 5 bits because practical test has shown
* that the 5th bit is always ignored during writes if the current
* MC_CGM_ACn_DCm_PREDIV field has only 4 bits
*
* The manual states only selectors 1, 5 and 15 have DC0_PREDIV on 5 bits
*
* This should be changed if any problems occur.
*/
#define MC_CGM_ACn_DCm_PREDIV_MASK (0x001F0000)
#define MC_CGM_ACn_DCm_PREDIV_OFFSET (16)
#define MC_CGM_ACn_DCm_DE (1 << 31)
/*
* MC_CGM_ACn_SC/MC_CGM_ACn_SS
*/
#define CGM_ACn_SC(cgm_addr,ac) ((cgm_addr + 0x00000800) + ((ac) * 0x20))
#define CGM_ACn_SS(cgm_addr,ac) ((cgm_addr + 0x00000804) + ((ac) * 0x20))
#define MC_CGM_ACn_SEL_MASK (0x07000000)
#define MC_CGM_ACn_SEL_SET(source) (MC_CGM_ACn_SEL_MASK & (((source) & 0x7) << MC_CGM_ACn_SEL_OFFSET))
#define MC_CGM_ACn_SEL_OFFSET (24)
#define MC_CGM_ACn_SEL_FIRC (0x0)
#define MC_CGM_ACn_SEL_XOSC (0x1)
#define MC_CGM_ACn_SEL_ARMPLL (0x2)
/*
* According to the manual some PLL can be divided by X (X={1,3,5}):
* PERPLLDIVX, VIDEOPLLDIVX.
*/
#define MC_CGM_ACn_SEL_PERPLLDIVX (0x3)
#define MC_CGM_ACn_SEL_ENETPLL (0x4)
#define MC_CGM_ACn_SEL_DDRPLL (0x5)
#define MC_CGM_ACn_SEL_EXTSRCPAD (0x7)
#define MC_CGM_ACn_SEL_SYSCLK (0x8)
#define MC_CGM_ACn_SEL_VIDEOPLLDIVX (0x9)
#define MC_CGM_ACn_SEL_PERCLK (0xA)
/* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */
#define PLLDIG_PLLDV(pll) ((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80))
#define PLLDIG_PLLDV_MFD(div) (PLLDIG_PLLDV_MFD_MASK & (div))
#define PLLDIG_PLLDV_MFD_MASK (0x000000FF)
/*
* PLLDIG_PLLDV_RFDPHIB has a different format for /32 according to
* the reference manual. This other value respect the formula 2^[RFDPHIBY+1]
*/
#define PLLDIG_PLLDV_RFDPHI_SET(val) (PLLDIG_PLLDV_RFDPHI_MASK & (((val) & PLLDIG_PLLDV_RFDPHI_MAXVALUE) << PLLDIG_PLLDV_RFDPHI_OFFSET))
#define PLLDIG_PLLDV_RFDPHI_MASK (0x003F0000)
#define PLLDIG_PLLDV_RFDPHI_MAXVALUE (0x3F)
#define PLLDIG_PLLDV_RFDPHI_OFFSET (16)
#define PLLDIG_PLLDV_RFDPHI1_SET(val) (PLLDIG_PLLDV_RFDPHI1_MASK & (((val) & PLLDIG_PLLDV_RFDPHI1_MAXVALUE) << PLLDIG_PLLDV_RFDPHI1_OFFSET))
#define PLLDIG_PLLDV_RFDPHI1_MASK (0x7E000000)
#define PLLDIG_PLLDV_RFDPHI1_MAXVALUE (0x3F)
#define PLLDIG_PLLDV_RFDPHI1_OFFSET (25)
#define PLLDIG_PLLDV_PREDIV_SET(val) (PLLDIG_PLLDV_PREDIV_MASK & (((val) & PLLDIG_PLLDV_PREDIV_MAXVALUE) << PLLDIG_PLLDV_PREDIV_OFFSET))
#define PLLDIG_PLLDV_PREDIV_MASK (0x00007000)
#define PLLDIG_PLLDV_PREDIV_MAXVALUE (0x7)
#define PLLDIG_PLLDV_PREDIV_OFFSET (12)
/* PLLDIG PLL Fractional Divide Register (PLLDIG_PLLFD) */
#define PLLDIG_PLLFD(pll) ((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80))
#define PLLDIG_PLLFD_MFN_SET(val) (PLLDIG_PLLFD_MFN_MASK & (val))
#define PLLDIG_PLLFD_MFN_MASK (0x00007FFF)
#define PLLDIG_PLLFD_SMDEN (1 << 30)
/* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */
#define PLLDIG_PLLCAL1(pll) ((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80))
#define PLLDIG_PLLCAL1_NDAC1_SET(val) (PLLDIG_PLLCAL1_NDAC1_MASK & ((val) << PLLDIG_PLLCAL1_NDAC1_OFFSET))
#define PLLDIG_PLLCAL1_NDAC1_OFFSET (24)
#define PLLDIG_PLLCAL1_NDAC1_MASK (0x7F000000)
/* Digital Frequency Synthesizer (DFS) */
/* According to the manual there are 3 DFS modules only for ARM_PLL, DDR_PLL, ENET_PLL */
#define DFS0_BASE_ADDR (MC_CGM0_BASE_ADDR + 0x00000040)
/* DFS DLL Program Register 1 */
#define DFS_DLLPRG1(pll) (DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80))
#define DFS_DLLPRG1_V2IGC_SET(val) (DFS_DLLPRG1_V2IGC_MASK & ((val) << DFS_DLLPRG1_V2IGC_OFFSET))
#define DFS_DLLPRG1_V2IGC_OFFSET (0)
#define DFS_DLLPRG1_V2IGC_MASK (0x00000007)
#define DFS_DLLPRG1_LCKWT_SET(val) (DFS_DLLPRG1_LCKWT_MASK & ((val) << DFS_DLLPRG1_LCKWT_OFFSET))
#define DFS_DLLPRG1_LCKWT_OFFSET (4)
#define DFS_DLLPRG1_LCKWT_MASK (0x00000030)
#define DFS_DLLPRG1_DACIN_SET(val) (DFS_DLLPRG1_DACIN_MASK & ((val) << DFS_DLLPRG1_DACIN_OFFSET))
#define DFS_DLLPRG1_DACIN_OFFSET (6)
#define DFS_DLLPRG1_DACIN_MASK (0x000001C0)
#define DFS_DLLPRG1_CALBYPEN_SET(val) (DFS_DLLPRG1_CALBYPEN_MASK & ((val) << DFS_DLLPRG1_CALBYPEN_OFFSET))
#define DFS_DLLPRG1_CALBYPEN_OFFSET (9)
#define DFS_DLLPRG1_CALBYPEN_MASK (0x00000200)
#define DFS_DLLPRG1_VSETTLCTRL_SET(val) (DFS_DLLPRG1_VSETTLCTRL_MASK & ((val) << DFS_DLLPRG1_VSETTLCTRL_OFFSET))
#define DFS_DLLPRG1_VSETTLCTRL_OFFSET (10)
#define DFS_DLLPRG1_VSETTLCTRL_MASK (0x00000C00)
#define DFS_DLLPRG1_CPICTRL_SET(val) (DFS_DLLPRG1_CPICTRL_MASK & ((val) << DFS_DLLPRG1_CPICTRL_OFFSET))
#define DFS_DLLPRG1_CPICTRL_OFFSET (12)
#define DFS_DLLPRG1_CPICTRL_MASK (0x00007000)
/* DFS Control Register (DFS_CTRL) */
#define DFS_CTRL(pll) (DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80))
#define DFS_CTRL_DLL_LOLIE (1 << 0)
#define DFS_CTRL_DLL_RESET (1 << 1)
/* DFS Port Status Register (DFS_PORTSR) */
#define DFS_PORTSR(pll) (DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80))
/* DFS Port Reset Register (DFS_PORTRESET) */
#define DFS_PORTRESET(pll) (DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80))
#define DFS_PORTRESET_PORTRESET_SET(val) (DFS_PORTRESET_PORTRESET_MASK | (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) << DFS_PORTRESET_PORTRESET_OFFSET))
#define DFS_PORTRESET_PORTRESET_MAXVAL (0xF)
#define DFS_PORTRESET_PORTRESET_MASK (0x0000000F)
#define DFS_PORTRESET_PORTRESET_OFFSET (0)
/* DFS Divide Register Portn (DFS_DVPORTn) */
#define DFS_DVPORTn(pll,n) (DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4)))
/*
* The mathematical formula for fdfs_clockout is the following:
* fdfs_clckout = fdfs_clkin / ( DFS_DVPORTn[MFI] + (DFS_DVPORTn[MFN]/256) )
*/
#define DFS_DVPORTn_MFI_SET(val) (DFS_DVPORTn_MFI_MASK & (((val) & DFS_DVPORTn_MFI_MAXVAL) << DFS_DVPORTn_MFI_OFFSET) )
#define DFS_DVPORTn_MFN_SET(val) (DFS_DVPORTn_MFN_MASK & (((val) & DFS_DVPORTn_MFN_MAXVAL) << DFS_DVPORTn_MFN_OFFSET) )
#define DFS_DVPORTn_MFI_MASK (0x0000FF00)
#define DFS_DVPORTn_MFN_MASK (0x000000FF)
#define DFS_DVPORTn_MFI_MAXVAL (0xFF)
#define DFS_DVPORTn_MFN_MAXVAL (0xFF)
#define DFS_DVPORTn_MFI_OFFSET (8)
#define DFS_DVPORTn_MFN_OFFSET (0)
#define DFS_MAXNUMBER (4)
#define DFS_PARAMS_Nr (3)
/* Frequencies are in Hz */
#define FIRC_CLK_FREQ (48000000)
#define XOSC_CLK_FREQ (40000000)
#define PLL_MIN_FREQ (650000000)
#define PLL_MAX_FREQ (1300000000)
#define ARM_PLL_PHI0_FREQ (1000000000)
#define ARM_PLL_PHI1_FREQ (1000000000)
/* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */
#define ARM_PLL_PHI1_DFS1_EN (1)
#define ARM_PLL_PHI1_DFS1_MFI (3)
#define ARM_PLL_PHI1_DFS1_MFN (194)
/* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */
#define ARM_PLL_PHI1_DFS2_EN (1)
#define ARM_PLL_PHI1_DFS2_MFI (1)
#define ARM_PLL_PHI1_DFS2_MFN (170)
/* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */
#define ARM_PLL_PHI1_DFS3_EN (1)
#define ARM_PLL_PHI1_DFS3_MFI (1)
#define ARM_PLL_PHI1_DFS3_MFN (170)
#define ARM_PLL_PHI1_DFS_Nr (3)
#define ARM_PLL_PLLDV_PREDIV (2)
#define ARM_PLL_PLLDV_MFD (50)
#define ARM_PLL_PLLDV_MFN (0)
#define PERIPH_PLL_PHI0_FREQ (400000000)
#define PERIPH_PLL_PHI1_FREQ (100000000)
#define PERIPH_PLL_PHI1_DFS_Nr (0)
#define PERIPH_PLL_PLLDV_PREDIV (1)
#define PERIPH_PLL_PLLDV_MFD (30)
#define PERIPH_PLL_PLLDV_MFN (0)
#define ENET_PLL_PHI0_FREQ (500000000)
#define ENET_PLL_PHI1_FREQ (1000000000)
/* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/
#define ENET_PLL_PHI1_DFS1_EN (1)
#define ENET_PLL_PHI1_DFS1_MFI (2)
#define ENET_PLL_PHI1_DFS1_MFN (219)
/* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/
#define ENET_PLL_PHI1_DFS2_EN (1)
#define ENET_PLL_PHI1_DFS2_MFI (2)
#define ENET_PLL_PHI1_DFS2_MFN (219)
/* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/
#define ENET_PLL_PHI1_DFS3_EN (1)
#define ENET_PLL_PHI1_DFS3_MFI (3)
#define ENET_PLL_PHI1_DFS3_MFN (32)
/* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/
#define ENET_PLL_PHI1_DFS4_EN (1)
#define ENET_PLL_PHI1_DFS4_MFI (2)
#define ENET_PLL_PHI1_DFS4_MFN (0)
#define ENET_PLL_PHI1_DFS_Nr (4)
#define ENET_PLL_PLLDV_PREDIV (2)
#define ENET_PLL_PLLDV_MFD (50)
#define ENET_PLL_PLLDV_MFN (0)
#define DDR_PLL_PHI0_FREQ (533000000)
#define DDR_PLL_PHI1_FREQ (1066000000)
/* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */
#define DDR_PLL_PHI1_DFS1_EN (1)
#define DDR_PLL_PHI1_DFS1_MFI (2)
#define DDR_PLL_PHI1_DFS1_MFN (33)
/* DDR_PLL_PHI1_DFS2_REQ - 500 Mhz */
#define DDR_PLL_PHI1_DFS2_EN (1)
#define DDR_PLL_PHI1_DFS2_MFI (2)
#define DDR_PLL_PHI1_DFS2_MFN (33)
/* DDR_PLL_PHI1_DFS3_FREQ - 350 Mhz */
#define DDR_PLL_PHI1_DFS3_EN (1)
#define DDR_PLL_PHI1_DFS3_MFI (3)
#define DDR_PLL_PHI1_DFS3_MFN (11)
#define DDR_PLL_PHI1_DFS_Nr (3)
#define DDR_PLL_PLLDV_PREDIV (2)
#define DDR_PLL_PLLDV_MFD (53)
#define DDR_PLL_PLLDV_MFN (6144)
#define VIDEO_PLL_PHI0_FREQ (600000000)
#define VIDEO_PLL_PHI1_FREQ (0)
#define VIDEO_PLL_PHI1_DFS_Nr (0)
#define VIDEO_PLL_PLLDV_PREDIV (1)
#define VIDEO_PLL_PLLDV_MFD (30)
#define VIDEO_PLL_PLLDV_MFN (0)
#endif
#endif /*__ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ */

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arch/arm/include/asm/arch-s32v234/mc_me_regs.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015, Freescale Semiconductor, Inc.
*/
#ifndef __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
#define __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
#ifndef __ASSEMBLY__
/* MC_ME registers definitions */
/* MC_ME_GS */
#define MC_ME_GS (MC_ME_BASE_ADDR + 0x00000000)
#define MC_ME_GS_S_SYSCLK_FIRC (0x0 << 0)
#define MC_ME_GS_S_SYSCLK_FXOSC (0x1 << 0)
#define MC_ME_GS_S_SYSCLK_ARMPLL (0x2 << 0)
#define MC_ME_GS_S_STSCLK_DISABLE (0xF << 0)
#define MC_ME_GS_S_FIRC (1 << 4)
#define MC_ME_GS_S_XOSC (1 << 5)
#define MC_ME_GS_S_ARMPLL (1 << 6)
#define MC_ME_GS_S_PERPLL (1 << 7)
#define MC_ME_GS_S_ENETPLL (1 << 8)
#define MC_ME_GS_S_DDRPLL (1 << 9)
#define MC_ME_GS_S_VIDEOPLL (1 << 10)
#define MC_ME_GS_S_MVR (1 << 20)
#define MC_ME_GS_S_PDO (1 << 23)
#define MC_ME_GS_S_MTRANS (1 << 27)
#define MC_ME_GS_S_CRT_MODE_RESET (0x0 << 28)
#define MC_ME_GS_S_CRT_MODE_TEST (0x1 << 28)
#define MC_ME_GS_S_CRT_MODE_DRUN (0x3 << 28)
#define MC_ME_GS_S_CRT_MODE_RUN0 (0x4 << 28)
#define MC_ME_GS_S_CRT_MODE_RUN1 (0x5 << 28)
#define MC_ME_GS_S_CRT_MODE_RUN2 (0x6 << 28)
#define MC_ME_GS_S_CRT_MODE_RUN3 (0x7 << 28)
/* MC_ME_MCTL */
#define MC_ME_MCTL (MC_ME_BASE_ADDR + 0x00000004)
#define MC_ME_MCTL_KEY (0x00005AF0)
#define MC_ME_MCTL_INVERTEDKEY (0x0000A50F)
#define MC_ME_MCTL_RESET (0x0 << 28)
#define MC_ME_MCTL_TEST (0x1 << 28)
#define MC_ME_MCTL_DRUN (0x3 << 28)
#define MC_ME_MCTL_RUN0 (0x4 << 28)
#define MC_ME_MCTL_RUN1 (0x5 << 28)
#define MC_ME_MCTL_RUN2 (0x6 << 28)
#define MC_ME_MCTL_RUN3 (0x7 << 28)
/* MC_ME_ME */
#define MC_ME_ME (MC_ME_BASE_ADDR + 0x00000008)
#define MC_ME_ME_RESET_FUNC (1 << 0)
#define MC_ME_ME_TEST (1 << 1)
#define MC_ME_ME_DRUN (1 << 3)
#define MC_ME_ME_RUN0 (1 << 4)
#define MC_ME_ME_RUN1 (1 << 5)
#define MC_ME_ME_RUN2 (1 << 6)
#define MC_ME_ME_RUN3 (1 << 7)
/* MC_ME_RUN_PCn */
#define MC_ME_RUN_PCn(n) (MC_ME_BASE_ADDR + 0x00000080 + 0x4 * (n))
#define MC_ME_RUN_PCn_RESET (1 << 0)
#define MC_ME_RUN_PCn_TEST (1 << 1)
#define MC_ME_RUN_PCn_DRUN (1 << 3)
#define MC_ME_RUN_PCn_RUN0 (1 << 4)
#define MC_ME_RUN_PCn_RUN1 (1 << 5)
#define MC_ME_RUN_PCn_RUN2 (1 << 6)
#define MC_ME_RUN_PCn_RUN3 (1 << 7)
/*
* MC_ME_RESET_MC/MC_ME_TEST_MC
* MC_ME_DRUN_MC
* MC_ME_RUNn_MC
*/
#define MC_ME_RESET_MC (MC_ME_BASE_ADDR + 0x00000020)
#define MC_ME_TEST_MC (MC_ME_BASE_ADDR + 0x00000024)
#define MC_ME_DRUN_MC (MC_ME_BASE_ADDR + 0x0000002C)
#define MC_ME_RUNn_MC(n) (MC_ME_BASE_ADDR + 0x00000030 + 0x4 * (n))
#define MC_ME_RUNMODE_MC_SYSCLK(val) (MC_ME_RUNMODE_MC_SYSCLK_MASK & (val))
#define MC_ME_RUNMODE_MC_SYSCLK_MASK (0x0000000F)
#define MC_ME_RUNMODE_MC_FIRCON (1 << 4)
#define MC_ME_RUNMODE_MC_XOSCON (1 << 5)
#define MC_ME_RUNMODE_MC_PLL(pll) (1 << (6 + (pll)))
#define MC_ME_RUNMODE_MC_MVRON (1 << 20)
#define MC_ME_RUNMODE_MC_PDO (1 << 23)
#define MC_ME_RUNMODE_MC_PWRLVL0 (1 << 28)
#define MC_ME_RUNMODE_MC_PWRLVL1 (1 << 29)
#define MC_ME_RUNMODE_MC_PWRLVL2 (1 << 30)
/* MC_ME_DRUN_SEC_CC_I */
#define MC_ME_DRUN_SEC_CC_I (MC_ME_BASE_ADDR + 0x260)
/* MC_ME_RUNn_SEC_CC_I */
#define MC_ME_RUNn_SEC_CC_I(n) (MC_ME_BASE_ADDR + 0x270 + (n) * 0x10)
#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK(val,offset) ((MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK & (val)) << offset)
#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET (4)
#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET (8)
#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET (12)
#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK (0x3)
/*
* ME_PCTLn
* Please note that these registers are 8 bits width, so
* the operations over them should be done using 8 bits operations.
*/
#define MC_ME_PCTLn_RUNPCm(n) ( (n) & MC_ME_PCTLn_RUNPCm_MASK )
#define MC_ME_PCTLn_RUNPCm_MASK (0x7)
/* DEC200 Peripheral Control Register */
#define MC_ME_PCTL39 (MC_ME_BASE_ADDR + 0x000000E4)
/* 2D-ACE Peripheral Control Register */
#define MC_ME_PCTL40 (MC_ME_BASE_ADDR + 0x000000EB)
/* ENET Peripheral Control Register */
#define MC_ME_PCTL50 (MC_ME_BASE_ADDR + 0x000000F1)
/* DMACHMUX0 Peripheral Control Register */
#define MC_ME_PCTL49 (MC_ME_BASE_ADDR + 0x000000F2)
/* CSI0 Peripheral Control Register */
#define MC_ME_PCTL48 (MC_ME_BASE_ADDR + 0x000000F3)
/* MMDC0 Peripheral Control Register */
#define MC_ME_PCTL54 (MC_ME_BASE_ADDR + 0x000000F5)
/* FRAY Peripheral Control Register */
#define MC_ME_PCTL52 (MC_ME_BASE_ADDR + 0x000000F7)
/* PIT0 Peripheral Control Register */
#define MC_ME_PCTL58 (MC_ME_BASE_ADDR + 0x000000F9)
/* FlexTIMER0 Peripheral Control Register */
#define MC_ME_PCTL79 (MC_ME_BASE_ADDR + 0x0000010C)
/* SARADC0 Peripheral Control Register */
#define MC_ME_PCTL77 (MC_ME_BASE_ADDR + 0x0000010E)
/* LINFLEX0 Peripheral Control Register */
#define MC_ME_PCTL83 (MC_ME_BASE_ADDR + 0x00000110)
/* IIC0 Peripheral Control Register */
#define MC_ME_PCTL81 (MC_ME_BASE_ADDR + 0x00000112)
/* DSPI0 Peripheral Control Register */
#define MC_ME_PCTL87 (MC_ME_BASE_ADDR + 0x00000114)
/* CANFD0 Peripheral Control Register */
#define MC_ME_PCTL85 (MC_ME_BASE_ADDR + 0x00000116)
/* CRC0 Peripheral Control Register */
#define MC_ME_PCTL91 (MC_ME_BASE_ADDR + 0x00000118)
/* DSPI2 Peripheral Control Register */
#define MC_ME_PCTL89 (MC_ME_BASE_ADDR + 0x0000011A)
/* SDHC Peripheral Control Register */
#define MC_ME_PCTL93 (MC_ME_BASE_ADDR + 0x0000011E)
/* VIU0 Peripheral Control Register */
#define MC_ME_PCTL100 (MC_ME_BASE_ADDR + 0x00000127)
/* HPSMI Peripheral Control Register */
#define MC_ME_PCTL104 (MC_ME_BASE_ADDR + 0x0000012B)
/* SIPI Peripheral Control Register */
#define MC_ME_PCTL116 (MC_ME_BASE_ADDR + 0x00000137)
/* LFAST Peripheral Control Register */
#define MC_ME_PCTL120 (MC_ME_BASE_ADDR + 0x0000013B)
/* MMDC1 Peripheral Control Register */
#define MC_ME_PCTL162 (MC_ME_BASE_ADDR + 0x00000161)
/* DMACHMUX1 Peripheral Control Register */
#define MC_ME_PCTL161 (MC_ME_BASE_ADDR + 0x00000162)
/* CSI1 Peripheral Control Register */
#define MC_ME_PCTL160 (MC_ME_BASE_ADDR + 0x00000163)
/* QUADSPI0 Peripheral Control Register */
#define MC_ME_PCTL166 (MC_ME_BASE_ADDR + 0x00000165)
/* PIT1 Peripheral Control Register */
#define MC_ME_PCTL170 (MC_ME_BASE_ADDR + 0x00000169)
/* FlexTIMER1 Peripheral Control Register */
#define MC_ME_PCTL182 (MC_ME_BASE_ADDR + 0x00000175)
/* IIC2 Peripheral Control Register */
#define MC_ME_PCTL186 (MC_ME_BASE_ADDR + 0x00000179)
/* IIC1 Peripheral Control Register */
#define MC_ME_PCTL184 (MC_ME_BASE_ADDR + 0x0000017B)
/* CANFD1 Peripheral Control Register */
#define MC_ME_PCTL190 (MC_ME_BASE_ADDR + 0x0000017D)
/* LINFLEX1 Peripheral Control Register */
#define MC_ME_PCTL188 (MC_ME_BASE_ADDR + 0x0000017F)
/* DSPI3 Peripheral Control Register */
#define MC_ME_PCTL194 (MC_ME_BASE_ADDR + 0x00000181)
/* DSPI1 Peripheral Control Register */
#define MC_ME_PCTL192 (MC_ME_BASE_ADDR + 0x00000183)
/* TSENS Peripheral Control Register */
#define MC_ME_PCTL206 (MC_ME_BASE_ADDR + 0x0000018D)
/* CRC1 Peripheral Control Register */
#define MC_ME_PCTL204 (MC_ME_BASE_ADDR + 0x0000018F)
/* VIU1 Peripheral Control Register */
#define MC_ME_PCTL208 (MC_ME_BASE_ADDR + 0x00000193)
/* JPEG Peripheral Control Register */
#define MC_ME_PCTL212 (MC_ME_BASE_ADDR + 0x00000197)
/* H264_DEC Peripheral Control Register */
#define MC_ME_PCTL216 (MC_ME_BASE_ADDR + 0x0000019B)
/* H264_ENC Peripheral Control Register */
#define MC_ME_PCTL220 (MC_ME_BASE_ADDR + 0x0000019F)
/* MBIST Peripheral Control Register */
#define MC_ME_PCTL236 (MC_ME_BASE_ADDR + 0x000001A9)
/* Core status register */
#define MC_ME_CS (MC_ME_BASE_ADDR + 0x000001C0)
#endif
#endif /*__ARCH_ARM_MACH_S32V234_MCME_REGS_H__ */

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arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015, Freescale Semiconductor, Inc.
*/
#ifndef __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
#define __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
#define MC_RGM_DES (MC_RGM_BASE_ADDR)
#define MC_RGM_FES (MC_RGM_BASE_ADDR + 0x300)
#define MC_RGM_FERD (MC_RGM_BASE_ADDR + 0x310)
#define MC_RGM_FBRE (MC_RGM_BASE_ADDR + 0x330)
#define MC_RGM_FESS (MC_RGM_BASE_ADDR + 0x340)
#define MC_RGM_DDR_HE (MC_RGM_BASE_ADDR + 0x350)
#define MC_RGM_DDR_HS (MC_RGM_BASE_ADDR + 0x354)
#define MC_RGM_FRHE (MC_RGM_BASE_ADDR + 0x358)
#define MC_RGM_FREC (MC_RGM_BASE_ADDR + 0x600)
#define MC_RGM_FRET (MC_RGM_BASE_ADDR + 0x607)
#define MC_RGM_DRET (MC_RGM_BASE_ADDR + 0x60B)
/* function reset sources mask */
#define F_SWT4 0x8000
#define F_JTAG 0x400
#define F_FCCU_SOFT 0x40
#define F_FCCU_HARD 0x20
#define F_SOFT_FUNC 0x8
#define F_ST_DONE 0x4
#define F_EXT_RST 0x1
#endif /* __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ */

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arch/arm/include/asm/arch-s32v234/mmdc.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015, Freescale Semiconductor, Inc.
*/
#ifndef __ARCH_ARM_MACH_S32V234_MMDC_H__
#define __ARCH_ARM_MACH_S32V234_MMDC_H__
#define MMDC0 0
#define MMDC1 1
#define MMDC_MDCTL 0x0
#define MMDC_MDPDC 0x4
#define MMDC_MDOTC 0x8
#define MMDC_MDCFG0 0xC
#define MMDC_MDCFG1 0x10
#define MMDC_MDCFG2 0x14
#define MMDC_MDMISC 0x18
#define MMDC_MDSCR 0x1C
#define MMDC_MDREF 0x20
#define MMDC_MDRWD 0x2C
#define MMDC_MDOR 0x30
#define MMDC_MDMRR 0x34
#define MMDC_MDCFG3LP 0x38
#define MMDC_MDMR4 0x3C
#define MMDC_MDASP 0x40
#define MMDC_MAARCR 0x400
#define MMDC_MAPSR 0x404
#define MMDC_MAEXIDR0 0x408
#define MMDC_MAEXIDR1 0x40C
#define MMDC_MADPCR0 0x410
#define MMDC_MADPCR1 0x414
#define MMDC_MADPSR0 0x418
#define MMDC_MADPSR1 0x41C
#define MMDC_MADPSR2 0x420
#define MMDC_MADPSR3 0x424
#define MMDC_MADPSR4 0x428
#define MMDC_MADPSR5 0x42C
#define MMDC_MASBS0 0x430
#define MMDC_MASBS1 0x434
#define MMDC_MAGENP 0x440
#define MMDC_MPZQHWCTRL 0x800
#define MMDC_MPWLGCR 0x808
#define MMDC_MPWLDECTRL0 0x80C
#define MMDC_MPWLDECTRL1 0x810
#define MMDC_MPWLDLST 0x814
#define MMDC_MPODTCTRL 0x818
#define MMDC_MPRDDQBY0DL 0x81C
#define MMDC_MPRDDQBY1DL 0x820
#define MMDC_MPRDDQBY2DL 0x824
#define MMDC_MPRDDQBY3DL 0x828
#define MMDC_MPDGCTRL0 0x83C
#define MMDC_MPDGCTRL1 0x840
#define MMDC_MPDGDLST0 0x844
#define MMDC_MPRDDLCTL 0x848
#define MMDC_MPRDDLST 0x84C
#define MMDC_MPWRDLCTL 0x850
#define MMDC_MPWRDLST 0x854
#define MMDC_MPZQLP2CTL 0x85C
#define MMDC_MPRDDLHWCTL 0x860
#define MMDC_MPWRDLHWCTL 0x864
#define MMDC_MPRDDLHWST0 0x868
#define MMDC_MPRDDLHWST1 0x86C
#define MMDC_MPWRDLHWST1 0x870
#define MMDC_MPWRDLHWST2 0x874
#define MMDC_MPWLHWERR 0x878
#define MMDC_MPDGHWST0 0x87C
#define MMDC_MPDGHWST1 0x880
#define MMDC_MPDGHWST2 0x884
#define MMDC_MPDGHWST3 0x888
#define MMDC_MPPDCMPR1 0x88C
#define MMDC_MPPDCMPR2 0x890
#define MMDC_MPSWDAR0 0x894
#define MMDC_MPSWDRDR0 0x898
#define MMDC_MPSWDRDR1 0x89C
#define MMDC_MPSWDRDR2 0x8A0
#define MMDC_MPSWDRDR3 0x8A4
#define MMDC_MPSWDRDR4 0x8A8
#define MMDC_MPSWDRDR5 0x8AC
#define MMDC_MPSWDRDR6 0x8B0
#define MMDC_MPSWDRDR7 0x8B4
#define MMDC_MPMUR0 0x8B8
#define MMDC_MPDCCR 0x8C0
#define MMDC_MPMUR0_FRC_MSR (1 << 11)
#define MMDC_MPZQHWCTRL_ZQ_HW_FOR (1 << 16)
#endif

149
arch/arm/include/asm/arch-s32v234/siul.h
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@ -1,149 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015, Freescale Semiconductor, Inc.
*/
#ifndef __ARCH_ARM_MACH_S32V234_SIUL_H__
#define __ARCH_ARM_MACH_S32V234_SIUL_H__
#include "ddr.h"
#define SIUL2_MIDR1 (SIUL2_BASE_ADDR + 0x00000004)
#define SIUL2_MIDR2 (SIUL2_BASE_ADDR + 0x00000008)
#define SIUL2_DISR0 (SIUL2_BASE_ADDR + 0x00000010)
#define SIUL2_DIRER0 (SIUL2_BASE_ADDR + 0x00000018)
#define SIUL2_DIRSR0 (SIUL2_BASE_ADDR + 0x00000020)
#define SIUL2_IREER0 (SIUL2_BASE_ADDR + 0x00000028)
#define SIUL2_IFEER0 (SIUL2_BASE_ADDR + 0x00000030)
#define SIUL2_IFER0 (SIUL2_BASE_ADDR + 0x00000038)
#define SIUL2_IFMCR_BASE (SIUL2_BASE_ADDR + 0x00000040)
#define SIUL2_IFMCRn(i) (SIUL2_IFMCR_BASE + 4 * (i))
#define SIUL2_IFCPR (SIUL2_BASE_ADDR + 0x000000C0)
/* SIUL2_MSCR specifications as stated in Reference Manual:
* 0 - 359 Output Multiplexed Signal Configuration Registers
* 512- 1023 Input Multiplexed Signal Configuration Registers */
#define SIUL2_MSCR_BASE (SIUL2_BASE_ADDR + 0x00000240)
#define SIUL2_MSCRn(i) (SIUL2_MSCR_BASE + 4 * (i))
#define SIUL2_IMCR_BASE (SIUL2_BASE_ADDR + 0x00000A40)
#define SIUL2_IMCRn(i) (SIUL2_IMCR_BASE + 4 * (i))
#define SIUL2_GPDO_BASE (SIUL2_BASE_ADDR + 0x00001300)
#define SIUL2_GPDOn(i) (SIUL2_GPDO_BASE + 4 * (i))
#define SIUL2_GPDI_BASE (SIUL2_BASE_ADDR + 0x00001500)
#define SIUL2_GPDIn(i) (SIUL2_GPDI_BASE + 4 * (i))
#define SIUL2_PGPDO_BASE (SIUL2_BASE_ADDR + 0x00001700)
#define SIUL2_PGPDOn(i) (SIUL2_PGPDO_BASE + 2 * (i))
#define SIUL2_PGPDI_BASE (SIUL2_BASE_ADDR + 0x00001740)
#define SIUL2_PGPDIn(i) (SIUL2_PGPDI_BASE + 2 * (i))
#define SIUL2_MPGPDO_BASE (SIUL2_BASE_ADDR + 0x00001780)
#define SIUL2_MPGPDOn(i) (SIUL2_MPGPDO_BASE + 4 * (i))
/* SIUL2_MSCR masks */
#define SIUL2_MSCR_DDR_DO_TRIM(v) ((v) & 0xC0000000)
#define SIUL2_MSCR_DDR_DO_TRIM_MIN (0 << 30)
#define SIUL2_MSCR_DDR_DO_TRIM_50PS (1 << 30)
#define SIUL2_MSCR_DDR_DO_TRIM_100PS (2 << 30)
#define SIUL2_MSCR_DDR_DO_TRIM_150PS (3 << 30)
#define SIUL2_MSCR_DDR_INPUT(v) ((v) & 0x20000000)
#define SIUL2_MSCR_DDR_INPUT_CMOS (0 << 29)
#define SIUL2_MSCR_DDR_INPUT_DIFF_DDR (1 << 29)
#define SIUL2_MSCR_DDR_SEL(v) ((v) & 0x18000000)
#define SIUL2_MSCR_DDR_SEL_DDR3 (0 << 27)
#define SIUL2_MSCR_DDR_SEL_LPDDR2 (2 << 27)
#define SIUL2_MSCR_DDR_ODT(v) ((v) & 0x07000000)
#define SIUL2_MSCR_DDR_ODT_120ohm (1 << 24)
#define SIUL2_MSCR_DDR_ODT_60ohm (2 << 24)
#define SIUL2_MSCR_DDR_ODT_40ohm (3 << 24)
#define SIUL2_MSCR_DDR_ODT_30ohm (4 << 24)
#define SIUL2_MSCR_DDR_ODT_24ohm (5 << 24)
#define SIUL2_MSCR_DDR_ODT_20ohm (6 << 24)
#define SIUL2_MSCR_DDR_ODT_17ohm (7 << 24)
#define SIUL2_MSCR_DCYCLE_TRIM(v) ((v) & 0x00C00000)
#define SIUL2_MSCR_DCYCLE_TRIM_NONE (0 << 22)
#define SIUL2_MSCR_DCYCLE_TRIM_LEFT (1 << 22)
#define SIUL2_MSCR_DCYCLE_TRIM_RIGHT (2 << 22)
#define SIUL2_MSCR_OBE(v) ((v) & 0x00200000)
#define SIUL2_MSCR_OBE_EN (1 << 21)
#define SIUL2_MSCR_ODE(v) ((v) & 0x00100000)
#define SIUL2_MSCR_ODE_EN (1 << 20)
#define SIUL2_MSCR_IBE(v) ((v) & 0x00010000)
#define SIUL2_MSCR_IBE_EN (1 << 19)
#define SIUL2_MSCR_HYS(v) ((v) & 0x00400000)
#define SIUL2_MSCR_HYS_EN (1 << 18)
#define SIUL2_MSCR_INV(v) ((v) & 0x00020000)
#define SIUL2_MSCR_INV_EN (1 << 17)
#define SIUL2_MSCR_PKE(v) ((v) & 0x00010000)
#define SIUL2_MSCR_PKE_EN (1 << 16)
#define SIUL2_MSCR_SRE(v) ((v) & 0x0000C000)
#define SIUL2_MSCR_SRE_SPEED_LOW_50 (0 << 14)
#define SIUL2_MSCR_SRE_SPEED_LOW_100 (1 << 14)
#define SIUL2_MSCR_SRE_SPEED_HIGH_100 (2 << 14)
#define SIUL2_MSCR_SRE_SPEED_HIGH_200 (3 << 14)
#define SIUL2_MSCR_PUE(v) ((v) & 0x00002000)
#define SIUL2_MSCR_PUE_EN (1 << 13)
#define SIUL2_MSCR_PUS(v) ((v) & 0x00001800)
#define SIUL2_MSCR_PUS_100K_DOWN (0 << 11)
#define SIUL2_MSCR_PUS_50K_DOWN (1 << 11)
#define SIUL2_MSCR_PUS_100K_UP (2 << 11)
#define SIUL2_MSCR_PUS_33K_UP (3 << 11)
#define SIUL2_MSCR_DSE(v) ((v) & 0x00000700)
#define SIUL2_MSCR_DSE_240ohm (1 << 8)
#define SIUL2_MSCR_DSE_120ohm (2 << 8)
#define SIUL2_MSCR_DSE_80ohm (3 << 8)
#define SIUL2_MSCR_DSE_60ohm (4 << 8)
#define SIUL2_MSCR_DSE_48ohm (5 << 8)
#define SIUL2_MSCR_DSE_40ohm (6 << 8)
#define SIUL2_MSCR_DSE_34ohm (7 << 8)
#define SIUL2_MSCR_CRPOINT_TRIM(v) ((v) & 0x000000C0)
#define SIUL2_MSCR_CRPOINT_TRIM_1 (1 << 6)
#define SIUL2_MSCR_SMC(v) ((v) & 0x00000020)
#define SIUL2_MSCR_MUX_MODE(v) ((v) & 0x0000000f)
#define SIUL2_MSCR_MUX_MODE_ALT1 (0x1)
#define SIUL2_MSCR_MUX_MODE_ALT2 (0x2)
#define SIUL2_MSCR_MUX_MODE_ALT3 (0x3)
/* UART settings */
#define SIUL2_UART0_TXD_PAD 12
#define SIUL2_UART_TXD (SIUL2_MSCR_OBE_EN | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_60ohm | \
SIUL2_MSCR_SRE_SPEED_LOW_100 | SIUL2_MSCR_MUX_MODE_ALT1)
#define SIUL2_UART0_MSCR_RXD_PAD 11
#define SIUL2_UART0_IMCR_RXD_PAD 200
#define SIUL2_UART_MSCR_RXD (SIUL2_MSCR_PUE_EN | SIUL2_MSCR_IBE_EN | SIUL2_MSCR_DCYCLE_TRIM_RIGHT)
#define SIUL2_UART_IMCR_RXD (SIUL2_MSCR_MUX_MODE_ALT2)
/* uSDHC settings */
#define SIUL2_USDHC_PAD_CTRL_BASE (SIUL2_MSCR_SRE_SPEED_HIGH_200 | SIUL2_MSCR_OBE_EN | \
SIUL2_MSCR_DSE_34ohm | SIUL2_MSCR_PKE_EN | SIUL2_MSCR_IBE_EN | \
SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_PUE_EN )
#define SIUL2_USDHC_PAD_CTRL_CMD (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT1)
#define SIUL2_USDHC_PAD_CTRL_CLK (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
#define SIUL2_USDHC_PAD_CTRL_DAT0_3 (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
#define SIUL2_USDHC_PAD_CTRL_DAT4_7 (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT3)
#endif /*__ARCH_ARM_MACH_S32V234_SIUL_H__ */

23
board/freescale/s32v234evb/Kconfig
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if TARGET_S32V234EVB
config SYS_CPU
string
default "armv8"
config SYS_BOARD
string
default "s32v234evb"
config SYS_VENDOR
string
default "freescale"
config SYS_SOC
string
default "s32v234"
config SYS_CONFIG_NAME
string
default "s32v234evb"
endif

8
board/freescale/s32v234evb/MAINTAINERS
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@ -1,8 +0,0 @@
S32V234 Evaluation BOARD
M: Eddy Petrișor <eddy.petrisor@gmail.com>
S: Maintained
F: arch/arm/cpu/armv8/s32v234/
F: arch/arm/include/asm/arch-s32v234/
F: board/freescale/s32v234evb/
F: include/configs/s32v234evb.h
F: configs/s32v234evb_defconfig

9
board/freescale/s32v234evb/Makefile
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# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2013-2015, Freescale Semiconductor, Inc.
obj-y := clock.o
obj-y += lpddr2.o
obj-y += s32v234evb.o
#########################################################################

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board/freescale/s32v234evb/clock.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015, Freescale Semiconductor, Inc.
*/
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mc_cgm_regs.h>
#include <asm/arch/mc_me_regs.h>
#include <asm/arch/clock.h>
/*
* Select the clock reference for required pll.
* pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL.
* refclk_freq - input referece clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)
*/
static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq)
{
u32 clk_src;
u32 pll_idx;
volatile struct src *src = (struct src *)SRC_SOC_BASE_ADDR;
/* select the pll clock source */
switch (refclk_freq) {
case FIRC_CLK_FREQ:
clk_src = SRC_GPR1_FIRC_CLK_SOURCE;
break;
case XOSC_CLK_FREQ:
clk_src = SRC_GPR1_XOSC_CLK_SOURCE;
break;
default:
/* The clock frequency for the source clock is unknown */
return -1;
}
/*
* The hardware definition is not uniform, it has to calculate again
* the recurrence formula.
*/
switch (pll) {
case PERIPH_PLL:
pll_idx = 3;
break;
case ENET_PLL:
pll_idx = 1;
break;
case DDR_PLL:
pll_idx = 2;
break;
default:
pll_idx = pll;
}
writel(readl(&src->gpr1) | SRC_GPR1_PLL_SOURCE(pll_idx, clk_src),
&src->gpr1);
return 0;
}
static void entry_to_target_mode(u32 mode)
{
writel(mode | MC_ME_MCTL_KEY, MC_ME_MCTL);
writel(mode | MC_ME_MCTL_INVERTEDKEY, MC_ME_MCTL);
while ((readl(MC_ME_GS) & MC_ME_GS_S_MTRANS) != 0x00000000) ;
}
/*
* Program the pll according to the input parameters.
* pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL.
* refclk_freq - input reference clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)
* freq - expected output frequency for PHY0
* freq1 - expected output frequency for PHY1
* dfs_nr - number of DFS modules for current PLL
* dfs - array with the activation dfs field, mfn and mfi
* plldv_prediv - divider of clkfreq_ref
* plldv_mfd - loop multiplication factor divider
* pllfd_mfn - numerator loop multiplication factor divider
* Please consult the PLLDIG chapter of platform manual
* before to use this function.
*)
*/
static int program_pll(enum pll_type pll, u32 refclk_freq, u32 freq0, u32 freq1,
u32 dfs_nr, u32 dfs[][DFS_PARAMS_Nr], u32 plldv_prediv,
u32 plldv_mfd, u32 pllfd_mfn)
{
u32 i, rfdphi1, rfdphi, dfs_on = 0, fvco;
/*
* This formula is from platform reference manual (Rev. 1, 6/2015), PLLDIG chapter.
*/
fvco =
(refclk_freq / plldv_prediv) * (plldv_mfd +
pllfd_mfn / (float)20480);
/*
* VCO should have value in [ PLL_MIN_FREQ, PLL_MAX_FREQ ]. Please consult
* the platform DataSheet in order to determine the allowed values.
*/
if (fvco < PLL_MIN_FREQ || fvco > PLL_MAX_FREQ) {
return -1;
}
if (select_pll_source_clk(pll, refclk_freq) < 0) {
return -1;
}
rfdphi = fvco / freq0;
rfdphi1 = (freq1 == 0) ? 0 : fvco / freq1;
writel(PLLDIG_PLLDV_RFDPHI1_SET(rfdphi1) |
PLLDIG_PLLDV_RFDPHI_SET(rfdphi) |
PLLDIG_PLLDV_PREDIV_SET(plldv_prediv) |
PLLDIG_PLLDV_MFD(plldv_mfd), PLLDIG_PLLDV(pll));
writel(readl(PLLDIG_PLLFD(pll)) | PLLDIG_PLLFD_MFN_SET(pllfd_mfn) |
PLLDIG_PLLFD_SMDEN, PLLDIG_PLLFD(pll));
/* switch on the pll in current mode */
writel(readl(MC_ME_RUNn_MC(0)) | MC_ME_RUNMODE_MC_PLL(pll),
MC_ME_RUNn_MC(0));
entry_to_target_mode(MC_ME_MCTL_RUN0);
/* Only ARM_PLL, ENET_PLL and DDR_PLL */
if ((pll == ARM_PLL) || (pll == ENET_PLL) || (pll == DDR_PLL)) {
/* DFS clk enable programming */
writel(DFS_CTRL_DLL_RESET, DFS_CTRL(pll));
writel(DFS_DLLPRG1_CPICTRL_SET(0x5) |
DFS_DLLPRG1_VSETTLCTRL_SET(0x1) |
DFS_DLLPRG1_CALBYPEN_SET(0x0) |
DFS_DLLPRG1_DACIN_SET(0x1) | DFS_DLLPRG1_LCKWT_SET(0x0) |
DFS_DLLPRG1_V2IGC_SET(0x5), DFS_DLLPRG1(pll));
for (i = 0; i < dfs_nr; i++) {
if (dfs[i][0]) {
writel(DFS_DVPORTn_MFI_SET(dfs[i][2]) |
DFS_DVPORTn_MFN_SET(dfs[i][1]),
DFS_DVPORTn(pll, i));
dfs_on |= (dfs[i][0] << i);
}
}
writel(readl(DFS_CTRL(pll)) & ~DFS_CTRL_DLL_RESET,
DFS_CTRL(pll));
writel(readl(DFS_PORTRESET(pll)) &
~DFS_PORTRESET_PORTRESET_SET(dfs_on),
DFS_PORTRESET(pll));
while ((readl(DFS_PORTSR(pll)) & dfs_on) != dfs_on) ;
}
entry_to_target_mode(MC_ME_MCTL_RUN0);
return 0;
}
static void aux_source_clk_config(uintptr_t cgm_addr, u8 ac, u32 source)
{
/* select the clock source */
writel(MC_CGM_ACn_SEL_SET(source), CGM_ACn_SC(cgm_addr, ac));
}
static void aux_div_clk_config(uintptr_t cgm_addr, u8 ac, u8 dc, u32 divider)
{
/* set the divider */
writel(MC_CGM_ACn_DCm_DE | MC_CGM_ACn_DCm_PREDIV(divider),
CGM_ACn_DCm(cgm_addr, ac, dc));
}
static void setup_sys_clocks(void)
{
/* set ARM PLL DFS 1 as SYSCLK */
writel((readl(MC_ME_RUNn_MC(0)) & ~MC_ME_RUNMODE_MC_SYSCLK_MASK) |
MC_ME_RUNMODE_MC_SYSCLK(0x2), MC_ME_RUNn_MC(0));
entry_to_target_mode(MC_ME_MCTL_RUN0);
/* select sysclks ARMPLL, ARMPLLDFS2, ARMPLLDFS3 */
writel(MC_ME_RUNMODE_SEC_CC_I_SYSCLK
(0x2,
MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET) |
MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2,
MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET)
| MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2,
MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET),
MC_ME_RUNn_SEC_CC_I(0));
/* setup the sys clock divider for CORE_CLK (1000MHz) */
writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0),
CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0));
/* setup the sys clock divider for CORE2_CLK (500MHz) */
writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1),
CGM_SC_DCn(MC_CGM1_BASE_ADDR, 1));
/* setup the sys clock divider for SYS3_CLK (266 MHz) */
writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0),
CGM_SC_DCn(MC_CGM0_BASE_ADDR, 0));
/* setup the sys clock divider for SYS6_CLK (133 Mhz) */
writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1),
CGM_SC_DCn(MC_CGM0_BASE_ADDR, 1));
entry_to_target_mode(MC_ME_MCTL_RUN0);
}
static void setup_aux_clocks(void)
{
/*
* setup the aux clock divider for PERI_CLK
* (source: PERIPH_PLL_PHI_0/5, PERI_CLK - 80 MHz)
*/
aux_source_clk_config(MC_CGM0_BASE_ADDR, 5, MC_CGM_ACn_SEL_PERPLLDIVX);
aux_div_clk_config(MC_CGM0_BASE_ADDR, 5, 0, 4);
/* setup the aux clock divider for LIN_CLK (40MHz) */
aux_source_clk_config(MC_CGM0_BASE_ADDR, 3, MC_CGM_ACn_SEL_PERPLLDIVX);
aux_div_clk_config(MC_CGM0_BASE_ADDR, 3, 0, 1);
/* setup the aux clock divider for ENET_TIME_CLK (50MHz) */
aux_source_clk_config(MC_CGM0_BASE_ADDR, 7, MC_CGM_ACn_SEL_ENETPLL);
aux_div_clk_config(MC_CGM0_BASE_ADDR, 7, 1, 9);
/* setup the aux clock divider for ENET_CLK (50MHz) */
aux_source_clk_config(MC_CGM2_BASE_ADDR, 2, MC_CGM_ACn_SEL_ENETPLL);
aux_div_clk_config(MC_CGM2_BASE_ADDR, 2, 0, 9);
/* setup the aux clock divider for SDHC_CLK (50 MHz). */
aux_source_clk_config(MC_CGM0_BASE_ADDR, 15, MC_CGM_ACn_SEL_ENETPLL);
aux_div_clk_config(MC_CGM0_BASE_ADDR, 15, 0, 9);
/* setup the aux clock divider for DDR_CLK (533MHz) and APEX_SYS_CLK (266MHz) */
aux_source_clk_config(MC_CGM0_BASE_ADDR, 8, MC_CGM_ACn_SEL_DDRPLL);
aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 0, 0);
/* setup the aux clock divider for DDR4_CLK (133,25MHz) */
aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 1, 3);
entry_to_target_mode(MC_ME_MCTL_RUN0);
}
static void enable_modules_clock(void)
{
/* PIT0 */
writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL58);
/* PIT1 */
writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL170);
/* LINFLEX0 */
writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL83);
/* LINFLEX1 */
writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL188);
/* ENET */
writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL50);
/* SDHC */
writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL93);
/* IIC0 */
writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL81);
/* IIC1 */
writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL184);
/* IIC2 */
writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL186);
/* MMDC0 */
writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL54);
/* MMDC1 */
writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL162);
entry_to_target_mode(MC_ME_MCTL_RUN0);
}
void clock_init(void)
{
unsigned int arm_dfs[ARM_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {
{ARM_PLL_PHI1_DFS1_EN, ARM_PLL_PHI1_DFS1_MFN,
ARM_PLL_PHI1_DFS1_MFI},
{ARM_PLL_PHI1_DFS2_EN, ARM_PLL_PHI1_DFS2_MFN,
ARM_PLL_PHI1_DFS2_MFI},
{ARM_PLL_PHI1_DFS3_EN, ARM_PLL_PHI1_DFS3_MFN,
ARM_PLL_PHI1_DFS3_MFI}
};
unsigned int enet_dfs[ENET_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {
{ENET_PLL_PHI1_DFS1_EN, ENET_PLL_PHI1_DFS1_MFN,
ENET_PLL_PHI1_DFS1_MFI},
{ENET_PLL_PHI1_DFS2_EN, ENET_PLL_PHI1_DFS2_MFN,
ENET_PLL_PHI1_DFS2_MFI},
{ENET_PLL_PHI1_DFS3_EN, ENET_PLL_PHI1_DFS3_MFN,
ENET_PLL_PHI1_DFS3_MFI},
{ENET_PLL_PHI1_DFS4_EN, ENET_PLL_PHI1_DFS4_MFN,
ENET_PLL_PHI1_DFS4_MFI}
};
unsigned int ddr_dfs[DDR_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {
{DDR_PLL_PHI1_DFS1_EN, DDR_PLL_PHI1_DFS1_MFN,
DDR_PLL_PHI1_DFS1_MFI},
{DDR_PLL_PHI1_DFS2_EN, DDR_PLL_PHI1_DFS2_MFN,
DDR_PLL_PHI1_DFS2_MFI},
{DDR_PLL_PHI1_DFS3_EN, DDR_PLL_PHI1_DFS3_MFN,
DDR_PLL_PHI1_DFS3_MFI}
};
writel(MC_ME_RUN_PCn_DRUN | MC_ME_RUN_PCn_RUN0 | MC_ME_RUN_PCn_RUN1 |
MC_ME_RUN_PCn_RUN2 | MC_ME_RUN_PCn_RUN3, MC_ME_RUN_PCn(0));
/* turn on FXOSC */
writel(MC_ME_RUNMODE_MC_MVRON | MC_ME_RUNMODE_MC_XOSCON |
MC_ME_RUNMODE_MC_FIRCON | MC_ME_RUNMODE_MC_SYSCLK(0x1),
MC_ME_RUNn_MC(0));
entry_to_target_mode(MC_ME_MCTL_RUN0);
program_pll(ARM_PLL, XOSC_CLK_FREQ, ARM_PLL_PHI0_FREQ,
ARM_PLL_PHI1_FREQ, ARM_PLL_PHI1_DFS_Nr, arm_dfs,
ARM_PLL_PLLDV_PREDIV, ARM_PLL_PLLDV_MFD, ARM_PLL_PLLDV_MFN);
setup_sys_clocks();
program_pll(PERIPH_PLL, XOSC_CLK_FREQ, PERIPH_PLL_PHI0_FREQ,
PERIPH_PLL_PHI1_FREQ, PERIPH_PLL_PHI1_DFS_Nr, NULL,
PERIPH_PLL_PLLDV_PREDIV, PERIPH_PLL_PLLDV_MFD,
PERIPH_PLL_PLLDV_MFN);
program_pll(ENET_PLL, XOSC_CLK_FREQ, ENET_PLL_PHI0_FREQ,
ENET_PLL_PHI1_FREQ, ENET_PLL_PHI1_DFS_Nr, enet_dfs,
ENET_PLL_PLLDV_PREDIV, ENET_PLL_PLLDV_MFD,
ENET_PLL_PLLDV_MFN);
program_pll(DDR_PLL, XOSC_CLK_FREQ, DDR_PLL_PHI0_FREQ,
DDR_PLL_PHI1_FREQ, DDR_PLL_PHI1_DFS_Nr, ddr_dfs,
DDR_PLL_PLLDV_PREDIV, DDR_PLL_PLLDV_MFD, DDR_PLL_PLLDV_MFN);
program_pll(VIDEO_PLL, XOSC_CLK_FREQ, VIDEO_PLL_PHI0_FREQ,
VIDEO_PLL_PHI1_FREQ, VIDEO_PLL_PHI1_DFS_Nr, NULL,
VIDEO_PLL_PLLDV_PREDIV, VIDEO_PLL_PLLDV_MFD,
VIDEO_PLL_PLLDV_MFN);
setup_aux_clocks();
enable_modules_clock();
}

136
board/freescale/s32v234evb/lpddr2.c
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@ -1,136 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015, Freescale Semiconductor, Inc.
*/
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/siul.h>
#include <asm/arch/lpddr2.h>
#include <asm/arch/mmdc.h>
volatile int mscr_offset_ck0;
void lpddr2_config_iomux(uint8_t module)
{
int i;
switch (module) {
case DDR0:
mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0);
writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0));
writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0));
writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1));
writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0));
writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1));
for (i = _DDR0_DM0; i <= _DDR0_DM3; i++)
writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));
for (i = _DDR0_DQS0; i <= _DDR0_DQS3; i++)
writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));
for (i = _DDR0_A0; i <= _DDR0_A9; i++)
writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));
for (i = _DDR0_D0; i <= _DDR0_D31; i++)
writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));
break;
case DDR1:
writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0));
writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0));
writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1));
writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0));
writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1));
for (i = _DDR1_DM0; i <= _DDR1_DM3; i++)
writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));
for (i = _DDR1_DQS0; i <= _DDR1_DQS3; i++)
writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));
for (i = _DDR1_A0; i <= _DDR1_A9; i++)
writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));
for (i = _DDR1_D0; i <= _DDR1_D31; i++)
writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));
break;
}
}
void config_mmdc(uint8_t module)
{
unsigned long mmdc_addr = (module) ? MMDC1_BASE_ADDR : MMDC0_BASE_ADDR;
writel(MMDC_MDSCR_CFG_VALUE, mmdc_addr + MMDC_MDSCR);
writel(MMDC_MDCFG0_VALUE, mmdc_addr + MMDC_MDCFG0);
writel(MMDC_MDCFG1_VALUE, mmdc_addr + MMDC_MDCFG1);
writel(MMDC_MDCFG2_VALUE, mmdc_addr + MMDC_MDCFG2);
writel(MMDC_MDCFG3LP_VALUE, mmdc_addr + MMDC_MDCFG3LP);
writel(MMDC_MDOTC_VALUE, mmdc_addr + MMDC_MDOTC);
writel(MMDC_MDMISC_VALUE, mmdc_addr + MMDC_MDMISC);
writel(MMDC_MDOR_VALUE, mmdc_addr + MMDC_MDOR);
writel(_MDCTL, mmdc_addr + MMDC_MDCTL);
writel(MMDC_MPMUR0_VALUE, mmdc_addr + MMDC_MPMUR0);
while (readl(mmdc_addr + MMDC_MPMUR0) & MMDC_MPMUR0_FRC_MSR) {
}
writel(MMDC_MDSCR_RST_VALUE, mmdc_addr + MMDC_MDSCR);
/* Perform ZQ calibration */
writel(MMDC_MPZQLP2CTL_VALUE, mmdc_addr + MMDC_MPZQLP2CTL);
writel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL);
while (readl(mmdc_addr + MMDC_MPZQHWCTRL) & MMDC_MPZQHWCTRL_ZQ_HW_FOR) {
}
/* Enable MMDC with CS0 */
writel(_MDCTL + 0x80000000, mmdc_addr + MMDC_MDCTL);
/* Complete the initialization sequence as defined by JEDEC */
writel(MMDC_MDSCR_MR1_VALUE, mmdc_addr + MMDC_MDSCR);
writel(MMDC_MDSCR_MR2_VALUE, mmdc_addr + MMDC_MDSCR);
writel(MMDC_MDSCR_MR3_VALUE, mmdc_addr + MMDC_MDSCR);
writel(MMDC_MDSCR_MR10_VALUE, mmdc_addr + MMDC_MDSCR);
/* Set the amount of DRAM */
/* Set DQS settings based on board type */
switch (module) {
case MMDC0:
writel(MMDC_MDASP_MODULE0_VALUE, mmdc_addr + MMDC_MDASP);
writel(MMDC_MPRDDLCTL_MODULE0_VALUE,
mmdc_addr + MMDC_MPRDDLCTL);
writel(MMDC_MPWRDLCTL_MODULE0_VALUE,
mmdc_addr + MMDC_MPWRDLCTL);
writel(MMDC_MPDGCTRL0_MODULE0_VALUE,
mmdc_addr + MMDC_MPDGCTRL0);
writel(MMDC_MPDGCTRL1_MODULE0_VALUE,
mmdc_addr + MMDC_MPDGCTRL1);
break;
case MMDC1:
writel(MMDC_MDASP_MODULE1_VALUE, mmdc_addr + MMDC_MDASP);
writel(MMDC_MPRDDLCTL_MODULE1_VALUE,
mmdc_addr + MMDC_MPRDDLCTL);
writel(MMDC_MPWRDLCTL_MODULE1_VALUE,
mmdc_addr + MMDC_MPWRDLCTL);
writel(MMDC_MPDGCTRL0_MODULE1_VALUE,
mmdc_addr + MMDC_MPDGCTRL0);
writel(MMDC_MPDGCTRL1_MODULE1_VALUE,
mmdc_addr + MMDC_MPDGCTRL1);
break;
}
writel(MMDC_MDRWD_VALUE, mmdc_addr + MMDC_MDRWD);
writel(MMDC_MDPDC_VALUE, mmdc_addr + MMDC_MDPDC);
writel(MMDC_MDREF_VALUE, mmdc_addr + MMDC_MDREF);
writel(MMDC_MPODTCTRL_VALUE, mmdc_addr + MMDC_MPODTCTRL);
writel(MMDC_MDSCR_DEASSERT_VALUE, mmdc_addr + MMDC_MDSCR);
}

184
board/freescale/s32v234evb/s32v234evb.c
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@ -1,184 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2013-2015, Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <init.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/siul.h>
#include <asm/arch/lpddr2.h>
#include <asm/arch/clock.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
void setup_iomux_ddr(void)
{
lpddr2_config_iomux(DDR0);
lpddr2_config_iomux(DDR1);
}
void ddr_phy_init(void)
{
}
void ddr_ctrl_init(void)
{
config_mmdc(0);
config_mmdc(1);
}
int dram_init(void)
{
setup_iomux_ddr();
ddr_ctrl_init();
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
}
static void setup_iomux_uart(void)
{
/* Muxing for linflex */
/* Replace the magic values after bringup */
/* set TXD - MSCR[12] PA12 */
writel(SIUL2_UART_TXD, SIUL2_MSCRn(SIUL2_UART0_TXD_PAD));
/* set RXD - MSCR[11] - PA11 */
writel(SIUL2_UART_MSCR_RXD, SIUL2_MSCRn(SIUL2_UART0_MSCR_RXD_PAD));
/* set RXD - IMCR[200] - 200 */
writel(SIUL2_UART_IMCR_RXD, SIUL2_IMCRn(SIUL2_UART0_IMCR_RXD_PAD));
}
static void setup_iomux_enet(void)
{
}
static void setup_iomux_i2c(void)
{
}
#ifdef CONFIG_SYS_USE_NAND
void setup_iomux_nfc(void)
{
}
#endif
#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{USDHC_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
{
/* eSDHC1 is always present */
return 1;
}
int board_mmc_init(struct bd_info * bis)
{
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
/* Set iomux PADS for USDHC */
/* PK6 pad: uSDHC clk */
writel(SIUL2_USDHC_PAD_CTRL_CLK, SIUL2_MSCRn(150));
writel(0x3, SIUL2_MSCRn(902));
/* PK7 pad: uSDHC CMD */
writel(SIUL2_USDHC_PAD_CTRL_CMD, SIUL2_MSCRn(151));
writel(0x3, SIUL2_MSCRn(901));
/* PK8 pad: uSDHC DAT0 */
writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(152));
writel(0x3, SIUL2_MSCRn(903));
/* PK9 pad: uSDHC DAT1 */
writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(153));
writel(0x3, SIUL2_MSCRn(904));
/* PK10 pad: uSDHC DAT2 */
writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(154));
writel(0x3, SIUL2_MSCRn(905));
/* PK11 pad: uSDHC DAT3 */
writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(155));
writel(0x3, SIUL2_MSCRn(906));
/* PK15 pad: uSDHC DAT4 */
writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(159));
writel(0x3, SIUL2_MSCRn(907));
/* PL0 pad: uSDHC DAT5 */
writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(160));
writel(0x3, SIUL2_MSCRn(908));
/* PL1 pad: uSDHC DAT6 */
writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(161));
writel(0x3, SIUL2_MSCRn(909));
/* PL2 pad: uSDHC DAT7 */
writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(162));
writel(0x3, SIUL2_MSCRn(910));
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
}
#endif
static void mscm_init(void)
{
struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
int i;
for (i = 0; i < MSCM_IRSPRC_NUM; i++)
writew(MSCM_IRSPRC_CPn_EN, &mscmir->irsprc[i]);
}
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
int board_early_init_f(void)
{
clock_init();
mscm_init();
setup_iomux_uart();
setup_iomux_enet();
setup_iomux_i2c();
#ifdef CONFIG_SYS_USE_NAND
setup_iomux_nfc();
#endif
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
return 0;
}
int checkboard(void)
{
puts("Board: s32v234evb\n");
return 0;
}

28
board/freescale/s32v234evb/s32v234evb.cfg
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@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2013-2015, Freescale Semiconductor, Inc.
*/
/*
* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#include <asm/mach-imx/imximage.cfg>
/* image version */
IMAGE_VERSION 2
BOOT_FROM sd
/*
* Boot Device : one of qspi, sd:
* qspi: flash_offset: 0x1000
* sd/mmc: flash_offset: 0x1000
*/
#ifdef CONFIG_IMX_HAB
SECURE_BOOT
#endif

25
configs/s32v234evb_defconfig
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@ -1,25 +0,0 @@
CONFIG_ARM=y
CONFIG_TARGET_S32V234EVB=y
CONFIG_SYS_TEXT_BASE=0x3E800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc7c00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/s32v234evb/s32v234evb.cfg"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyLF0 root=/dev/ram rw"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LINFLEXUART=y
CONFIG_OF_LIBFDT=y

2
drivers/mmc/Kconfig
View File

@ -804,7 +804,7 @@ config FSL_ESDHC_IMX
config FSL_USDHC config FSL_USDHC
bool "Freescale/NXP i.MX uSDHC controller support" bool "Freescale/NXP i.MX uSDHC controller support"
depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMXRT || TARGET_S32V234EVB depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMXRT
select FSL_ESDHC_IMX select FSL_ESDHC_IMX
help help
This enables the Ultra Secured Digital Host Controller enhancements This enables the Ultra Secured Digital Host Controller enhancements

167
include/configs/s32v234evb.h
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@ -1,167 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015-2016 Freescale Semiconductor, Inc.
*
* Configuration settings for the Freescale S32V234 EVB board.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/imx-regs.h>
#define CONFIG_S32V234
/* Config GIC */
#define CONFIG_GICV2
#define GICD_BASE 0x7D001000
#define GICC_BASE 0x7D002000
#define CONFIG_REMAKE_ELF
#undef CONFIG_RUN_FROM_IRAM_ONLY
#define CONFIG_RUN_FROM_DDR1
#undef CONFIG_RUN_FROM_DDR0
/* Run by default from DDR1 */
#ifdef CONFIG_RUN_FROM_DDR0
#define DDR_BASE_ADDR 0x80000000
#else
#define DDR_BASE_ADDR 0xC0000000
#endif
#define CONFIG_MACH_TYPE 4146
#define CONFIG_SKIP_LOWLEVEL_INIT
/* Enable passing of ATAGs */
#define CONFIG_CMDLINE_TAG
/* SMP Spin Table Definitions */
#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY (1000000000) /* 1000MHz */
#define CONFIG_SYS_FSL_ERRATUM_A008585
/* Size of malloc() pool */
#ifdef CONFIG_RUN_FROM_IRAM_ONLY
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1 * 1024 * 1024)
#else
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#endif
#define LINFLEXUART_BASE LINFLEXD0_BASE_ADDR
#define CONFIG_DEBUG_UART_LINFLEXUART
#define CONFIG_DEBUG_UART_BASE LINFLEXUART_BASE
#define CONFIG_SYS_UART_PORT (1)
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_NUM 1
#if 0
/* Ethernet config */
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_FEC_MXC_PHYADDR 0
#endif
#if 0 /* Disable until the FLASH will be implemented */
#define CONFIG_SYS_USE_NAND
#endif
#ifdef CONFIG_SYS_USE_NAND
/* Nand Flash Configs */
#define CONFIG_JFFS2_NAND
#define MTD_NAND_FSL_NFC_SWECC 1
#define CONFIG_NAND_FSL_NFC
#define CONFIG_SYS_NAND_BASE 0x400E0000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_SYS_NAND_SELECT_DEVICE
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
#define CONFIG_LOADADDR 0xC307FFC0
#define CONFIG_EXTRA_ENV_SETTINGS \
"boot_scripts=boot.scr.uimg boot.scr\0" \
"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
"console=ttyLF0,115200\0" \
"fdt_file=s32v234-evb.dtb\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdt_addr_r=0xC2000000\0" \
"kernel_addr_r=0xC307FFC0\0" \
"ramdisk_addr_r=0xC4000000\0" \
"ramdisk=rootfs.uimg\0"\
"ip_dyn=yes\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"update_sd_firmware_filename=u-boot.imx\0" \
"update_sd_firmware=" \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"if mmc dev ${mmcdev}; then " \
"if ${get_cmd} ${update_sd_firmware_filename}; then " \
"setexpr fw_sz ${filesize} / 0x200; " \
"setexpr fw_sz ${fw_sz} + 1; " \
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
"fi; " \
"fi\0" \
"loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr} ${ramdisk}\0" \
"jtagboot=echo Booting using jtag...; " \
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
"jtagsdboot=echo Booting loading Linux with ramdisk from SD...; " \
"run loaduimage; run loadramdisk; run loadfdt;"\
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
"boot_net_usb_start=true\0" \
BOOTENV
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
func(DHCP, dhcp, na)
#define CONFIG_BOOTCOMMAND \
"run distro_bootcmd"
#include <config_distro_bootcmd.h>
#include <linux/stringify.h>
/* Miscellaneous configurable options */
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
#ifdef CONFIG_RUN_FROM_IRAM_ONLY
#define CONFIG_SYS_MALLOC_BASE (DDR_BASE_ADDR)
#endif
/* Physical memory map */
/* EVB board has 2x256 MB DDR chips, DDR0 and DDR1, u-boot is using just one */
#define PHYS_SDRAM (DDR_BASE_ADDR)
#define PHYS_SDRAM_SIZE (256 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* environment organization */
#define CONFIG_BOOTP_BOOTFILESIZE
#endif