mirror of
https://github.com/brain-hackers/u-boot-brain
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sun6i: Add dram initialization code
Add full support for dram initialization, using a fixed clock and autodetection of the memory organization (numbers of channels, bus-width, etc.). This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK, extended with extra initialization sequences and the autodetect algorithm from boot0. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
This commit is contained in:
Hans de Goede
parent
bec72c7994
commit
9a07eb0ba0
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@ -30,6 +30,7 @@ endif
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ifdef CONFIG_SPL_BUILD
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obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o
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obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
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obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
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obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
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ifdef CONFIG_SPL_FEL
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obj-y += start.o
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435
arch/arm/cpu/armv7/sunxi/dram_sun6i.c
Normal file
435
arch/arm/cpu/armv7/sunxi/dram_sun6i.c
Normal file
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@ -0,0 +1,435 @@
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/*
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* Sun6i platform dram controller init.
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*
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* (C) Copyright 2007-2012
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Berg Xing <bergxing@allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/prcm.h>
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/* DRAM clk & zq defaults, maybe turn these into Kconfig options ? */
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#define DRAM_CLK_DEFAULT 312000000
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#define DRAM_ZQ_DEFAULT 0x78
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struct dram_sun6i_para {
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u8 bus_width;
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u8 chan;
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u8 rank;
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u8 rows;
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u16 page_size;
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};
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/*
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* Wait up to 1s for value to be set in given part of reg.
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*/
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static void await_completion(u32 *reg, u32 mask, u32 val)
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{
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unsigned long tmo = timer_get_us() + 1000000;
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while ((readl(reg) & mask) != val) {
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if (timer_get_us() > tmo)
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panic("Timeout initialising DRAM\n");
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}
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}
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static void mctl_sys_init(void)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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const int dram_clk_div = 2;
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clock_set_pll5(DRAM_CLK_DEFAULT * dram_clk_div);
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clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK,
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CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST |
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CCM_DRAMCLK_CFG_UPD);
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await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
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writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg);
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/* deassert mctl reset */
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setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
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/* enable mctl clock */
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setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
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}
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static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para)
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{
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struct sunxi_mctl_phy_reg *mctl_phy;
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if (ch_index == 0)
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mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
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else
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mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
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/* disable + reset dlls */
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writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr);
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writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr);
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writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr);
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if (para->bus_width == 32) {
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writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr);
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writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr);
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}
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udelay(2);
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/* enable + reset dlls */
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writel(0, &mctl_phy->acdllcr);
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writel(0, &mctl_phy->dx0dllcr);
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writel(0, &mctl_phy->dx1dllcr);
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if (para->bus_width == 32) {
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writel(0, &mctl_phy->dx2dllcr);
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writel(0, &mctl_phy->dx3dllcr);
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}
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udelay(22);
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/* enable and release reset of dlls */
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writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr);
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writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr);
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writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr);
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if (para->bus_width == 32) {
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writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr);
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writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr);
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}
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udelay(22);
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}
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static bool mctl_rank_detect(u32 *gsr0, int rank)
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{
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const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank;
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const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank;
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await_completion(gsr0, done, done);
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await_completion(gsr0 + 0x10, done, done);
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return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) & err);
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}
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static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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struct sunxi_mctl_ctl_reg *mctl_ctl;
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struct sunxi_mctl_phy_reg *mctl_phy;
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if (ch_index == 0) {
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mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
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} else {
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mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE;
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mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
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}
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writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd);
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await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0);
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/* PHY initialization */
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writel(MCTL_PGCR, &mctl_phy->pgcr);
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writel(MCTL_MR0, &mctl_phy->mr0);
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writel(MCTL_MR1, &mctl_phy->mr1);
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writel(MCTL_MR2, &mctl_phy->mr2);
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writel(MCTL_MR3, &mctl_phy->mr3);
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writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST,
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&mctl_phy->ptr0);
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/* Unknown magic performed by boot0 */
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if ((readl(SUNXI_RTC_BASE + 0x20c) & 3) == 2)
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setbits_le32(&mctl_phy->ptr0, 1 << 18);
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writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1);
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writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2);
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writel((MCTL_TCCD << 31) | (MCTL_TRC << 25) | (MCTL_TRRD << 21) |
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(MCTL_TRAS << 16) | (MCTL_TRCD << 12) | (MCTL_TRP << 8) |
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(MCTL_TWTR << 5) | (MCTL_TRTP << 2) | (MCTL_TMRD << 0),
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&mctl_phy->dtpr0);
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writel((MCTL_TDQSCKMAX << 27) | (MCTL_TDQSCK << 24) |
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(MCTL_TRFC << 16) | (MCTL_TRTODT << 11) |
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((MCTL_TMOD - 12) << 9) | (MCTL_TFAW << 3) | (0 << 2) |
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(MCTL_TAOND << 0), &mctl_phy->dtpr1);
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writel((MCTL_TDLLK << 19) | (MCTL_TCKE << 15) | (MCTL_TXPDLL << 10) |
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(MCTL_TEXSR << 0), &mctl_phy->dtpr2);
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writel(1, &mctl_ctl->dfitphyupdtype0);
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writel(MCTL_DCR_DDR3, &mctl_phy->dcr);
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writel(MCTL_DSGCR, &mctl_phy->dsgcr);
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writel(MCTL_DXCCR, &mctl_phy->dxccr);
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writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr);
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writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr);
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writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr);
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writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr);
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await_completion(&mctl_phy->pgsr, 0x03, 0x03);
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writel(DRAM_ZQ_DEFAULT, &mctl_phy->zq0cr1);
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setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
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writel(MCTL_PIR_STEP1, &mctl_phy->pir);
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udelay(10);
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await_completion(&mctl_phy->pgsr, 0x1f, 0x1f);
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/* rank detect */
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if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) {
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para->rank = 1;
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clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK);
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}
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/*
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* channel detect, check channel 1 dx0 and dx1 have rank 0, if not
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* assume nothing is connected to channel 1.
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*/
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if (ch_index == 1 && !mctl_rank_detect(&mctl_phy->dx0gsr0, 0)) {
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para->chan = 1;
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clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
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return;
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}
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/* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */
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if (!mctl_rank_detect(&mctl_phy->dx2gsr0, 0)) {
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para->bus_width = 16;
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para->page_size = 2048;
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setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE);
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setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE);
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clrbits_le32(&mctl_phy->dx2gcr, MCTL_DX_GCR_EN);
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clrbits_le32(&mctl_phy->dx3gcr, MCTL_DX_GCR_EN);
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}
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setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
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writel(MCTL_PIR_STEP2, &mctl_phy->pir);
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udelay(10);
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await_completion(&mctl_phy->pgsr, 0x11, 0x11);
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if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK)
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panic("Training error initialising DRAM\n");
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/* Move to configure state */
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writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl);
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await_completion(&mctl_ctl->sstat, 0x07, 0x01);
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/* Set number of clks per micro-second */
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writel(DRAM_CLK_DEFAULT / 1000000, &mctl_ctl->togcnt1u);
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/* Set number of clks per 100 nano-seconds */
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writel(DRAM_CLK_DEFAULT / 10000000, &mctl_ctl->togcnt100n);
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/* Set memory timing registers */
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writel(MCTL_TREFI, &mctl_ctl->trefi);
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writel(MCTL_TMRD, &mctl_ctl->tmrd);
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writel(MCTL_TRFC, &mctl_ctl->trfc);
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writel((MCTL_TPREA << 16) | MCTL_TRP, &mctl_ctl->trp);
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writel(MCTL_TRTW, &mctl_ctl->trtw);
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writel(MCTL_TAL, &mctl_ctl->tal);
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writel(MCTL_TCL, &mctl_ctl->tcl);
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writel(MCTL_TCWL, &mctl_ctl->tcwl);
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writel(MCTL_TRAS, &mctl_ctl->tras);
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writel(MCTL_TRC, &mctl_ctl->trc);
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writel(MCTL_TRCD, &mctl_ctl->trcd);
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writel(MCTL_TRRD, &mctl_ctl->trrd);
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writel(MCTL_TRTP, &mctl_ctl->trtp);
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writel(MCTL_TWR, &mctl_ctl->twr);
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writel(MCTL_TWTR, &mctl_ctl->twtr);
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writel(MCTL_TEXSR, &mctl_ctl->texsr);
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writel(MCTL_TXP, &mctl_ctl->txp);
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writel(MCTL_TXPDLL, &mctl_ctl->txpdll);
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writel(MCTL_TZQCS, &mctl_ctl->tzqcs);
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writel(MCTL_TZQCSI, &mctl_ctl->tzqcsi);
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writel(MCTL_TDQS, &mctl_ctl->tdqs);
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writel(MCTL_TCKSRE, &mctl_ctl->tcksre);
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writel(MCTL_TCKSRX, &mctl_ctl->tcksrx);
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writel(MCTL_TCKE, &mctl_ctl->tcke);
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writel(MCTL_TMOD, &mctl_ctl->tmod);
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writel(MCTL_TRSTL, &mctl_ctl->trstl);
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writel(MCTL_TZQCL, &mctl_ctl->tzqcl);
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writel(MCTL_TMRR, &mctl_ctl->tmrr);
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writel(MCTL_TCKESR, &mctl_ctl->tckesr);
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writel(MCTL_TDPD, &mctl_ctl->tdpd);
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/* Unknown magic performed by boot0 */
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setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3);
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clrbits_le32(&mctl_ctl->dfiodtcfg1, 0x1f);
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/* Select 16/32-bits mode for MCTL */
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if (para->bus_width == 16)
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setbits_le32(&mctl_ctl->ppcfg, 1);
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/* Set DFI timing registers */
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writel(MCTL_TCWL, &mctl_ctl->dfitphywrl);
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writel(MCTL_TCL - 1, &mctl_ctl->dfitrdden);
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writel(MCTL_DFITPHYRDL, &mctl_ctl->dfitphyrdl);
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writel(MCTL_DFISTCFG0, &mctl_ctl->dfistcfg0);
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writel(MCTL_MCFG_DDR3, &mctl_ctl->mcfg);
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/* DFI update configuration register */
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writel(MCTL_DFIUPDCFG_UPD, &mctl_ctl->dfiupdcfg);
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/* Move to access state */
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writel(MCTL_SCTL_ACCESS, &mctl_ctl->sctl);
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await_completion(&mctl_ctl->sstat, 0x07, 0x03);
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}
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static void mctl_com_init(struct dram_sun6i_para *para)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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struct sunxi_mctl_phy_reg * const mctl_phy1 =
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(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
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struct sunxi_prcm_reg * const prcm =
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(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
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writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 |
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((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) |
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MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
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MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr);
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/* Unknown magic performed by boot0 */
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setbits_le32(&mctl_com->dbgcr, (1 << 6));
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if (para->chan == 1) {
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/* Shutdown channel 1 */
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setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE);
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setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE);
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clrbits_le32(&mctl_phy1->dsgcr, MCTL_DSGCR_ENABLE);
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/*
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* CH0 ?? this is what boot0 does. Leave as is until we can
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* confirm this.
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*/
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setbits_le32(&prcm->vdd_sys_pwroff,
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PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF);
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}
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}
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static void mctl_port_cfg(void)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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/* enable DRAM AXI clock for CPU access */
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setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM);
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/* Bunch of magic writes performed by boot0 */
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writel(0x00400302, &mctl_com->rmcr[0]);
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writel(0x01000307, &mctl_com->rmcr[1]);
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writel(0x00400302, &mctl_com->rmcr[2]);
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writel(0x01000307, &mctl_com->rmcr[3]);
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writel(0x01000307, &mctl_com->rmcr[4]);
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writel(0x01000303, &mctl_com->rmcr[6]);
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writel(0x01000303, &mctl_com->mmcr[0]);
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writel(0x00400310, &mctl_com->mmcr[1]);
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writel(0x01000307, &mctl_com->mmcr[2]);
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writel(0x01000303, &mctl_com->mmcr[3]);
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writel(0x01800303, &mctl_com->mmcr[4]);
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writel(0x01800303, &mctl_com->mmcr[5]);
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writel(0x01800303, &mctl_com->mmcr[6]);
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writel(0x01800303, &mctl_com->mmcr[7]);
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writel(0x01000303, &mctl_com->mmcr[8]);
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writel(0x00000002, &mctl_com->mmcr[15]);
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writel(0x00000310, &mctl_com->mbagcr[0]);
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writel(0x00400310, &mctl_com->mbagcr[1]);
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writel(0x00400310, &mctl_com->mbagcr[2]);
|
||||
writel(0x00000307, &mctl_com->mbagcr[3]);
|
||||
writel(0x00000317, &mctl_com->mbagcr[4]);
|
||||
writel(0x00000307, &mctl_com->mbagcr[5]);
|
||||
}
|
||||
|
||||
static bool mctl_mem_matches(u32 offset)
|
||||
{
|
||||
const int match_count = 64;
|
||||
int i, matches = 0;
|
||||
|
||||
for (i = 0; i < match_count; i++) {
|
||||
if (readl(CONFIG_SYS_SDRAM_BASE + i * 4) ==
|
||||
readl(CONFIG_SYS_SDRAM_BASE + offset + i * 4))
|
||||
matches++;
|
||||
}
|
||||
|
||||
return matches == match_count;
|
||||
}
|
||||
|
||||
unsigned long sunxi_dram_init(void)
|
||||
{
|
||||
struct sunxi_mctl_com_reg * const mctl_com =
|
||||
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
|
||||
u32 offset;
|
||||
int bank, bus, columns;
|
||||
|
||||
/* Set initial parameters, these get modified by the autodetect code */
|
||||
struct dram_sun6i_para para = {
|
||||
.bus_width = 32,
|
||||
.chan = 2,
|
||||
.rank = 2,
|
||||
.page_size = 4096,
|
||||
.rows = 16,
|
||||
};
|
||||
|
||||
mctl_sys_init();
|
||||
|
||||
mctl_dll_init(0, ¶);
|
||||
mctl_dll_init(1, ¶);
|
||||
|
||||
setbits_le32(&mctl_com->ccr,
|
||||
MCTL_CCR_MASTER_CLK_EN |
|
||||
MCTL_CCR_CH0_CLK_EN |
|
||||
MCTL_CCR_CH1_CLK_EN);
|
||||
|
||||
mctl_channel_init(0, ¶);
|
||||
mctl_channel_init(1, ¶);
|
||||
mctl_com_init(¶);
|
||||
mctl_port_cfg();
|
||||
|
||||
/*
|
||||
* Change to 1 ch / sequence / 8192 byte pages / 16 rows /
|
||||
* 8 bit banks / 1 rank mode.
|
||||
*/
|
||||
clrsetbits_le32(&mctl_com->cr,
|
||||
MCTL_CR_CHANNEL_MASK | MCTL_CR_PAGE_SIZE_MASK |
|
||||
MCTL_CR_ROW_MASK | MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
|
||||
MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE |
|
||||
MCTL_CR_PAGE_SIZE(8192) | MCTL_CR_ROW(16) |
|
||||
MCTL_CR_BANK(1) | MCTL_CR_RANK(1));
|
||||
|
||||
/* Detect and set page size */
|
||||
for (columns = 7; columns < 20; columns++) {
|
||||
if (mctl_mem_matches(1 << columns))
|
||||
break;
|
||||
}
|
||||
bus = (para.bus_width == 32) ? 2 : 1;
|
||||
columns -= bus;
|
||||
para.page_size = (1 << columns) * (bus << 1);
|
||||
clrsetbits_le32(&mctl_com->cr, MCTL_CR_PAGE_SIZE_MASK,
|
||||
MCTL_CR_PAGE_SIZE(para.page_size));
|
||||
|
||||
/* Detect and set rows */
|
||||
for (para.rows = 11; para.rows < 16; para.rows++) {
|
||||
offset = 1 << (para.rows + columns + bus);
|
||||
if (mctl_mem_matches(offset))
|
||||
break;
|
||||
}
|
||||
clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
|
||||
MCTL_CR_ROW(para.rows));
|
||||
|
||||
/* Detect bank size */
|
||||
offset = 1 << (para.rows + columns + bus + 2);
|
||||
bank = mctl_mem_matches(offset) ? 0 : 1;
|
||||
|
||||
/* Restore interleave, chan and rank values, set bank size */
|
||||
clrsetbits_le32(&mctl_com->cr,
|
||||
MCTL_CR_CHANNEL_MASK | MCTL_CR_SEQUENCE |
|
||||
MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
|
||||
MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) |
|
||||
MCTL_CR_RANK(para.rank));
|
||||
|
||||
return 1 << (para.rank + para.rows + bank + columns + para.chan + bus);
|
||||
}
|
||||
|
|
@ -96,9 +96,10 @@
|
|||
#define SUNXI_GMAC_BASE 0x01c50000
|
||||
|
||||
#define SUNXI_DRAM_COM_BASE 0x01c62000
|
||||
#define SUNXI_DRAM_CTL_BASE 0x01c63000
|
||||
#define SUNXI_DRAM_PHY_CH1_BASE 0x01c65000
|
||||
#define SUNXI_DRAM_PHY_CH2_BASE 0x01c66000
|
||||
#define SUNXI_DRAM_CTL0_BASE 0x01c63000
|
||||
#define SUNXI_DRAM_CTL1_BASE 0x01c64000
|
||||
#define SUNXI_DRAM_PHY0_BASE 0x01c65000
|
||||
#define SUNXI_DRAM_PHY1_BASE 0x01c66000
|
||||
|
||||
/* module sram */
|
||||
#define SUNXI_SRAM_C_BASE 0x01d00000
|
||||
|
|
@ -110,6 +111,7 @@
|
|||
#define SUNXI_MP_BASE 0x01e80000
|
||||
#define SUNXI_AVG_BASE 0x01ea0000
|
||||
|
||||
#define SUNXI_RTC_BASE 0x01f00000
|
||||
#define SUNXI_PRCM_BASE 0x01f01400
|
||||
#define SUN6I_CPUCFG_BASE 0x01f01c00
|
||||
#define SUNXI_R_UART_BASE 0x01f02800
|
||||
|
|
|
|||
|
|
@ -15,7 +15,11 @@
|
|||
#include <linux/types.h>
|
||||
|
||||
/* dram regs definition */
|
||||
#if defined(CONFIG_MACH_SUN6I)
|
||||
#include <asm/arch/dram_sun6i.h>
|
||||
#else
|
||||
#include <asm/arch/dram_sun4i.h>
|
||||
#endif
|
||||
|
||||
unsigned long sunxi_dram_init(void);
|
||||
|
||||
|
|
|
|||
359
arch/arm/include/asm/arch-sunxi/dram_sun6i.h
Normal file
359
arch/arm/include/asm/arch-sunxi/dram_sun6i.h
Normal file
|
|
@ -0,0 +1,359 @@
|
|||
/*
|
||||
* Sun6i platform dram controller register and constant defines
|
||||
*
|
||||
* (C) Copyright 2007-2012
|
||||
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
|
||||
* Berg Xing <bergxing@allwinnertech.com>
|
||||
* Tom Cubie <tangliang@allwinnertech.com>
|
||||
*
|
||||
* (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _SUNXI_DRAM_SUN6I_H
|
||||
#define _SUNXI_DRAM_SUN6I_H
|
||||
|
||||
struct sunxi_mctl_com_reg {
|
||||
u32 cr; /* 0x00 */
|
||||
u32 ccr; /* 0x04 controller configuration register */
|
||||
u32 dbgcr; /* 0x08 */
|
||||
u32 dbgcr1; /* 0x0c */
|
||||
u32 rmcr[8]; /* 0x10 */
|
||||
u32 mmcr[16]; /* 0x30 */
|
||||
u32 mbagcr[6]; /* 0x70 */
|
||||
u32 maer; /* 0x88 */
|
||||
u8 res0[0x14]; /* 0x8c */
|
||||
u32 mdfscr; /* 0x100 */
|
||||
u32 mdfsmer; /* 0x104 */
|
||||
u32 mdfsmrmr; /* 0x108 */
|
||||
u32 mdfstr0; /* 0x10c */
|
||||
u32 mdfstr1; /* 0x110 */
|
||||
u32 mdfstr2; /* 0x114 */
|
||||
u32 mdfstr3; /* 0x118 */
|
||||
u32 mdfsgcr; /* 0x11c */
|
||||
u8 res1[0x1c]; /* 0x120 */
|
||||
u32 mdfsivr; /* 0x13c */
|
||||
u8 res2[0x0c]; /* 0x140 */
|
||||
u32 mdfstcr; /* 0x14c */
|
||||
};
|
||||
|
||||
struct sunxi_mctl_ctl_reg {
|
||||
u8 res0[0x04]; /* 0x00 */
|
||||
u32 sctl; /* 0x04 */
|
||||
u32 sstat; /* 0x08 */
|
||||
u8 res1[0x34]; /* 0x0c */
|
||||
u32 mcmd; /* 0x40 */
|
||||
u8 res2[0x08]; /* 0x44 */
|
||||
u32 cmdstat; /* 0x4c */
|
||||
u32 cmdstaten; /* 0x50 */
|
||||
u8 res3[0x0c]; /* 0x54 */
|
||||
u32 mrrcfg0; /* 0x60 */
|
||||
u32 mrrstat0; /* 0x64 */
|
||||
u32 mrrstat1; /* 0x68 */
|
||||
u8 res4[0x10]; /* 0x6c */
|
||||
u32 mcfg1; /* 0x7c */
|
||||
u32 mcfg; /* 0x80 */
|
||||
u32 ppcfg; /* 0x84 */
|
||||
u32 mstat; /* 0x88 */
|
||||
u32 lp2zqcfg; /* 0x8c */
|
||||
u8 res5[0x04]; /* 0x90 */
|
||||
u32 dtustat; /* 0x94 */
|
||||
u32 dtuna; /* 0x98 */
|
||||
u32 dtune; /* 0x9c */
|
||||
u32 dtuprd0; /* 0xa0 */
|
||||
u32 dtuprd1; /* 0xa4 */
|
||||
u32 dtuprd2; /* 0xa8 */
|
||||
u32 dtuprd3; /* 0xac */
|
||||
u32 dtuawdt; /* 0xb0 */
|
||||
u8 res6[0x0c]; /* 0xb4 */
|
||||
u32 togcnt1u; /* 0xc0 */
|
||||
u8 res7[0x08]; /* 0xc4 */
|
||||
u32 togcnt100n; /* 0xcc */
|
||||
u32 trefi; /* 0xd0 */
|
||||
u32 tmrd; /* 0xd4 */
|
||||
u32 trfc; /* 0xd8 */
|
||||
u32 trp; /* 0xdc */
|
||||
u32 trtw; /* 0xe0 */
|
||||
u32 tal; /* 0xe4 */
|
||||
u32 tcl; /* 0xe8 */
|
||||
u32 tcwl; /* 0xec */
|
||||
u32 tras; /* 0xf0 */
|
||||
u32 trc; /* 0xf4 */
|
||||
u32 trcd; /* 0xf8 */
|
||||
u32 trrd; /* 0xfc */
|
||||
u32 trtp; /* 0x100 */
|
||||
u32 twr; /* 0x104 */
|
||||
u32 twtr; /* 0x108 */
|
||||
u32 texsr; /* 0x10c */
|
||||
u32 txp; /* 0x110 */
|
||||
u32 txpdll; /* 0x114 */
|
||||
u32 tzqcs; /* 0x118 */
|
||||
u32 tzqcsi; /* 0x11c */
|
||||
u32 tdqs; /* 0x120 */
|
||||
u32 tcksre; /* 0x124 */
|
||||
u32 tcksrx; /* 0x128 */
|
||||
u32 tcke; /* 0x12c */
|
||||
u32 tmod; /* 0x130 */
|
||||
u32 trstl; /* 0x134 */
|
||||
u32 tzqcl; /* 0x138 */
|
||||
u32 tmrr; /* 0x13c */
|
||||
u32 tckesr; /* 0x140 */
|
||||
u32 tdpd; /* 0x144 */
|
||||
u8 res8[0xb8]; /* 0x148 */
|
||||
u32 dtuwactl; /* 0x200 */
|
||||
u32 dturactl; /* 0x204 */
|
||||
u32 dtucfg; /* 0x208 */
|
||||
u32 dtuectl; /* 0x20c */
|
||||
u32 dtuwd0; /* 0x210 */
|
||||
u32 dtuwd1; /* 0x214 */
|
||||
u32 dtuwd2; /* 0x218 */
|
||||
u32 dtuwd3; /* 0x21c */
|
||||
u32 dtuwdm; /* 0x220 */
|
||||
u32 dturd0; /* 0x224 */
|
||||
u32 dturd1; /* 0x228 */
|
||||
u32 dturd2; /* 0x22c */
|
||||
u32 dturd3; /* 0x230 */
|
||||
u32 dtulfsrwd; /* 0x234 */
|
||||
u32 dtulfsrrd; /* 0x238 */
|
||||
u32 dtueaf; /* 0x23c */
|
||||
u32 dfitctldly; /* 0x240 */
|
||||
u32 dfiodtcfg; /* 0x244 */
|
||||
u32 dfiodtcfg1; /* 0x248 */
|
||||
u32 dfiodtrmap; /* 0x24c */
|
||||
u32 dfitphywrd; /* 0x250 */
|
||||
u32 dfitphywrl; /* 0x254 */
|
||||
u8 res9[0x08]; /* 0x258 */
|
||||
u32 dfitrdden; /* 0x260 */
|
||||
u32 dfitphyrdl; /* 0x264 */
|
||||
u8 res10[0x08]; /* 0x268 */
|
||||
u32 dfitphyupdtype0; /* 0x270 */
|
||||
u32 dfitphyupdtype1; /* 0x274 */
|
||||
u32 dfitphyupdtype2; /* 0x278 */
|
||||
u32 dfitphyupdtype3; /* 0x27c */
|
||||
u32 dfitctrlupdmin; /* 0x280 */
|
||||
u32 dfitctrlupdmax; /* 0x284 */
|
||||
u32 dfitctrlupddly; /* 0x288 */
|
||||
u8 res11[4]; /* 0x28c */
|
||||
u32 dfiupdcfg; /* 0x290 */
|
||||
u32 dfitrefmski; /* 0x294 */
|
||||
u32 dfitcrlupdi; /* 0x298 */
|
||||
u8 res12[0x10]; /* 0x29c */
|
||||
u32 dfitrcfg0; /* 0x2ac */
|
||||
u32 dfitrstat0; /* 0x2b0 */
|
||||
u32 dfitrwrlvlen; /* 0x2b4 */
|
||||
u32 dfitrrdlvlen; /* 0x2b8 */
|
||||
u32 dfitrrdlvlgateen; /* 0x2bc */
|
||||
u8 res13[0x04]; /* 0x2c0 */
|
||||
u32 dfistcfg0; /* 0x2c4 */
|
||||
u32 dfistcfg1; /* 0x2c8 */
|
||||
u8 res14[0x04]; /* 0x2cc */
|
||||
u32 dfitdramclken; /* 0x2d0 */
|
||||
u32 dfitdramclkdis; /* 0x2d4 */
|
||||
u8 res15[0x18]; /* 0x2d8 */
|
||||
u32 dfilpcfg0; /* 0x2f0 */
|
||||
};
|
||||
|
||||
struct sunxi_mctl_phy_reg {
|
||||
u8 res0[0x04]; /* 0x00 */
|
||||
u32 pir; /* 0x04 */
|
||||
u32 pgcr; /* 0x08 phy general configuration register */
|
||||
u32 pgsr; /* 0x0c */
|
||||
u32 dllgcr; /* 0x10 */
|
||||
u32 acdllcr; /* 0x14 */
|
||||
u32 ptr0; /* 0x18 */
|
||||
u32 ptr1; /* 0x1c */
|
||||
u32 ptr2; /* 0x20 */
|
||||
u32 aciocr; /* 0x24 */
|
||||
u32 dxccr; /* 0x28 DATX8 common configuration register */
|
||||
u32 dsgcr; /* 0x2c dram system general config register */
|
||||
u32 dcr; /* 0x30 */
|
||||
u32 dtpr0; /* 0x34 dram timing parameters register 0 */
|
||||
u32 dtpr1; /* 0x38 dram timing parameters register 1 */
|
||||
u32 dtpr2; /* 0x3c dram timing parameters register 2 */
|
||||
u32 mr0; /* 0x40 mode register 0 */
|
||||
u32 mr1; /* 0x44 mode register 1 */
|
||||
u32 mr2; /* 0x48 mode register 2 */
|
||||
u32 mr3; /* 0x4c mode register 3 */
|
||||
u32 odtcr; /* 0x50 */
|
||||
u32 dtar; /* 0x54 data training address register */
|
||||
u32 dtd0; /* 0x58 */
|
||||
u32 dtd1; /* 0x5c */
|
||||
u8 res1[0x60]; /* 0x60 */
|
||||
u32 dcuar; /* 0xc0 */
|
||||
u32 dcudr; /* 0xc4 */
|
||||
u32 dcurr; /* 0xc8 */
|
||||
u32 dculr; /* 0xcc */
|
||||
u32 dcugcr; /* 0xd0 */
|
||||
u32 dcutpr; /* 0xd4 */
|
||||
u32 dcusr0; /* 0xd8 */
|
||||
u32 dcusr1; /* 0xdc */
|
||||
u8 res2[0x20]; /* 0xe0 */
|
||||
u32 bistrr; /* 0x100 */
|
||||
u32 bistmskr0; /* 0x104 */
|
||||
u32 bistmskr1; /* 0x108 */
|
||||
u32 bistwcr; /* 0x10c */
|
||||
u32 bistlsr; /* 0x110 */
|
||||
u32 bistar0; /* 0x114 */
|
||||
u32 bistar1; /* 0x118 */
|
||||
u32 bistar2; /* 0x11c */
|
||||
u32 bistupdr; /* 0x120 */
|
||||
u32 bistgsr; /* 0x124 */
|
||||
u32 bistwer; /* 0x128 */
|
||||
u32 bistber0; /* 0x12c */
|
||||
u32 bistber1; /* 0x130 */
|
||||
u32 bistber2; /* 0x134 */
|
||||
u32 bistwcsr; /* 0x138 */
|
||||
u32 bistfwr0; /* 0x13c */
|
||||
u32 bistfwr1; /* 0x140 */
|
||||
u8 res3[0x3c]; /* 0x144 */
|
||||
u32 zq0cr0; /* 0x180 zq 0 control register 0 */
|
||||
u32 zq0cr1; /* 0x184 zq 0 control register 1 */
|
||||
u32 zq0sr0; /* 0x188 zq 0 status register 0 */
|
||||
u32 zq0sr1; /* 0x18c zq 0 status register 1 */
|
||||
u8 res4[0x30]; /* 0x190 */
|
||||
u32 dx0gcr; /* 0x1c0 */
|
||||
u32 dx0gsr0; /* 0x1c4 */
|
||||
u32 dx0gsr1; /* 0x1c8 */
|
||||
u32 dx0dllcr; /* 0x1cc */
|
||||
u32 dx0dqtr; /* 0x1d0 */
|
||||
u32 dx0dqstr; /* 0x1d4 */
|
||||
u8 res5[0x28]; /* 0x1d8 */
|
||||
u32 dx1gcr; /* 0x200 */
|
||||
u32 dx1gsr0; /* 0x204 */
|
||||
u32 dx1gsr1; /* 0x208 */
|
||||
u32 dx1dllcr; /* 0x20c */
|
||||
u32 dx1dqtr; /* 0x210 */
|
||||
u32 dx1dqstr; /* 0x214 */
|
||||
u8 res6[0x28]; /* 0x218 */
|
||||
u32 dx2gcr; /* 0x240 */
|
||||
u32 dx2gsr0; /* 0x244 */
|
||||
u32 dx2gsr1; /* 0x248 */
|
||||
u32 dx2dllcr; /* 0x24c */
|
||||
u32 dx2dqtr; /* 0x250 */
|
||||
u32 dx2dqstr; /* 0x254 */
|
||||
u8 res7[0x28]; /* 0x258 */
|
||||
u32 dx3gcr; /* 0x280 */
|
||||
u32 dx3gsr0; /* 0x284 */
|
||||
u32 dx3gsr1; /* 0x288 */
|
||||
u32 dx3dllcr; /* 0x28c */
|
||||
u32 dx3dqtr; /* 0x290 */
|
||||
u32 dx3dqstr; /* 0x294 */
|
||||
};
|
||||
|
||||
/*
|
||||
* DRAM common (sunxi_mctl_com_reg) register constants.
|
||||
*/
|
||||
#define MCTL_CR_RANK_MASK (3 << 0)
|
||||
#define MCTL_CR_RANK(x) (((x) - 1) << 0)
|
||||
#define MCTL_CR_BANK_MASK (3 << 2)
|
||||
#define MCTL_CR_BANK(x) ((x) << 2)
|
||||
#define MCTL_CR_ROW_MASK (0xf << 4)
|
||||
#define MCTL_CR_ROW(x) (((x) - 1) << 4)
|
||||
#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8)
|
||||
#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8)
|
||||
#define MCTL_CR_BUSW_MASK (3 << 12)
|
||||
#define MCTL_CR_BUSW16 (1 << 12)
|
||||
#define MCTL_CR_BUSW32 (3 << 12)
|
||||
#define MCTL_CR_SEQUENCE (1 << 15)
|
||||
#define MCTL_CR_DDR3 (3 << 16)
|
||||
#define MCTL_CR_CHANNEL_MASK (1 << 19)
|
||||
#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19)
|
||||
#define MCTL_CR_UNKNOWN ((1 << 22) | (1 << 20))
|
||||
#define MCTL_CCR_CH0_CLK_EN (1 << 0)
|
||||
#define MCTL_CCR_CH1_CLK_EN (1 << 1)
|
||||
#define MCTL_CCR_MASTER_CLK_EN (1 << 2)
|
||||
|
||||
/*
|
||||
* DRAM control (sunxi_mctl_ctl_reg) register constants.
|
||||
* Note that we use constant values for a lot of the timings, this is what
|
||||
* the original boot0 bootloader does.
|
||||
*/
|
||||
#define MCTL_SCTL_CONFIG 1
|
||||
#define MCTL_SCTL_ACCESS 2
|
||||
#define MCTL_MCMD_NOP 0x88000000
|
||||
#define MCTL_MCMD_BUSY 0x80000000
|
||||
#define MCTL_MCFG_DDR3 0x70061
|
||||
#define MCTL_TREFI 78
|
||||
#define MCTL_TMRD 4
|
||||
#define MCTL_TRFC 115
|
||||
#define MCTL_TRP 9
|
||||
#define MCTL_TPREA 0
|
||||
#define MCTL_TRTW 2
|
||||
#define MCTL_TAL 0
|
||||
#define MCTL_TCL 9
|
||||
#define MCTL_TCWL 8
|
||||
#define MCTL_TRAS 18
|
||||
#define MCTL_TRC 23
|
||||
#define MCTL_TRCD 9
|
||||
#define MCTL_TRRD 4
|
||||
#define MCTL_TRTP 4
|
||||
#define MCTL_TWR 8
|
||||
#define MCTL_TWTR 4
|
||||
#define MCTL_TEXSR 512
|
||||
#define MCTL_TXP 4
|
||||
#define MCTL_TXPDLL 14
|
||||
#define MCTL_TZQCS 64
|
||||
#define MCTL_TZQCSI 0
|
||||
#define MCTL_TDQS 1
|
||||
#define MCTL_TCKSRE 5
|
||||
#define MCTL_TCKSRX 5
|
||||
#define MCTL_TCKE 4
|
||||
#define MCTL_TMOD 12
|
||||
#define MCTL_TRSTL 80
|
||||
#define MCTL_TZQCL 512
|
||||
#define MCTL_TMRR 2
|
||||
#define MCTL_TCKESR 5
|
||||
#define MCTL_TDPD 0
|
||||
#define MCTL_DFITPHYRDL 15
|
||||
#define MCTL_DFIUPDCFG_UPD (1 << 1)
|
||||
#define MCTL_DFISTCFG0 5
|
||||
|
||||
/*
|
||||
* DRAM phy (sunxi_mctl_phy_reg) register values / constants.
|
||||
*/
|
||||
#define MCTL_PIR_CLEAR_STATUS (1 << 28)
|
||||
#define MCTL_PIR_STEP1 0xe9
|
||||
#define MCTL_PIR_STEP2 0x81
|
||||
#define MCTL_PGCR_RANK (1 << 19)
|
||||
#define MCTL_PGCR 0x018c0202
|
||||
#define MCTL_PGSR_TRAIN_ERR_MASK (3 << 5)
|
||||
/* constants for both acdllcr as well as dx#dllcr */
|
||||
#define MCTL_DLLCR_NRESET (1 << 30)
|
||||
#define MCTL_DLLCR_DISABLE (1 << 31)
|
||||
/* ptr constants these are or-ed together to get the final ptr# values */
|
||||
#define MCTL_TITMSRST 10
|
||||
#define MCTL_TDLLLOCK 2250
|
||||
#define MCTL_TDLLSRST 23
|
||||
#define MCTL_TDINIT0 217000
|
||||
#define MCTL_TDINIT1 160
|
||||
#define MCTL_TDINIT2 87000
|
||||
#define MCTL_TDINIT3 433
|
||||
/* end ptr constants */
|
||||
#define MCTL_ACIOCR_DISABLE ((3 << 18) | (1 << 8) | (1 << 3))
|
||||
#define MCTL_DXCCR_DISABLE ((1 << 3) | (1 << 2))
|
||||
#define MCTL_DXCCR 0x800
|
||||
#define MCTL_DSGCR_ENABLE (1 << 28)
|
||||
#define MCTL_DSGCR 0xf200001b
|
||||
#define MCTL_DCR_DDR3 0x0b
|
||||
/* dtpr constants these are or-ed together to get the final dtpr# values */
|
||||
#define MCTL_TCCD 0
|
||||
#define MCTL_TDQSCKMAX 1
|
||||
#define MCTL_TDQSCK 1
|
||||
#define MCTL_TRTODT 0
|
||||
#define MCTL_TFAW 20
|
||||
#define MCTL_TAOND 0
|
||||
#define MCTL_TDLLK 512
|
||||
/* end dtpr constants */
|
||||
#define MCTL_MR0 0x1a50
|
||||
#define MCTL_MR1 0x4
|
||||
#define MCTL_MR2 ((MCTL_TCWL - 5) << 3)
|
||||
#define MCTL_MR3 0x0
|
||||
#define MCTL_DX_GCR_EN (1 << 0)
|
||||
#define MCTL_DX_GCR 0x880
|
||||
#define MCTL_DX_GSR0_RANK0_TRAIN_DONE (1 << 0)
|
||||
#define MCTL_DX_GSR0_RANK1_TRAIN_DONE (1 << 1)
|
||||
#define MCTL_DX_GSR0_RANK0_TRAIN_ERR (1 << 4)
|
||||
#define MCTL_DX_GSR0_RANK1_TRAIN_ERR (1 << 5)
|
||||
|
||||
#endif /* _SUNXI_DRAM_SUN6I_H */
|
||||
Loading…
Reference in New Issue
Block a user