diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c
index 8912098573..0b1a8f4bbc 100644
--- a/arch/arm/cpu/arm926ejs/mx25/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx25/generic.c
@@ -13,6 +13,7 @@
 #include <div64.h>
 #include <netdev.h>
 #include <asm/io.h>
+#include <asm/arch-imx/cpu.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 
diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c
index e9d8800f8c..9491096424 100644
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -309,7 +309,7 @@ void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
 		bus, tgtclk, freq);
 }
 
-void mxs_set_lcdclk(uint32_t freq)
+void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 0b02e9e778..273e209cbb 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -23,10 +23,12 @@ config MX6SL
 	bool
 
 config MX6SX
+	select ROM_UNIFIED_SECTIONS
 	bool
 
 config MX6UL
 	select SYS_L2CACHE_OFF
+	select ROM_UNIFIED_SECTIONS
 	bool
 
 choice
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index bf6effc939..8af191d660 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -9,5 +9,4 @@
 
 obj-y	:= soc.o clock.o
 obj-$(CONFIG_SPL_BUILD)	     += ddr.o
-obj-$(CONFIG_SECURE_BOOT)    += hab.o
 obj-$(CONFIG_MP)             += mp.o
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 11efd12c9a..67e0f3252f 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -473,6 +473,251 @@ static u32 get_mmdc_ch0_clk(void)
 	}
 }
 
+#if defined(CONFIG_VIDEO_MXS)
+static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
+			    u32 post_div)
+{
+	u32 reg = 0;
+	ulong start;
+
+	debug("pll5 div = %d, num = %d, denom = %d\n",
+	      pll_div, pll_num, pll_denom);
+
+	/* Power up PLL5 video */
+	writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
+	       BM_ANADIG_PLL_VIDEO_BYPASS |
+	       BM_ANADIG_PLL_VIDEO_DIV_SELECT |
+	       BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
+	       &imx_ccm->analog_pll_video_clr);
+
+	/* Set div, num and denom */
+	switch (post_div) {
+	case 1:
+		writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
+		       BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
+		       &imx_ccm->analog_pll_video_set);
+		break;
+	case 2:
+		writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
+		       BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
+		       &imx_ccm->analog_pll_video_set);
+		break;
+	case 4:
+		writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
+		       BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
+		       &imx_ccm->analog_pll_video_set);
+		break;
+	default:
+		puts("Wrong test_div!\n");
+		return -EINVAL;
+	}
+
+	writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
+	       &imx_ccm->analog_pll_video_num);
+	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
+	       &imx_ccm->analog_pll_video_denom);
+
+	/* Wait PLL5 lock */
+	start = get_timer(0);	/* Get current timestamp */
+
+	do {
+		reg = readl(&imx_ccm->analog_pll_video);
+		if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
+			/* Enable PLL out */
+			writel(BM_ANADIG_PLL_VIDEO_ENABLE,
+			       &imx_ccm->analog_pll_video_set);
+			return 0;
+		}
+	} while (get_timer(0) < (start + 10)); /* Wait 10ms */
+
+	puts("Lock PLL5 timeout\n");
+
+	return -ETIME;
+}
+
+/*
+ * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
+ *
+ * 'freq' using KHz as unit, see driver/video/mxsfb.c.
+ */
+void mxs_set_lcdclk(u32 base_addr, u32 freq)
+{
+	u32 reg = 0;
+	u32 hck = MXC_HCLK / 1000;
+	/* DIV_SELECT ranges from 27 to 54 */
+	u32 min = hck * 27;
+	u32 max = hck * 54;
+	u32 temp, best = 0;
+	u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
+	u32 pll_div, pll_num, pll_denom, post_div = 1;
+
+	debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
+
+	if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL)) {
+		debug("This chip not support lcd!\n");
+		return;
+	}
+
+	if (base_addr == LCDIF1_BASE_ADDR) {
+		reg = readl(&imx_ccm->cscdr2);
+		/* Can't change clocks when clock not from pre-mux */
+		if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
+			return;
+	}
+
+	if (is_cpu_type(MXC_CPU_MX6SX)) {
+		reg = readl(&imx_ccm->cscdr2);
+		/* Can't change clocks when clock not from pre-mux */
+		if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
+			return;
+	}
+
+	temp = freq * max_pred * max_postd;
+	if (temp > max) {
+		puts("Please decrease freq, too large!\n");
+		return;
+	}
+	if (temp < min) {
+		/*
+		 * Register: PLL_VIDEO
+		 * Bit Field: POST_DIV_SELECT
+		 * 00 — Divide by 4.
+		 * 01 — Divide by 2.
+		 * 10 — Divide by 1.
+		 * 11 — Reserved
+		 * No need to check post_div(1)
+		 */
+		for (post_div = 2; post_div <= 4; post_div <<= 1) {
+			if ((temp * post_div) > min) {
+				freq *= post_div;
+				break;
+			}
+		}
+
+		if (post_div > 4) {
+			printf("Fail to set rate to %dkhz", freq);
+			return;
+		}
+	}
+
+	/* Choose the best pred and postd to match freq for lcd */
+	for (i = 1; i <= max_pred; i++) {
+		for (j = 1; j <= max_postd; j++) {
+			temp = freq * i * j;
+			if (temp > max || temp < min)
+				continue;
+			if (best == 0 || temp < best) {
+				best = temp;
+				pred = i;
+				postd = j;
+			}
+		}
+	}
+
+	if (best == 0) {
+		printf("Fail to set rate to %dKHz", freq);
+		return;
+	}
+
+	debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
+
+	pll_div = best / hck;
+	pll_denom = 1000000;
+	pll_num = (best - hck * pll_div) * pll_denom / hck;
+
+	/*
+	 *                                  pll_num
+	 *             (24MHz * (pll_div + --------- ))
+	 *                                 pll_denom
+	 *freq KHz =  --------------------------------
+	 *             post_div * pred * postd * 1000
+	 */
+
+	if (base_addr == LCDIF1_BASE_ADDR) {
+		if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
+			return;
+
+		/* Select pre-lcd clock to PLL5 and set pre divider */
+		clrsetbits_le32(&imx_ccm->cscdr2,
+				MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
+				MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
+				(0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
+				((pred - 1) <<
+				 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
+
+		/* Set the post divider */
+		clrsetbits_le32(&imx_ccm->cbcmr,
+				MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
+				((postd - 1) <<
+				 MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
+	} else if (is_cpu_type(MXC_CPU_MX6SX)) {
+		/* Setting LCDIF2 for i.MX6SX */
+		if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
+			return;
+
+		/* Select pre-lcd clock to PLL5 and set pre divider */
+		clrsetbits_le32(&imx_ccm->cscdr2,
+				MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
+				MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
+				(0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
+				((pred - 1) <<
+				 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
+
+		/* Set the post divider */
+		clrsetbits_le32(&imx_ccm->cscmr1,
+				MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
+				((postd - 1) <<
+				 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
+	}
+}
+
+int enable_lcdif_clock(u32 base_addr)
+{
+	u32 reg = 0;
+	u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
+
+	if (is_cpu_type(MXC_CPU_MX6SX)) {
+		if ((base_addr == LCDIF1_BASE_ADDR) ||
+		    (base_addr == LCDIF2_BASE_ADDR)) {
+			puts("Wrong LCD interface!\n");
+			return -EINVAL;
+		}
+		/* Set to pre-mux clock at default */
+		lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
+			MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
+			MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
+		lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
+			(MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
+			 MXC_CCM_CCGR3_DISP_AXI_MASK) :
+			(MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
+			 MXC_CCM_CCGR3_DISP_AXI_MASK);
+	} else if (is_cpu_type(MXC_CPU_MX6UL)) {
+		if (base_addr != LCDIF1_BASE_ADDR) {
+			puts("Wrong LCD interface!\n");
+			return -EINVAL;
+		}
+		/* Set to pre-mux clock at default */
+		lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
+		lcdif_ccgr3_mask =  MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
+	} else {
+		return 0;
+	}
+
+	reg = readl(&imx_ccm->cscdr2);
+	reg &= ~lcdif_clk_sel_mask;
+	writel(reg, &imx_ccm->cscdr2);
+
+	/* Enable the LCDIF pix clock */
+	reg = readl(&imx_ccm->CCGR3);
+	reg |= lcdif_ccgr3_mask;
+	writel(reg, &imx_ccm->CCGR3);
+
+	reg = readl(&imx_ccm->CCGR2);
+	reg |= MXC_CCM_CCGR2_LCD_MASK;
+	writel(reg, &imx_ccm->CCGR2);
+}
+#endif
+
 #ifdef CONFIG_FSL_QSPI
 /* qspi_num can be from 0 - 1 */
 void enable_qspi_clk(int qspi_num)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 282302b1fc..bf5ae8cdff 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -15,6 +15,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/imx-common/boot_mode.h>
 #include <asm/imx-common/dma.h>
+#include <asm/imx-common/hab.h>
 #include <stdbool.h>
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>
@@ -48,6 +49,13 @@ U_BOOT_DEVICE(imx6_thermal) = {
 };
 #endif
 
+#if defined(CONFIG_SECURE_BOOT)
+struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
+	.bank = 0,
+	.word = 6,
+};
+#endif
+
 u32 get_nr_cpus(void)
 {
 	struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
@@ -392,6 +400,13 @@ const struct boot_mode soc_boot_modes[] = {
 	{NULL,		0},
 };
 
+void reset_misc(void)
+{
+#ifdef CONFIG_VIDEO_MXS
+	lcdif_power_down();
+#endif
+}
+
 void s_init(void)
 {
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig
index ea19e5c411..97d62389fd 100644
--- a/arch/arm/cpu/armv7/mx7/Kconfig
+++ b/arch/arm/cpu/armv7/mx7/Kconfig
@@ -2,9 +2,11 @@ if ARCH_MX7
 
 config MX7
 	bool
+	select ROM_UNIFIED_SECTIONS
 	default y
 
 config MX7D
+	select ROM_UNIFIED_SECTIONS
 	bool
 
 choice
diff --git a/arch/arm/cpu/armv7/mx7/Makefile b/arch/arm/cpu/armv7/mx7/Makefile
index e6ecef010c..d21f87f18c 100644
--- a/arch/arm/cpu/armv7/mx7/Makefile
+++ b/arch/arm/cpu/armv7/mx7/Makefile
@@ -6,3 +6,7 @@
 #
 
 obj-y	:= soc.o clock.o clock_slice.o
+
+ifdef CONFIG_ARMV7_PSCI
+obj-y  += psci-mx7.o psci.o
+endif
diff --git a/arch/arm/cpu/armv7/mx7/psci-mx7.c b/arch/arm/cpu/armv7/mx7/psci-mx7.c
new file mode 100644
index 0000000000..9a330476cf
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx7/psci-mx7.c
@@ -0,0 +1,69 @@
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/arch/imx-regs.h>
+#include <common.h>
+
+#define __secure __attribute__((section("._secure.text")))
+
+#define GPC_CPU_PGC_SW_PDN_REQ	0xfc
+#define GPC_CPU_PGC_SW_PUP_REQ	0xf0
+#define GPC_PGC_C1		0x840
+
+#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7	0x2
+
+/* below is for i.MX7D */
+#define SRC_GPR1_MX7D		0x074
+#define SRC_A7RCR0		0x004
+#define SRC_A7RCR1		0x008
+
+#define BP_SRC_A7RCR0_A7_CORE_RESET0	0
+#define BP_SRC_A7RCR1_A7_CORE1_ENABLE	1
+
+static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
+{
+	writel(enable, GPC_IPS_BASE_ADDR + offset);
+}
+
+__secure void imx_gpcv2_set_core1_power(bool pdn)
+{
+	u32 reg = pdn ? GPC_CPU_PGC_SW_PUP_REQ : GPC_CPU_PGC_SW_PDN_REQ;
+	u32 val;
+
+	imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1);
+
+	val = readl(GPC_IPS_BASE_ADDR + reg);
+	val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
+	writel(val, GPC_IPS_BASE_ADDR + reg);
+
+	while ((readl(GPC_IPS_BASE_ADDR + reg) &
+	       BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7) != 0)
+		;
+
+	imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1);
+}
+
+__secure void imx_enable_cpu_ca7(int cpu, bool enable)
+{
+	u32 mask, val;
+
+	mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);
+	val = readl(SRC_BASE_ADDR + SRC_A7RCR1);
+	val = enable ? val | mask : val & ~mask;
+	writel(val, SRC_BASE_ADDR + SRC_A7RCR1);
+}
+
+__secure int imx_cpu_on(int fn, int cpu, int pc)
+{
+	writel(pc, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D);
+	imx_gpcv2_set_core1_power(true);
+	imx_enable_cpu_ca7(cpu, true);
+	return 0;
+}
+
+__secure int imx_cpu_off(int cpu)
+{
+	imx_enable_cpu_ca7(cpu, false);
+	imx_gpcv2_set_core1_power(false);
+	writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4);
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
new file mode 100644
index 0000000000..34c6ab33f0
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx7/psci.S
@@ -0,0 +1,54 @@
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/armv7.h>
+#include <asm/arch-armv7/generictimer.h>
+#include <asm/psci.h>
+
+	.pushsection ._secure.text, "ax"
+
+	.arch_extension sec
+
+	@ r1 = target CPU
+	@ r2 = target PC
+
+.globl	psci_arch_init
+psci_arch_init:
+	mov	r6, lr
+
+	bl	psci_get_cpu_id
+	bl	psci_get_cpu_stack_top
+	mov	sp, r0
+
+	bx	r6
+
+	@ r1 = target CPU
+	@ r2 = target PC
+
+.globl psci_cpu_on
+psci_cpu_on:
+	push	{lr}
+
+	mov	r0, r1
+	bl	psci_get_cpu_stack_top
+	str	r2, [r0]
+	dsb
+
+	ldr	r2, =psci_cpu_entry
+	bl	imx_cpu_on
+
+	pop	{pc}
+
+.globl psci_cpu_off
+psci_cpu_off:
+
+	bl	psci_cpu_off_common
+	bl	psci_get_cpu_id
+	bl	imx_cpu_off
+
+1: 	wfi
+	b 1b
+
+	.globl psci_text_end
+psci_text_end:
+	.popsection
diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
index 2ed05ea4f9..c777922e9d 100644
--- a/arch/arm/cpu/armv7/mx7/soc.c
+++ b/arch/arm/cpu/armv7/mx7/soc.c
@@ -11,6 +11,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/imx-common/boot_mode.h>
 #include <asm/imx-common/dma.h>
+#include <asm/imx-common/hab.h>
 #include <asm/arch/crm_regs.h>
 #include <dm.h>
 #include <imx_thermal.h>
@@ -28,6 +29,13 @@ U_BOOT_DEVICE(imx7_thermal) = {
 };
 #endif
 
+#if defined(CONFIG_SECURE_BOOT)
+struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
+	.bank = 1,
+	.word = 3,
+};
+#endif
+
 /*
  * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
  * defines a 2-bit SPEED_GRADING
@@ -114,10 +122,19 @@ u32 __weak get_board_rev(void)
 }
 #endif
 
+/* enable all periherial can be accessed in nosec mode */
+static void init_csu(void)
+{
+	int i = 0;
+	for (i = 0; i < CSU_NUM_REGS; i++)
+		writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
+}
+
 int arch_cpu_init(void)
 {
 	init_aips();
 
+	init_csu();
 	/* Disable PDE bit of WMCR register */
 	imx_set_wdog_powerdown(false);
 
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 03cd9f60f9..d48a905cf3 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -14,6 +14,23 @@ OUTPUT_ARCH(arm)
 ENTRY(_start)
 SECTIONS
 {
+	/*
+	 * Discard the relocation entries for secure text.
+	 * The secure code is bundled with u-boot image, so there will
+	 * be relocations entries for the secure code, since we use
+	 * "-mword-relocations" to compile and "-pie" to link into the
+	 * final image. We do not need the relocation entries for secure
+	 * code, because secure code will not be relocated, it only needs
+	 * to be copied from loading address to CONFIG_ARMV7_SECURE_BASE,
+	 * which is the linking and running address for secure code.
+	 * If keep the relocation entries in .rel.dyn section,
+	 * "relocation offset + linking address" may locates into an
+	 * address that is reserved by SoC, then will trigger data abort.
+	 *
+	 * The reason that move .rel._secure at the beginning, is to
+	 * avoid hole in the final image.
+	 */
+	/DISCARD/ : { *(.rel._secure*) }
 	. = 0x00000000;
 
 	. = ALIGN(4);
diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig
index 37b375249d..2296239226 100644
--- a/arch/arm/imx-common/Kconfig
+++ b/arch/arm/imx-common/Kconfig
@@ -1,2 +1,5 @@
 config IMX_CONFIG
 	string
+
+config ROM_UNIFIED_SECTIONS
+	bool
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 1698d061e7..e7190c3fbc 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -14,7 +14,7 @@ ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
 obj-y	+= timer.o cpu.o speed.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
-ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs))
 obj-y	+= misc.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
 endif
@@ -27,6 +27,7 @@ ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
 obj-y 	+= cache.o init.o
 obj-$(CONFIG_CMD_SATA) += sata.o
 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
+obj-$(CONFIG_SECURE_BOOT)    += hab.o
 endif
 ifeq ($(SOC),$(filter $(SOC),vf610))
 obj-y += ddrmc-vf610.o
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index d3d1fc5afa..656bb60bbe 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -279,6 +279,9 @@ void arch_preboot_os(void)
 	/* disable video before launching O/S */
 	ipuv3_fb_shutdown();
 #endif
+#if defined(CONFIG_VIDEO_MXS)
+	lcdif_power_down();
+#endif
 }
 
 void set_chipselect_size(int const cs_size)
diff --git a/arch/arm/cpu/armv7/mx6/hab.c b/arch/arm/imx-common/hab.c
similarity index 96%
rename from arch/arm/cpu/armv7/mx6/hab.c
rename to arch/arm/imx-common/hab.c
index 27cabe477d..8bbcc22454 100644
--- a/arch/arm/cpu/armv7/mx6/hab.c
+++ b/arch/arm/imx-common/hab.c
@@ -5,11 +5,13 @@
  */
 
 #include <common.h>
+#include <config.h>
+#include <fuse.h>
 #include <asm/io.h>
 #include <asm/system.h>
-#include <asm/arch/hab.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/imx-common/hab.h>
 
 /* -------- start of HAB API updates ------------*/
 
@@ -79,6 +81,8 @@
 #define MX6DQ_PU_IROM_MMU_EN_VAR	0x009024a8
 #define MX6DLS_PU_IROM_MMU_EN_VAR	0x00901dd0
 #define MX6SL_PU_IROM_MMU_EN_VAR	0x00900a18
+#define IS_HAB_ENABLED_BIT \
+	(is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)
 
 /*
  * +------------+  0x0 (DDR_UIMAGE_START) -
@@ -260,13 +264,18 @@ uint8_t hab_engines[16] = {
 
 bool is_hab_enabled(void)
 {
-	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-	struct fuse_bank *bank = &ocotp->bank[0];
-	struct fuse_bank0_regs *fuse =
-		(struct fuse_bank0_regs *)bank->fuse_regs;
-	uint32_t reg = readl(&fuse->cfg5);
+	struct imx_sec_config_fuse_t *fuse =
+		(struct imx_sec_config_fuse_t *)&imx_sec_config_fuse;
+	uint32_t reg;
+	int ret;
 
-	return (reg & 0x2) == 0x2;
+	ret = fuse_read(fuse->bank, fuse->word, &reg);
+	if (ret) {
+		puts("\nSecure boot fuse read error\n");
+		return ret;
+	}
+
+	return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
 }
 
 static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
@@ -414,7 +423,7 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
 			 * crash.
 			 */
 			/* Check MMU enabled */
-			if (get_cr() & CR_M) {
+			if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
 				if (is_cpu_type(MXC_CPU_MX6Q) ||
 				    is_cpu_type(MXC_CPU_MX6D)) {
 					/*
diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index 1a88ce6862..92c7218e69 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -66,25 +66,6 @@ static inline ulong gpt_get_clk(void)
 	return MXC_CLK32;
 #endif
 }
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	ulong gpt_clk = gpt_get_clk();
-
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, gpt_clk);
-
-	return tick;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long usec)
-{
-	ulong gpt_clk = gpt_get_clk();
-
-	usec = usec * gpt_clk + 999999;
-	do_div(usec, 1000000);
-
-	return usec;
-}
 
 int timer_init(void)
 {
@@ -130,44 +111,9 @@ int timer_init(void)
 	return 0;
 }
 
-unsigned long long get_ticks(void)
+unsigned long timer_read_counter(void)
 {
-	ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */
-
-	/* increment tbu if tbl has rolled over */
-	if (now < gd->arch.tbl)
-		gd->arch.tbu++;
-	gd->arch.tbl = now;
-	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
-}
-
-ulong get_timer_masked(void)
-{
-	/*
-	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / GPT_CLK = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
-	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
-	 * 5 * 10^6 days - long enough.
-	 */
-	return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timstamp value */
-void __udelay(unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
+	return __raw_readl(&cur_gpt->counter); /* current tick value */
 }
 
 /*
@@ -178,20 +124,3 @@ ulong get_tbclk(void)
 {
 	return gpt_get_clk();
 }
-
-/*
- * This function is intended for SHORT delays only.
- * It will overflow at around 10 seconds @ 400MHz,
- * or 20 seconds @ 200MHz.
- */
-unsigned long usec2ticks(unsigned long usec)
-{
-	ulong ticks;
-
-	if (usec < 1000)
-		ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
-	else
-		ticks = ((usec / 10) * (get_tbclk() / 100000));
-
-	return ticks;
-}
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 7e681e94d7..8a75902ee5 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -27,6 +27,18 @@
 #define MXC_SOC_MX6		0x60
 #define MXC_SOC_MX7		0x70
 
+#define CHIP_REV_1_0            0x10
+#define CHIP_REV_1_1            0x11
+#define CHIP_REV_1_2            0x12
+#define CHIP_REV_1_5            0x15
+#define CHIP_REV_2_0            0x20
+#define CHIP_REV_2_5            0x25
+#define CHIP_REV_3_0            0x30
+
+#define BOARD_REV_1_0           0x0
+#define BOARD_REV_2_0           0x1
+#define BOARD_VER_OFFSET        0x8
+
 #define CS0_128					0
 #define CS0_64M_CS1_64M				1
 #define CS0_64M_CS1_32M_CS2_32M			2
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index 78c4e9b088..1b00ed7e6d 100644
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -526,8 +526,4 @@ struct cspi_regs {
 	IMX_CSPI2_BASE, \
 	IMX_CSPI3_BASE
 
-#define CHIP_REV_1_0		0x10
-#define CHIP_REV_1_1		0x11
-#define CHIP_REV_1_2		0x12
-
 #endif				/* _IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 5f0e1e6346..e73cc07653 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -291,17 +291,6 @@
 #define DP_MFD_216	(4 - 1)
 #define DP_MFN_216	3
 
-#define CHIP_REV_1_0            0x10
-#define CHIP_REV_1_1            0x11
-#define CHIP_REV_2_0            0x20
-#define CHIP_REV_2_5		0x25
-#define CHIP_REV_3_0            0x30
-
-#define BOARD_REV_1_0           0x0
-#define BOARD_REV_2_0           0x1
-
-#define BOARD_VER_OFFSET	0x8
-
 #define IMX_IIM_BASE            (IIM_BASE_ADDR)
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 2b220d6f8f..14505239e8 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -66,6 +66,8 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
 void enable_enet_clk(unsigned char enable);
+int enable_lcdif_clock(u32 base_addr);
 void enable_qspi_clk(int qspi_num);
 void enable_thermal_clk(void);
+void mxs_set_lcdclk(u32 base_addr, u32 freq);
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 10306cd776..13e0a3d907 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -174,6 +174,9 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET		29
 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK		(0x7 << 26)
 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET		26
+/* LCDIF on i.MX6SX/UL */
+#define MXC_CCM_CBCMR_LCDIF1_PODF_MASK                  (0x7 << 23)
+#define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET                23
 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK		(0x7 << 23)
 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET		23
 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK		(0x3 << 21)
@@ -210,7 +213,10 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET			27
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK		(0x7 << 23)
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET	23
-/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
+/* LCFIF2_PODF on i.MX6SX */
+#define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK			(0x7 << 20)
+#define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET               20
+/* ACLK_EMI on i.MX6DQ/SDL/DQP */
 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK		(0x7 << 20)
 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET		20
 /* CSCMR1_GPMI/BCH exist on i.MX6UL */
@@ -400,6 +406,20 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET		19
 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK		(0x1 << 18)
+/* LCDIF1 on i.MX6SX/UL */
+#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK             (0x7 << 15)
+#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET           15
+#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK              (0x7 << 12)
+#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET            12
+#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK              (0x7 << 9)
+#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET            9
+/* LCDIF2 on i.MX6SX */
+#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK             (0x7 << 6)
+#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET           6
+#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK              (0x7 << 3)
+#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET            3
+#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK              (0x7 << 0)
+#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET             0
 
 /* All IPU2_DI1 are LCDIF1 on MX6SX */
 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
@@ -622,17 +642,16 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR2_IPMUX3_MASK			(3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET	22
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
-#ifdef CONFIG_MX6SX
+/* i.MX6SX/UL LCD and PXP */
 #define MXC_CCM_CCGR2_LCD_OFFSET			28
 #define MXC_CCM_CCGR2_LCD_MASK				(3 << MXC_CCM_CCGR2_LCD_OFFSET)
 #define MXC_CCM_CCGR2_PXP_OFFSET			30
 #define MXC_CCM_CCGR2_PXP_MASK				(3 << MXC_CCM_CCGR2_PXP_OFFSET)
-#else
+
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET	24
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET	26
 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
-#endif
 
 /* Exist on i.MX6SX */
 #define MXC_CCM_CCGR3_M4_OFFSET					2
@@ -685,6 +704,13 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK			(3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET		26
 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK			(3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+
+#define MXC_CCM_CCGR3_DISP_AXI_OFFSET                           6
+#define MXC_CCM_CCGR3_DISP_AXI_MASK                             (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET)
+#define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET                         8
+#define MXC_CCM_CCGR3_LCDIF2_PIX_MASK                           (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET)
+#define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET                         10
+#define MXC_CCM_CCGR3_LCDIF1_PIX_MASK                           (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET)
 /* AXI on i.MX6UL */
 #define MXC_CCM_CCGR3_AXI_CLK_OFFSET				28
 #define MXC_CCM_CCGR3_AXI_CLK_MASK				(3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 74512ac08e..2f068e5c9b 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -264,6 +264,7 @@
 #define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
 #define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
+#define MX6UL_LCDIF1_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x48000)
 #ifdef CONFIG_MX6SX
 #define DEBUG_MONITOR_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x4C000)
 #else
@@ -300,8 +301,6 @@
 #define CSI1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x14000)
 #define PXP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x18000)
 #define CSI2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x1C000)
-#define LCDIF1_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x20000)
-#define LCDIF2_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x24000)
 #define VADC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x28000)
 #define VDEC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x2C000)
 #define SPBA_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x3C000)
@@ -319,16 +318,11 @@
 #define PWM7_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xAC000)
 #define PWM8_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xB0000)
 #endif
+/* Only for i.MX6SX */
+#define LCDIF2_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x24000)
+#define MX6SX_LCDIF1_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x20000)
 #define MX6SX_WDOG3_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x88000)
 
-/* only for i.MX6SX/UL */
-#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ?	\
-			 MX6UL_WDOG3_BASE_ADDR :  MX6SX_WDOG3_BASE_ADDR)
-
-#define CHIP_REV_1_0                 0x10
-#define CHIP_REV_1_2                 0x12
-#define CHIP_REV_1_5                 0x15
-#define CHIP_REV_2_0                 0x20
 #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 #define IRAM_SIZE                    0x00040000
 #else
@@ -336,9 +330,17 @@
 #endif
 #define FEC_QUIRK_ENET_MAC
 
+#include <asm/imx-common/regs-lcdif.h>
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
 
+/* only for i.MX6SX/UL */
+#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ?	\
+			 MX6UL_WDOG3_BASE_ADDR :  MX6SX_WDOG3_BASE_ADDR)
+#define LCDIF1_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL)) ?	\
+			  MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR
+
+
 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
 
 #define SRC_SCR_CORE_1_RESET_OFFSET     14
@@ -413,10 +415,37 @@ struct src {
 };
 
 /* GPR1 bitfields */
+#define IOMUXC_GPR1_APP_CLK_REQ_N		BIT(30)
+#define IOMUXC_GPR1_PCIE_EXIT_L1		BIT(28)
+#define IOMUXC_GPR1_PCIE_RDY_L23		BIT(27)
+#define IOMUXC_GPR1_PCIE_ENTER_L1		BIT(26)
+#define IOMUXC_GPR1_MIPI_COLOR_SW		BIT(25)
+#define IOMUXC_GPR1_DPI_OFF			BIT(24)
+#define IOMUXC_GPR1_EXC_MON_SLVE		BIT(22)
 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET		21
 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK		(1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
+#define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX		BIT(20)
+#define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX		BIT(19)
+#define IOMUXC_GPR1_PCIE_TEST_PD			BIT(18)
+#define IOMUXC_GPR1_IPU_VPU_MUX_IPU2		BIT(17)
+#define IOMUXC_GPR1_PCIE_REF_CLK_EN		BIT(16)
+#define IOMUXC_GPR1_USB_EXP_MODE			BIT(15)
+#define IOMUXC_GPR1_PCIE_INT			BIT(14)
 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET		13
 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK		(1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
+#define IOMUXC_GPR1_GINT				BIT(12)
+#define IOMUXC_GPR1_ADDRS3_MASK			(0x3 << 10)
+#define IOMUXC_GPR1_ADDRS3_32MB			(0x0 << 10)
+#define IOMUXC_GPR1_ADDRS3_64MB			(0x1 << 10)
+#define IOMUXC_GPR1_ADDRS3_128MB			(0x2 << 10)
+#define IOMUXC_GPR1_ACT_CS3			BIT(9)
+#define IOMUXC_GPR1_ADDRS2_MASK			(0x3 << 7)
+#define IOMUXC_GPR1_ACT_CS2			BIT(6)
+#define IOMUXC_GPR1_ADDRS1_MASK			(0x3 << 4)
+#define IOMUXC_GPR1_ACT_CS1			BIT(3)
+#define IOMUXC_GPR1_ADDRS0_OFFSET		(1)
+#define IOMUXC_GPR1_ADDRS0_MASK			(0x3 << 1)
+#define IOMUXC_GPR1_ACT_CS0			BIT(0)
 
 /* GPR3 bitfields */
 #define IOMUXC_GPR3_GPU_DBG_OFFSET		29
@@ -465,6 +494,14 @@ struct src {
 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET		2
 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK		(3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
 
+/* gpr12 bitfields */
+#define IOMUXC_GPR12_ARMP_IPG_CLK_EN		BIT(27)
+#define IOMUXC_GPR12_ARMP_AHB_CLK_EN		BIT(26)
+#define IOMUXC_GPR12_ARMP_ATB_CLK_EN		BIT(25)
+#define IOMUXC_GPR12_ARMP_APB_CLK_EN		BIT(24)
+#define IOMUXC_GPR12_DEVICE_TYPE		(0xf << 12)
+#define IOMUXC_GPR12_PCIE_CTL_2			BIT(10)
+#define IOMUXC_GPR12_LOS_LEVEL			(0x1f << 4)
 
 struct iomuxc {
 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index 4dc11ee981..e28a807ec2 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -217,6 +217,7 @@
 #define SNVS_LPGPR	0x68
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/imx-common/regs-lcdif.h>
 #include <asm/types.h>
 
 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
@@ -866,6 +867,9 @@ struct cspi_regs {
 	ECSPI3_BASE_ADDR, \
 	ECSPI4_BASE_ADDR
 
+#define CSU_INIT_SEC_LEVEL0	0x00FF00FF
+#define CSU_NUM_REGS		64
+
 struct ocotp_regs {
 	u32 ctrl;
 	u32 ctrl_set;
@@ -1029,101 +1033,6 @@ struct rdc_sema_regs {
 	u16	rstgt;		/* Reset Gate */
 };
 
-/* eLCDIF controller registers */
-struct mxs_lcdif_regs {
-	u32	hw_lcdif_ctrl;			/* 0x00 */
-	u32	hw_lcdif_ctrl_set;
-	u32	hw_lcdif_ctrl_clr;
-	u32	hw_lcdif_ctrl_tog;
-	u32	hw_lcdif_ctrl1;			/* 0x10 */
-	u32	hw_lcdif_ctrl1_set;
-	u32	hw_lcdif_ctrl1_clr;
-	u32	hw_lcdif_ctrl1_tog;
-	u32	hw_lcdif_ctrl2;			/* 0x20 */
-	u32	hw_lcdif_ctrl2_set;
-	u32	hw_lcdif_ctrl2_clr;
-	u32	hw_lcdif_ctrl2_tog;
-	u32	hw_lcdif_transfer_count;	/* 0x30 */
-	u32	reserved1[3];
-	u32	hw_lcdif_cur_buf;		/* 0x40 */
-	u32	reserved2[3];
-	u32	hw_lcdif_next_buf;		/* 0x50 */
-	u32	reserved3[3];
-	u32	hw_lcdif_timing;		/* 0x60 */
-	u32	reserved4[3];
-	u32	hw_lcdif_vdctrl0;		/* 0x70 */
-	u32	hw_lcdif_vdctrl0_set;
-	u32	hw_lcdif_vdctrl0_clr;
-	u32	hw_lcdif_vdctrl0_tog;
-	u32	hw_lcdif_vdctrl1;		/* 0x80 */
-	u32	reserved5[3];
-	u32	hw_lcdif_vdctrl2;		/* 0x90 */
-	u32	reserved6[3];
-	u32	hw_lcdif_vdctrl3;		/* 0xa0 */
-	u32	reserved7[3];
-	u32	hw_lcdif_vdctrl4;		/* 0xb0 */
-	u32	reserved8[3];
-	u32	hw_lcdif_dvictrl0;		/* 0xc0 */
-	u32	reserved9[3];
-	u32	hw_lcdif_dvictrl1;		/* 0xd0 */
-	u32	reserved10[3];
-	u32	hw_lcdif_dvictrl2;		/* 0xe0 */
-	u32	reserved11[3];
-	u32	hw_lcdif_dvictrl3;		/* 0xf0 */
-	u32	reserved12[3];
-	u32	hw_lcdif_dvictrl4;		/* 0x100 */
-	u32	reserved13[3];
-	u32	hw_lcdif_csc_coeffctrl0;	/* 0x110 */
-	u32	reserved14[3];
-	u32	hw_lcdif_csc_coeffctrl1;	/* 0x120 */
-	u32	reserved15[3];
-	u32	hw_lcdif_csc_coeffctrl2;	/* 0x130 */
-	u32	reserved16[3];
-	u32	hw_lcdif_csc_coeffctrl3;	/* 0x140 */
-	u32	reserved17[3];
-	u32	hw_lcdif_csc_coeffctrl4;	/* 0x150 */
-	u32	reserved18[3];
-	u32	hw_lcdif_csc_offset;	/* 0x160 */
-	u32	reserved19[3];
-	u32	hw_lcdif_csc_limit;		/* 0x170 */
-	u32	reserved20[3];
-	u32	hw_lcdif_data;			/* 0x180 */
-	u32	reserved21[3];
-	u32	hw_lcdif_bm_error_stat;	/* 0x190 */
-	u32	reserved22[3];
-	u32	hw_lcdif_crc_stat;		/* 0x1a0 */
-	u32	reserved23[3];
-	u32	hw_lcdif_lcdif_stat;	/* 0x1b0 */
-	u32	reserved24[3];
-	u32	hw_lcdif_version;		/* 0x1c0 */
-	u32	reserved25[3];
-	u32	hw_lcdif_debug0;		/* 0x1d0 */
-	u32	reserved26[3];
-	u32	hw_lcdif_debug1;		/* 0x1e0 */
-	u32	reserved27[3];
-	u32	hw_lcdif_debug2;		/* 0x1f0 */
-	u32	reserved28[3];
-	u32	hw_lcdif_thres;			/* 0x200 */
-	u32	reserved29[3];
-	u32	hw_lcdif_as_ctrl;		/* 0x210 */
-	u32	reserved30[3];
-	u32	hw_lcdif_as_buf;		/* 0x220 */
-	u32	reserved31[3];
-	u32	hw_lcdif_as_next_buf;	/* 0x230 */
-	u32	reserved32[3];
-	u32	hw_lcdif_as_clrkeylow;	/* 0x240 */
-	u32	reserved33[3];
-	u32	hw_lcdif_as_clrkeyhigh;	/* 0x250 */
-	u32	reserved34[3];
-	u32	hw_lcdif_as_sync_delay;	/* 0x260 */
-	u32	reserved35[3];
-	u32	hw_lcdif_as_debug3;		/* 0x270 */
-	u32	reserved36[3];
-	u32	hw_lcdif_as_debug4;		/* 0x280 */
-	u32	reserved37[3];
-	u32	hw_lcdif_as_debug5;		/* 0x290 */
-};
-
 #define MXS_LCDIF_BASE ELCDIF1_IPS_BASE_ADDR
 
 #define	LCDIF_CTRL_SFTRST					(1 << 31)
diff --git a/arch/arm/include/asm/arch-mxs/clock.h b/arch/arm/include/asm/arch-mxs/clock.h
index fc9d75b509..fdc5395a70 100644
--- a/arch/arm/include/asm/arch-mxs/clock.h
+++ b/arch/arm/include/asm/arch-mxs/clock.h
@@ -46,7 +46,7 @@ uint32_t mxc_get_clock(enum mxc_clock clk);
 void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq);
 void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
 void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq);
-void mxs_set_lcdclk(uint32_t freq);
+void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq);
 
 /* Compatibility with the FEC Ethernet driver */
 #define	imx_get_fecclk()	mxc_get_clock(MXC_AHB_CLK)
diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h
index 86914ef742..8872438122 100644
--- a/arch/arm/include/asm/arch-mxs/imx-regs.h
+++ b/arch/arm/include/asm/arch-mxs/imx-regs.h
@@ -15,8 +15,8 @@
 #include <asm/imx-common/regs-bch.h>
 #include <asm/arch/regs-digctl.h>
 #include <asm/imx-common/regs-gpmi.h>
+#include <asm/imx-common/regs-lcdif.h>
 #include <asm/arch/regs-i2c.h>
-#include <asm/arch/regs-lcdif.h>
 #include <asm/arch/regs-lradc.h>
 #include <asm/arch/regs-ocotp.h>
 #include <asm/arch/regs-pinctrl.h>
diff --git a/arch/arm/include/asm/arch-mx6/hab.h b/arch/arm/include/asm/imx-common/hab.h
similarity index 96%
rename from arch/arm/include/asm/arch-mx6/hab.h
rename to arch/arm/include/asm/imx-common/hab.h
index d0eaa67180..dab6789b10 100644
--- a/arch/arm/include/asm/arch-mx6/hab.h
+++ b/arch/arm/include/asm/imx-common/hab.h
@@ -85,6 +85,15 @@ enum hab_context {
 	HAB_CTX_MAX
 };
 
+struct imx_sec_config_fuse_t {
+	int bank;
+	int word;
+};
+
+#if defined(CONFIG_SECURE_BOOT)
+extern struct imx_sec_config_fuse_t const imx_sec_config_fuse;
+#endif
+
 /*Function prototype description*/
 typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t,
 		uint8_t* , size_t*);
@@ -113,7 +122,7 @@ typedef void hapi_clock_init_t(void);
 #define HAB_ENG_RTL		0x77   /* RTL simulation engine */
 #define HAB_ENG_SW		0xff   /* Software engine */
 
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_ROM_UNIFIED_SECTIONS
 #define HAB_RVT_BASE			0x00000100
 #else
 #define HAB_RVT_BASE			0x00000094
diff --git a/arch/arm/include/asm/imx-common/regs-common.h b/arch/arm/include/asm/imx-common/regs-common.h
index e54a220fa3..738267480e 100644
--- a/arch/arm/include/asm/imx-common/regs-common.h
+++ b/arch/arm/include/asm/imx-common/regs-common.h
@@ -10,6 +10,8 @@
 #ifndef __MXS_REGS_COMMON_H__
 #define __MXS_REGS_COMMON_H__
 
+#include <linux/types.h>
+
 /*
  * The i.MXS has interesting feature when it comes to register access. There
  * are four kinds of access to one particular register. Those are:
diff --git a/arch/arm/include/asm/arch-mxs/regs-lcdif.h b/arch/arm/include/asm/imx-common/regs-lcdif.h
similarity index 92%
rename from arch/arm/include/asm/arch-mxs/regs-lcdif.h
rename to arch/arm/include/asm/imx-common/regs-lcdif.h
index 8915d84d0d..5a4f61f77b 100644
--- a/arch/arm/include/asm/arch-mxs/regs-lcdif.h
+++ b/arch/arm/include/asm/imx-common/regs-lcdif.h
@@ -1,5 +1,5 @@
 /*
- * Freescale i.MX28 LCDIF Register Definitions
+ * Freescale i.MX28/6SX/6UL/7D LCDIF Register Definitions
  *
  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  * on behalf of DENX Software Engineering GmbH
@@ -10,16 +10,17 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __MX28_REGS_LCDIF_H__
-#define __MX28_REGS_LCDIF_H__
-
-#include <asm/imx-common/regs-common.h>
+#ifndef __IMX_REGS_LCDIF_H__
+#define __IMX_REGS_LCDIF_H__
 
 #ifndef	__ASSEMBLY__
+#include <asm/imx-common/regs-common.h>
+
 struct mxs_lcdif_regs {
 	mxs_reg_32(hw_lcdif_ctrl)		/* 0x00 */
 	mxs_reg_32(hw_lcdif_ctrl1)		/* 0x10 */
-#if defined(CONFIG_MX28)
+#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+	defined(CONFIG_MX7)
 	mxs_reg_32(hw_lcdif_ctrl2)		/* 0x20 */
 #endif
 	mxs_reg_32(hw_lcdif_transfer_count)	/* 0x20/0x30 */
@@ -54,7 +55,8 @@ struct mxs_lcdif_regs {
 #endif
 	mxs_reg_32(hw_lcdif_data)		/* 0x1b0/0x180 */
 	mxs_reg_32(hw_lcdif_bm_error_stat)	/* 0x1c0/0x190 */
-#if defined(CONFIG_MX28)
+#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+	defined(CONFIG_MX7)
 	mxs_reg_32(hw_lcdif_crc_stat)		/* 0x1a0 */
 #endif
 	mxs_reg_32(hw_lcdif_lcdif_stat)		/* 0x1d0/0x1b0 */
@@ -62,6 +64,18 @@ struct mxs_lcdif_regs {
 	mxs_reg_32(hw_lcdif_debug0)		/* 0x1f0/0x1d0 */
 	mxs_reg_32(hw_lcdif_debug1)		/* 0x200/0x1e0 */
 	mxs_reg_32(hw_lcdif_debug2)		/* 0x1f0 */
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7)
+	mxs_reg_32(hw_lcdif_thres)
+	mxs_reg_32(hw_lcdif_as_ctrl)
+	mxs_reg_32(hw_lcdif_as_buf)
+	mxs_reg_32(hw_lcdif_as_next_buf)
+	mxs_reg_32(hw_lcdif_as_clrkeylow)
+	mxs_reg_32(hw_lcdif_as_clrkeyhigh)
+	mxs_reg_32(hw_lcdif_as_sync_delay)
+	mxs_reg_32(hw_lcdif_as_debug3)
+	mxs_reg_32(hw_lcdif_as_debug4)
+	mxs_reg_32(hw_lcdif_as_debug5)
+#endif
 };
 #endif
 
@@ -194,7 +208,7 @@ struct mxs_lcdif_regs {
 #if defined(CONFIG_MX23)
 #define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK			(0xff << 24)
 #define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET			24
-#elif defined(CONFIG_MX28)
+#else
 #define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK			(0x3fff << 18)
 #define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET			18
 #endif
@@ -214,4 +228,4 @@ struct mxs_lcdif_regs {
 #define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK		0x3ffff
 #define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET		0
 
-#endif /* __MX28_REGS_LCDIF_H__ */
+#endif /* __IMX_REGS_LCDIF_H__ */
diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h
index 5673fb4bc1..386c2dc42b 100644
--- a/arch/arm/include/asm/imx-common/sys_proto.h
+++ b/arch/arm/include/asm/imx-common/sys_proto.h
@@ -47,6 +47,8 @@ int fecmxc_initialize(bd_t *bis);
 u32 get_ahb_clk(void);
 u32 get_periph_clk(void);
 
+void lcdif_power_down(void);
+
 int mxs_reset_block(struct mxs_register_32 *reg);
 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
diff --git a/board/aristainetos/aristainetos-v2.c b/board/aristainetos/aristainetos-v2.c
index 49dbd2e497..fa4b4d2c15 100644
--- a/board/aristainetos/aristainetos-v2.c
+++ b/board/aristainetos/aristainetos-v2.c
@@ -580,6 +580,21 @@ static void setup_iomux_gpio(void)
 	imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 }
 
+static void set_gpr_register(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
+	       IOMUXC_GPR1_EXC_MON_SLVE |
+	       (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
+	       IOMUXC_GPR1_ACT_CS0,
+	       &iomuxc_regs->gpr[1]);
+	writel(0x0, &iomuxc_regs->gpr[8]);
+	writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
+	       IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
+	       &iomuxc_regs->gpr[12]);
+}
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -588,6 +603,7 @@ int board_early_init_f(void)
 	gpio_direction_output(SOFT_RESET_GPIO, 1);
 	gpio_direction_output(SD2_DRIVER_ENABLE, 1);
 	setup_display();
+	set_gpr_register();
 	return 0;
 }
 
diff --git a/board/bachmann/ot1200/ot1200_spl.c b/board/bachmann/ot1200/ot1200_spl.c
index 9c77fd3330..f651a40a49 100644
--- a/board/bachmann/ot1200/ot1200_spl.c
+++ b/board/bachmann/ot1200/ot1200_spl.c
@@ -156,7 +156,3 @@ void board_init_f(ulong dummy)
 	/* load/boot image from boot device */
 	board_init_r(NULL, 0);
 }
-
-void reset_cpu(ulong addr)
-{
-}
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index 01871e100a..a21e7b00e1 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -39,8 +39,27 @@ static struct splash_location cm_fx6_splash_locations[] = {
 	{
 		.name = "sf",
 		.storage = SPLASH_STORAGE_SF,
+		.flags = SPLASH_STORAGE_RAW,
 		.offset = 0x100000,
 	},
+	{
+		.name = "mmc_fs",
+		.storage = SPLASH_STORAGE_MMC,
+		.flags = SPLASH_STORAGE_FS,
+		.devpart = "2:1",
+	},
+	{
+		.name = "usb_fs",
+		.storage = SPLASH_STORAGE_USB,
+		.flags = SPLASH_STORAGE_FS,
+		.devpart = "0:1",
+	},
+	{
+		.name = "sata_fs",
+		.storage = SPLASH_STORAGE_SATA,
+		.flags = SPLASH_STORAGE_FS,
+		.devpart = "0:1",
+	},
 };
 
 int splash_screen_prepare(void)
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index ccefc40eb0..189d903b6e 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -64,6 +64,7 @@ struct splash_location splash_locations[] = {
 	{
 		.name = "nand",
 		.storage = SPLASH_STORAGE_NAND,
+		.flags = SPLASH_STORAGE_RAW,
 		.offset = 0x100000,
 	},
 };
diff --git a/board/creative/xfi3/xfi3.c b/board/creative/xfi3/xfi3.c
index 1d83ea89aa..509c671cda 100644
--- a/board/creative/xfi3/xfi3.c
+++ b/board/creative/xfi3/xfi3.c
@@ -163,7 +163,7 @@ static const struct {
 	{ 0x21, 0,  0x0000 },
 };
 
-void board_mxsfb_system_setup(void)
+void mxsfb_system_setup(void)
 {
 	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
 	int i;
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 5644167008..581c9d5560 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -684,7 +684,9 @@ int board_late_init(void)
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	setenv("board_name", "SABRESD");
 
-	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+	if (is_mx6dqp())
+		setenv("board_rev", "MX6QP");
+	else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
 		setenv("board_rev", "MX6Q");
 	else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
 		setenv("board_rev", "MX6DL");
@@ -732,6 +734,35 @@ const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
 	.dram_dqm7 =  0x00020030,
 };
 
+const struct mx6dq_iomux_ddr_regs mx6dqp_ddr_ioregs = {
+	.dram_sdclk_0 =  0x00000030,
+	.dram_sdclk_1 =  0x00000030,
+	.dram_cas =  0x00000030,
+	.dram_ras =  0x00000030,
+	.dram_reset =  0x00000030,
+	.dram_sdcke0 =  0x00003000,
+	.dram_sdcke1 =  0x00003000,
+	.dram_sdba2 =  0x00000000,
+	.dram_sdodt0 =  0x00003030,
+	.dram_sdodt1 =  0x00003030,
+	.dram_sdqs0 =  0x00000030,
+	.dram_sdqs1 =  0x00000030,
+	.dram_sdqs2 =  0x00000030,
+	.dram_sdqs3 =  0x00000030,
+	.dram_sdqs4 =  0x00000030,
+	.dram_sdqs5 =  0x00000030,
+	.dram_sdqs6 =  0x00000030,
+	.dram_sdqs7 =  0x00000030,
+	.dram_dqm0 =  0x00000030,
+	.dram_dqm1 =  0x00000030,
+	.dram_dqm2 =  0x00000030,
+	.dram_dqm3 =  0x00000030,
+	.dram_dqm4 =  0x00000030,
+	.dram_dqm5 =  0x00000030,
+	.dram_dqm6 =  0x00000030,
+	.dram_dqm7 =  0x00000030,
+};
+
 const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
 	.grp_ddr_type =  0x000C0000,
 	.grp_ddrmode_ctl =  0x00020000,
@@ -764,6 +795,21 @@ const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 	.p1_mpwrdlctl =  0x48254A36,
 };
 
+const struct mx6_mmdc_calibration mx6dqp_mmcd_calib = {
+	.p0_mpwldectrl0 =  0x001B001E,
+	.p0_mpwldectrl1 =  0x002E0029,
+	.p1_mpwldectrl0 =  0x001B002A,
+	.p1_mpwldectrl1 =  0x0019002C,
+	.p0_mpdgctrl0 =  0x43240334,
+	.p0_mpdgctrl1 =  0x0324031A,
+	.p1_mpdgctrl0 =  0x43340344,
+	.p1_mpdgctrl1 =  0x03280276,
+	.p0_mprddlctl =  0x44383A3E,
+	.p1_mprddlctl =  0x3C3C3846,
+	.p0_mpwrdlctl =  0x2E303230,
+	.p1_mpwrdlctl =  0x38283E34,
+};
+
 /* MT41K128M16JT-125 */
 static struct mx6_ddr3_cfg mem_ddr = {
 	.mem_speed = 1600,
@@ -797,9 +843,15 @@ static void gpr_init(void)
 
 	/* enable AXI cache for VDOA/VPU/IPU */
 	writel(0xF00000CF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
+	if (is_mx6dqp()) {
+		/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+		writel(0x007F007F, &iomux->gpr[6]);
+		writel(0x007F007F, &iomux->gpr[7]);
+	} else {
+		/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+		writel(0x007F007F, &iomux->gpr[6]);
+		writel(0x007F007F, &iomux->gpr[7]);
+	}
 }
 
 /*
@@ -827,8 +879,13 @@ static void spl_dram_init(void)
 		.ddr_type = DDR_TYPE_DDR3,
 	};
 
-	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
-	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+	if (is_mx6dqp()) {
+		mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs);
+		mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr);
+	} else {
+		mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+		mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+	}
 }
 
 void board_init_f(ulong dummy)
@@ -857,8 +914,4 @@ void board_init_f(ulong dummy)
 	/* load/boot image from boot device */
 	board_init_r(NULL, 0);
 }
-
-void reset_cpu(ulong addr)
-{
-}
 #endif
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 6ba604e707..5eab4b54a8 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -520,8 +520,4 @@ void board_init_f(ulong dummy)
 	/* load/boot image from boot device */
 	board_init_r(NULL, 0);
 }
-
-void reset_cpu(ulong addr)
-{
-}
 #endif
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index b9af7e7b95..3ee46629ee 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -598,8 +598,4 @@ void board_init_f(ulong dummy)
 	/* load/boot image from boot device */
 	board_init_r(NULL, 0);
 }
-
-void reset_cpu(ulong addr)
-{
-}
 #endif
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 8650f350f3..b9b35736cf 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -52,6 +52,9 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SPEED_HIGH   |                                  \
 	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
 
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
 #define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
 	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
 
@@ -568,6 +571,62 @@ int board_phy_config(struct phy_device *phydev)
 }
 #endif
 
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+	MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+
+	/* LCD_RST */
+	MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* Use GPIO for Brightness adjustment, duty cycle = period. */
+	MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static int setup_lcd(void)
+{
+	enable_lcdif_clock(LCDIF1_BASE_ADDR);
+
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+	/* Reset the LCD */
+	gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
+	udelay(500);
+	gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
+
+	/* Set Brightness to high */
+	gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
+
+	return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -600,6 +659,10 @@ int board_init(void)
 	board_qspi_init();
 #endif
 
+#ifdef CONFIG_VIDEO_MXS
+	setup_lcd();
+#endif
+
 	return 0;
 }
 
@@ -811,8 +874,4 @@ void board_init_f(ulong dummy)
 	/* load/boot image from boot device */
 	board_init_r(NULL, 0);
 }
-
-void reset_cpu(ulong addr)
-{
-}
 #endif
diff --git a/board/freescale/mx7dsabresd/imximage.cfg b/board/freescale/mx7dsabresd/imximage.cfg
index 91b70ee4c8..76574ff506 100644
--- a/board/freescale/mx7dsabresd/imximage.cfg
+++ b/board/freescale/mx7dsabresd/imximage.cfg
@@ -22,6 +22,13 @@ IMAGE_VERSION 2
 
 BOOT_FROM	sd
 
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
 /*
  * Device Configuration Data (DCD)
  *
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index ee9890b599..6c863dae5a 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -41,6 +41,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
 	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
 
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
+	PAD_CTL_DSE_3P3V_49OHM)
+
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 /* I2C1 for PMIC */
@@ -190,6 +193,63 @@ static void iox74lv_init(void)
 	gpio_direction_output(IOX_STCP, 1);
 };
 
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+	MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+
+	MX7D_PAD_LCD_RESET__GPIO3_IO4	| MUX_PAD_CTRL(LCD_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pwm_pads[] = {
+	/* Use GPIO for Brightness adjustment, duty cycle = period */
+	MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static int setup_lcd(void)
+{
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+	imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
+
+	/* Reset LCD */
+	gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
+	udelay(500);
+	gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
+
+	/* Set Brightness to high */
+	gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_FEC_MXC
 static iomux_v3_cfg_t const fec1_pads[] = {
 	MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
@@ -417,6 +477,10 @@ int board_init(void)
 	setup_fec();
 #endif
 
+#ifdef CONFIG_VIDEO_MXS
+	setup_lcd();
+#endif
+
 	return 0;
 }
 
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index d28eb14f87..0a6ad47c7d 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -574,7 +574,3 @@ int spl_start_uboot(void)
 	return ret;
 }
 #endif
-
-void reset_cpu(ulong addr)
-{
-}
diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c
index b1688e0295..eb46265a32 100644
--- a/board/kosagi/novena/novena_spl.c
+++ b/board/kosagi/novena/novena_spl.c
@@ -607,7 +607,3 @@ void board_init_f(ulong dummy)
 	/* load/boot image from boot device */
 	board_init_r(NULL, 0);
 }
-
-void reset_cpu(ulong addr)
-{
-}
diff --git a/common/splash_source.c b/common/splash_source.c
index d1bb5a4baf..a09dd4b46e 100644
--- a/common/splash_source.c
+++ b/common/splash_source.c
@@ -12,13 +12,16 @@
 #include <splash.h>
 #include <spi_flash.h>
 #include <spi.h>
+#include <usb.h>
+#include <sata.h>
 #include <bmp_layout.h>
+#include <fs.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_SPI_FLASH
 static struct spi_flash *sf;
-static int splash_sf_read(u32 bmp_load_addr, int offset, size_t read_size)
+static int splash_sf_read_raw(u32 bmp_load_addr, int offset, size_t read_size)
 {
 	if (!sf) {
 		sf = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
@@ -32,7 +35,7 @@ static int splash_sf_read(u32 bmp_load_addr, int offset, size_t read_size)
 	return spi_flash_read(sf, offset, read_size, (void *)bmp_load_addr);
 }
 #else
-static int splash_sf_read(u32 bmp_load_addr, int offset, size_t read_size)
+static int splash_sf_read_raw(u32 bmp_load_addr, int offset, size_t read_size)
 {
 	debug("%s: sf support not available\n", __func__);
 	return -ENOSYS;
@@ -40,7 +43,7 @@ static int splash_sf_read(u32 bmp_load_addr, int offset, size_t read_size)
 #endif
 
 #ifdef CONFIG_CMD_NAND
-static int splash_nand_read(u32 bmp_load_addr, int offset, size_t read_size)
+static int splash_nand_read_raw(u32 bmp_load_addr, int offset, size_t read_size)
 {
 	return nand_read_skip_bad(&nand_info[nand_curr_device], offset,
 				  &read_size, NULL,
@@ -48,14 +51,14 @@ static int splash_nand_read(u32 bmp_load_addr, int offset, size_t read_size)
 				  (u_char *)bmp_load_addr);
 }
 #else
-static int splash_nand_read(u32 bmp_load_addr, int offset, size_t read_size)
+static int splash_nand_read_raw(u32 bmp_load_addr, int offset, size_t read_size)
 {
 	debug("%s: nand support not available\n", __func__);
 	return -ENOSYS;
 }
 #endif
 
-static int splash_storage_read(struct splash_location *location,
+static int splash_storage_read_raw(struct splash_location *location,
 			       u32 bmp_load_addr, size_t read_size)
 {
 	u32 offset;
@@ -66,9 +69,9 @@ static int splash_storage_read(struct splash_location *location,
 	offset = location->offset;
 	switch (location->storage) {
 	case SPLASH_STORAGE_NAND:
-		return splash_nand_read(bmp_load_addr, offset, read_size);
+		return splash_nand_read_raw(bmp_load_addr, offset, read_size);
 	case SPLASH_STORAGE_SF:
-		return splash_sf_read(bmp_load_addr, offset, read_size);
+		return splash_sf_read_raw(bmp_load_addr, offset, read_size);
 	default:
 		printf("Unknown splash location\n");
 	}
@@ -85,7 +88,7 @@ static int splash_load_raw(struct splash_location *location, u32 bmp_load_addr)
 	if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
 		goto splash_address_too_high;
 
-	res = splash_storage_read(location, bmp_load_addr, bmp_header_size);
+	res = splash_storage_read_raw(location, bmp_load_addr, bmp_header_size);
 	if (res < 0)
 		return res;
 
@@ -95,7 +98,7 @@ static int splash_load_raw(struct splash_location *location, u32 bmp_load_addr)
 	if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
 		goto splash_address_too_high;
 
-	return splash_storage_read(location, bmp_load_addr, bmp_size);
+	return splash_storage_read_raw(location, bmp_load_addr, bmp_size);
 
 splash_address_too_high:
 	printf("Error: splashimage address too high. Data overwrites U-Boot and/or placed beyond DRAM boundaries.\n");
@@ -103,6 +106,103 @@ splash_address_too_high:
 	return -EFAULT;
 }
 
+static int splash_select_fs_dev(struct splash_location *location)
+{
+	int res;
+
+	switch (location->storage) {
+	case SPLASH_STORAGE_MMC:
+		res = fs_set_blk_dev("mmc", location->devpart, FS_TYPE_ANY);
+		break;
+	case SPLASH_STORAGE_USB:
+		res = fs_set_blk_dev("usb", location->devpart, FS_TYPE_ANY);
+		break;
+	case SPLASH_STORAGE_SATA:
+		res = fs_set_blk_dev("sata", location->devpart, FS_TYPE_ANY);
+		break;
+	default:
+		printf("Error: unsupported location storage.\n");
+		return -ENODEV;
+	}
+
+	if (res)
+		printf("Error: could not access storage.\n");
+
+	return res;
+}
+
+#ifdef CONFIG_USB_STORAGE
+static int splash_init_usb(void)
+{
+	int err;
+
+	err = usb_init();
+	if (err)
+		return err;
+
+	return usb_stor_scan(1) < 0 ? -ENODEV : 0;
+}
+#else
+static inline int splash_init_usb(void)
+{
+	printf("Cannot load splash image: no USB support\n");
+	return -ENOSYS;
+}
+#endif
+
+#ifdef CONFIG_CMD_SATA
+static int splash_init_sata(void)
+{
+	return sata_initialize();
+}
+#else
+static inline int splash_init_sata(void)
+{
+	printf("Cannot load splash image: no SATA support\n");
+	return -ENOSYS;
+}
+#endif
+
+#define SPLASH_SOURCE_DEFAULT_FILE_NAME		"splash.bmp"
+
+static int splash_load_fs(struct splash_location *location, u32 bmp_load_addr)
+{
+	int res = 0;
+	loff_t bmp_size;
+	char *splash_file;
+
+	splash_file = getenv("splashfile");
+	if (!splash_file)
+		splash_file = SPLASH_SOURCE_DEFAULT_FILE_NAME;
+
+	if (location->storage == SPLASH_STORAGE_USB)
+		res = splash_init_usb();
+
+	if (location->storage == SPLASH_STORAGE_SATA)
+		res = splash_init_sata();
+
+	if (res)
+		return res;
+
+	res = splash_select_fs_dev(location);
+	if (res)
+		return res;
+
+	res = fs_size(splash_file, &bmp_size);
+	if (res) {
+		printf("Error (%d): cannot determine file size\n", res);
+		return res;
+	}
+
+	if (bmp_load_addr + bmp_size >= gd->start_addr_sp) {
+		printf("Error: splashimage address too high. Data overwrites U-Boot and/or placed beyond DRAM boundaries.\n");
+		return -EFAULT;
+	}
+
+	splash_select_fs_dev(location);
+	return fs_read(splash_file, bmp_load_addr, 0, 0, NULL);
+}
+
 /**
  * select_splash_location - return the splash location based on board support
  *			    and env variable "splashsource".
@@ -172,5 +272,10 @@ int splash_source_load(struct splash_location *locations, uint size)
 	if (!splash_location)
 		return -EINVAL;
 
-	return splash_load_raw(splash_location, bmp_load_addr);
+	if (splash_location->flags & SPLASH_STORAGE_RAW)
+		return splash_load_raw(splash_location, bmp_load_addr);
+	else if (splash_location->flags & SPLASH_STORAGE_FS)
+		return splash_load_fs(splash_location, bmp_load_addr);
+
+	return -EINVAL;
 }
diff --git a/doc/README.splashprepare b/doc/README.splashprepare
index a0f0f3ca51..56c1bef662 100644
--- a/doc/README.splashprepare
+++ b/doc/README.splashprepare
@@ -19,3 +19,8 @@ splashsource works as follows:
   use that splash location.
 - If splashsource is undefined, use the first splash location as default.
 - If splashsource is set to an unsupported value, do not load a splash screen.
+
+A splash source location can describe either storage with raw data, or storage
+formatted with a file system. In case of a filesystem, the splash screen data is
+loaded as a file. The name of the splash screen file can be controlled with the
+environment variable "splashfile".
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 101a619558..b92da4e202 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -83,6 +83,13 @@ config FSL_SEC_MON
 	  Security Monitor can be transitioned on any security failures,
 	  like software violations or hardware security violations.
 
+config MXC_OCOTP
+	bool "Enable MXC OCOTP Driver"
+	help
+	  If you say Y here, you will get support for the One Time
+	  Programmable memory pages that are stored on the some
+	  Freescale i.MX processors.
+
 config PCA9551_LED
 	bool "Enable PCA9551 LED driver"
 	help
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 03b0f88acf..ddbb118d70 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -55,7 +55,7 @@ static void mxs_lcd_init(GraphicDevice *panel,
 	uint8_t valid_data = 0;
 
 	/* Kick in the LCDIF clock */
-	mxs_set_lcdclk(PS2KHZ(mode->pixclock));
+	mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));
 
 	/* Restart the LCDIF block */
 	mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
@@ -131,6 +131,23 @@ static void mxs_lcd_init(GraphicDevice *panel,
 	writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
 }
 
+void lcdif_power_down(void)
+{
+	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+	int timeout = 1000000;
+
+	writel(panel.frameAdrs, &regs->hw_lcdif_cur_buf_reg);
+	writel(panel.frameAdrs, &regs->hw_lcdif_next_buf_reg);
+	writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
+	while (--timeout) {
+		if (readl(&regs->hw_lcdif_ctrl1_reg) &
+		    LCDIF_CTRL1_VSYNC_EDGE_IRQ)
+			break;
+		udelay(1);
+	}
+	mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);
+}
+
 void *video_hw_init(void)
 {
 	int bpp = -1;
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 15905b9840..99bf7d6550 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -250,4 +250,8 @@
 		"else echo U-Boot not downloaded..exiting;fi\0"		\
 	"bootcmd=run net_nfs\0"
 
+/* Enable FIT images support */
+#define CONFIG_CMD_FDT
+#define CONFIG_FIT
+
 #endif				/* __CONFIG_H */
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index 6e89dd1455..4feb12194b 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -8,6 +8,7 @@
 #ifndef __MX6CUBOXI_CONFIG_H
 #define __MX6CUBOXI_CONFIG_H
 
+#include <config_distro_defaults.h>
 #include "mx6_common.h"
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -81,23 +82,26 @@
 
 #define CONFIG_MXC_UART_BASE	UART1_BASE
 #define CONFIG_CONSOLE_DEV	"ttymxc0"
-#define CONFIG_MMCROOT		"/dev/mmcblk0p2"
 #define CONFIG_SYS_FSL_USDHC_NUM	1
 #define CONFIG_SYS_MMC_ENV_DEV		0	/* SDHC2 */
 
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"script=boot.scr\0" \
-	"image=zImage\0" \
 	"fdtfile=undefined\0" \
 	"fdt_addr_r=0x18000000\0" \
-	"boot_fdt=try\0" \
+	"fdt_addr=0x18000000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0"  \
+	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+	"ramdisk_addr_r=0x13000000\0" \
+	"ramdiskaddr=0x13000000\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_high=0xffffffff\0" \
 	"ip_dyn=yes\0" \
 	"console=" CONFIG_CONSOLE_DEV "\0" \
 	"bootm_size=0x10000000\0" \
 	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
-	"mmcpart=1\0" \
-	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
 	"update_sd_firmware=" \
 		"if test ${ip_dyn} = yes; then " \
 			"setenv get_cmd dhcp; " \
@@ -111,53 +115,6 @@
 				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
 			"fi; "	\
 		"fi\0" \
-	"mmcargs=setenv bootargs console=${console},${baudrate} " \
-		"root=${mmcroot}\0" \
-	"loadbootscript=" \
-		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
-	"bootscript=echo Running bootscript from mmc ...; " \
-		"source\0" \
-	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
-	"mmcboot=echo Booting from mmc ...; " \
-		"run mmcargs; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"bootz ${loadaddr} - ${fdt_addr_r}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
-				"else " \
-					"echo WARN: Cannot load the DT; " \
-				"fi; " \
-			"fi; " \
-		"else " \
-			"bootz; " \
-		"fi;\0" \
-	"netargs=setenv bootargs console=${console},${baudrate} " \
-		"root=/dev/nfs " \
-		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-	"netboot=echo Booting from net ...; " \
-		"run netargs; " \
-		"if test ${ip_dyn} = yes; then " \
-			"setenv get_cmd dhcp; " \
-		"else " \
-			"setenv get_cmd tftp; " \
-		"fi; " \
-		"${get_cmd} ${image}; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
-				"bootz ${loadaddr} - ${fdt_addr_r}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
-				"else " \
-					"echo WARN: Cannot load the DT; " \
-				"fi; " \
-			"fi; " \
-		"else " \
-			"bootz; " \
-		"fi;\0" \
 	"findfdt="\
 		"if test $board_name = HUMMINGBOARD && test $board_rev = MX6Q ; then " \
 			"setenv fdtfile imx6q-hummingboard.dtb; fi; " \
@@ -169,20 +126,23 @@
 			"setenv fdtfile imx6dl-cubox-i.dtb; fi; " \
 		"if test $fdtfile = undefined; then " \
 			"echo WARNING: Could not determine dtb to use; fi; \0" \
+	BOOTENV
 
 #define CONFIG_BOOTCOMMAND \
 	"run findfdt; " \
-	"mmc dev ${mmcdev};" \
-	"if mmc rescan; then " \
-		"if run loadbootscript; then " \
-		"run bootscript; " \
-		"else " \
-			"if run loadimage; then " \
-				"run mmcboot; " \
-			"else run netboot; " \
-			"fi; " \
-		"fi; " \
-	"else run netboot; fi"
+	"run distro_bootcmd"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS
+#endif /* CONFIG_SPL_BUILD */
 
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS           1
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 9dcc64ea57..3e045ef7a6 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -158,6 +158,8 @@
 					"setenv fdt_file imx6q-sabreauto.dtb; fi; " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
 					"setenv fdt_file imx6dl-sabreauto.dtb; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
+					"setenv fdt_file imx6qp-sabresd.dtb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
 					"setenv fdt_file imx6q-sabresd.dtb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index e9e3b27f36..bfc4f61814 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -19,7 +19,6 @@
 #define CONFIG_MXC_UART_BASE	UART1_BASE
 #define CONFIG_CONSOLE_DEV		"ttymxc0"
 #define CONFIG_MMCROOT			"/dev/mmcblk1p2"
-#define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
 
 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
 
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index d5faae6a7b..577963263e 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -77,6 +77,7 @@
 	"fdt_addr=0x83000000\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
+	"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
@@ -242,4 +243,21 @@
 
 #define CONFIG_IMX_THERMAL
 
+#define CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
+#endif
+
 #endif
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 1b6edeeae5..5615a348e8 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -33,7 +33,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT
 
-#define CONFIG_ROM_UNIFIED_SECTIONS
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
@@ -92,4 +91,15 @@
 #define CONFIG_CMD_FUSE
 #define CONFIG_MXC_OCOTP
 
+/*
+ * Default boot linux kernel in no secure mode.
+ * If want to boot kernel in secure mode, please define CONFIG_MX7_SEC
+ */
+#ifndef CONFIG_MX7_SEC
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_PSCI
+#define CONFIG_ARMV7_PSCI_NR_CPUS	2
+#define CONFIG_ARMV7_SECURE_BASE	0x00900000
+#endif
+
 #endif
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index f16f9c1271..cc98547461 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -14,6 +14,10 @@
 #define CONFIG_DBG_MONITOR
 #define PHYS_SDRAM_SIZE			SZ_1G
 
+/* Uncomment to enable secure boot support */
+/* #define CONFIG_SECURE_BOOT */
+#define CONFIG_CSF_SIZE			0x4000
+
 /* Network */
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
@@ -65,8 +69,15 @@
 	"initrd_high=0xffffffff\0" \
 	"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
 
+#define CONFIG_DFU_ENV_SETTINGS \
+	"dfu_alt_info=image raw 0 0x800000;"\
+		"u-boot raw 0 0x4000;"\
+		"bootimg part 0 1;"\
+		"rootfs part 0 2\0" \
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_DFU_ENV_SETTINGS \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
 	"console=ttymxc0\0" \
@@ -76,6 +87,7 @@
 	"fdt_addr=0x83000000\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
+	"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
@@ -188,4 +200,40 @@
 
 #define CONFIG_IMX_THERMAL
 
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+
+#define CONFIG_USB_GADGET
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+
+#define CONFIG_G_DNL_VENDOR_NUM		0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER	"FSL"
+
+/* USB Device Firmware Update support */
+#define CONFIG_CMD_DFU
+#define CONFIG_USB_FUNCTION_DFU
+#define CONFIG_DFU_MMC
+#define CONFIG_DFU_RAM
+
+#define CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/novena.h b/include/configs/novena.h
index cd426be18c..d88389a472 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -197,7 +197,7 @@
 	"bootdev=/dev/mmcblk0p1\0"					\
 	"rootdev=/dev/mmcblk0p2\0"					\
 	"netdev=eth0\0"							\
-	"kernel_addr_r=0x18000000\0"					\
+	"kernel_addr_r="__stringify(CONFIG_LOADADDR)"\0"		\
 	"addcons="							\
 		"setenv bootargs ${bootargs} "				\
 		"console=${consdev},${baudrate}\0"			\
diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h
index fbca8a68ef..2f6c97cf58 100644
--- a/include/configs/ts4800.h
+++ b/include/configs/ts4800.h
@@ -24,6 +24,8 @@
 
 #define CONFIG_HW_WATCHDOG
 
+#define CONFIG_OF_LIBFDT
+
 #define CONFIG_MACH_TYPE	MACH_TYPE_TS48XX
 
 /* text base address used when linking */
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 6e8aec267d..4c8e9e9819 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -9,6 +9,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <config_distro_defaults.h>
 #include "mx6_common.h"
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -88,19 +89,15 @@
 
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"script=boot.scr\0" \
-	"image=zImage\0" \
-	"console=ttymxc0\0" \
+	"console=ttymxc0,115200\0" \
 	"splashpos=m,m\0" \
 	"fdtfile=undefined\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
+	"fdt_addr_r=0x18000000\0" \
 	"fdt_addr=0x18000000\0" \
-	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
 	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
-	"mmcpart=1\0" \
-	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
 	"update_sd_firmware_filename=u-boot.imx\0" \
 	"update_sd_firmware=" \
 		"if test ${ip_dyn} = yes; then " \
@@ -115,8 +112,6 @@
 				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
 			"fi; "	\
 		"fi\0" \
-	"mmcargs=setenv bootargs console=${console},${baudrate} " \
-		"root=${mmcroot}; run videoargs\0" \
 	"videoargs=" \
 		"setenv nextcon 0; " \
 		"if hdmidet; then " \
@@ -143,51 +138,6 @@
 			"echo '- no FWBADAPT-7WVGA-LCD-F07A-0102 display';" \
 		"fi; " \
 		"setenv bootargs ${bootargs} ${fbmem}\0" \
-	"loadbootscript=" \
-		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
-	"bootscript=echo Running bootscript from mmc ...; " \
-		"source\0" \
-	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile}\0" \
-	"mmcboot=echo Booting from mmc ...; " \
-		"run mmcargs; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
-				"else " \
-					"echo WARN: Cannot load the DT; " \
-				"fi; " \
-			"fi; " \
-		"else " \
-			"bootz; " \
-		"fi;\0" \
-	"netargs=setenv bootargs console=${console},${baudrate} " \
-		"root=/dev/nfs " \
-	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-		"netboot=echo Booting from net ...; " \
-		"run netargs; " \
-		"if test ${ip_dyn} = yes; then " \
-			"setenv get_cmd dhcp; " \
-		"else " \
-			"setenv get_cmd tftp; " \
-		"fi; " \
-		"${get_cmd} ${image}; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr} ${fdtfile}; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
-				"else " \
-					"echo WARN: Cannot load the DT; " \
-				"fi; " \
-			"fi; " \
-		"else " \
-			"bootz; " \
-		"fi;\0" \
 	"findfdt="\
 		"if test $board_name = C1 && test $board_rev = MX6Q ; then " \
 			"setenv fdtfile imx6q-wandboard.dtb; fi; " \
@@ -199,19 +149,25 @@
 			"setenv fdtfile imx6dl-wandboard-revb1.dtb; fi; " \
 		"if test $fdtfile = undefined; then " \
 			"echo WARNING: Could not determine dtb to use; fi; \0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"pxe_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"ramdisk_addr_r=0x13000000\0" \
+	"ramdiskaddr=0x13000000\0" \
+	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(USB, usb, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
 
 #define CONFIG_BOOTCOMMAND \
 	   "run findfdt; " \
-	   "mmc dev ${mmcdev}; if mmc rescan; then " \
-		   "if run loadbootscript; then " \
-			   "run bootscript; " \
-		   "else " \
-			   "if run loadimage; then " \
-				   "run mmcboot; " \
-			   "else run netboot; " \
-			   "fi; " \
-		   "fi; " \
-	   "else run netboot; fi"
+	   "run distro_bootcmd"
+
+#include <config_distro_bootcmd.h>
 
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
diff --git a/include/splash.h b/include/splash.h
index 7ae7a68688..f0755ca695 100644
--- a/include/splash.h
+++ b/include/splash.h
@@ -27,12 +27,22 @@
 enum splash_storage {
 	SPLASH_STORAGE_NAND,
 	SPLASH_STORAGE_SF,
+	SPLASH_STORAGE_MMC,
+	SPLASH_STORAGE_USB,
+	SPLASH_STORAGE_SATA,
+};
+
+enum splash_flags {
+	SPLASH_STORAGE_RAW,
+	SPLASH_STORAGE_FS,
 };
 
 struct splash_location {
 	char *name;
 	enum splash_storage storage;
+	enum splash_flags flags;
 	u32 offset;	/* offset from start of storage */
+	char *devpart;  /* Use the load command dev:part conventions */
 };
 
 int splash_source_load(struct splash_location *locations, uint size);