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DM9000: Some minor code cleanups
Some lines of the U-boot DM9000x driver are longer than 80 characters, or need some other minor cleanup. Signed-off-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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@ -51,6 +51,7 @@ v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
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for DM9000A.
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- Adapted reset procedure to match DM9000 application
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notes (i.e. double reset)
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- some minor code cleanups
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These changes are tested with DM9000{A,EP,E} together
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with a 200MHz Atmel AT91SAM92161 core
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@ -115,7 +116,7 @@ typedef struct board_info {
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void (*outblk)(void *data_ptr, int count);
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void (*inblk)(void *data_ptr, int count);
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void (*rx_status)(u16 *RxStatus, u16 *RxLen);
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} board_info_t;
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} board_info_t;
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static board_info_t dm9000_info;
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/* For module input parameter */
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@ -454,15 +455,22 @@ eth_init(bd_t * bd)
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/* Set PHY */
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set_PHY_mode();
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/* Program operating register */
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DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */
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DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */
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DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
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DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */
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DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */
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DM9000_iow(DM9000_SMCR, 0); /* Special Mode */
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DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
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DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */
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/* Program operating register, only intern phy supported by now */
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DM9000_iow(DM9000_NCR, 0x0);
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/* TX Polling clear */
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DM9000_iow(DM9000_TCR, 0);
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/* Less 3Kb, 200us */
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DM9000_iow(DM9000_BPTR, 0x3f);
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/* Flow Control : High/Low Water */
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DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
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/* SH FIXME: This looks strange! Flow Control */
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DM9000_iow(DM9000_FCR, 0x0);
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/* Special Mode */
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DM9000_iow(DM9000_SMCR, 0);
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/* clear TX status */
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DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
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/* Clear interrupt status */
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DM9000_iow(DM9000_ISR, 0x0f);
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/* Set Node address */
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for (i = 0; i < 6; i++)
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@ -496,8 +504,11 @@ eth_init(bd_t * bd)
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DM9000_DBG("\n");
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/* Activate DM9000 */
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DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */
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DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */
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/* RX enable */
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DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
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/* Enable TX/RX interrupt mask */
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DM9000_iow(DM9000_IMR, IMR_PAR);
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i = 0;
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while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */
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udelay(1000);
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@ -720,7 +731,7 @@ phy_read(int reg)
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/* Fill the phyxcer register into REG_0C */
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DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
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DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
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udelay(100); /* Wait read complete */
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udelay(100); /* Wait read complete */
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DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
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val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
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@ -743,8 +754,8 @@ phy_write(int reg, u16 value)
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DM9000_iow(DM9000_EPDRL, (value & 0xff));
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DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
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DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
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udelay(500); /* Wait write complete */
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udelay(500); /* Wait write complete */
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DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
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DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value);
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}
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#endif /* CONFIG_DRIVER_DM9000 */
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#endif /* CONFIG_DRIVER_DM9000 */
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