mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-01 09:00:45 +09:00
powerpc/corenet_ds: move SATA config to board configuration
board configuration file is included before asm/config_mpc85xx.h. however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h. it will never take effective in the board configuration file for this kind of code : #ifdef CONFIG_FSL_SATA_V2 ... #endif To solve this problem, move CONFIG_FSL_SATA_V2 to board configuration header file. This patch reverts Timur's commit:3e0529f742e893653848494ffb9f7cd0d91304bf Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
parent
d607b9684b
commit
9760b274df
@ -137,7 +137,6 @@
|
|||||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
|
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
|
||||||
#define CONFIG_TSECV2
|
#define CONFIG_TSECV2
|
||||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||||
#define CONFIG_FSL_SATA_V2
|
|
||||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||||
@ -181,7 +180,6 @@
|
|||||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
||||||
#define CONFIG_TSECV2
|
#define CONFIG_TSECV2
|
||||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||||
#define CONFIG_FSL_SATA_V2
|
|
||||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||||
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
||||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||||
@ -194,7 +192,6 @@
|
|||||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
|
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
|
||||||
#define CONFIG_TSECV2
|
#define CONFIG_TSECV2
|
||||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||||
#define CONFIG_FSL_SATA_V2
|
|
||||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||||
@ -248,7 +245,6 @@
|
|||||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
|
||||||
#define CONFIG_TSECV2
|
#define CONFIG_TSECV2
|
||||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||||
#define CONFIG_FSL_SATA_V2
|
|
||||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||||
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
|
||||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||||
@ -324,7 +320,6 @@
|
|||||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||||
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
||||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||||
#define CONFIG_FSL_SATA_V2
|
|
||||||
#define CONFIG_SYS_NUM_FMAN 1
|
#define CONFIG_SYS_NUM_FMAN 1
|
||||||
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
||||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||||
@ -357,7 +352,6 @@
|
|||||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||||
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
||||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||||
#define CONFIG_FSL_SATA_V2
|
|
||||||
#define CONFIG_SYS_NUM_FMAN 1
|
#define CONFIG_SYS_NUM_FMAN 1
|
||||||
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
||||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||||
@ -435,7 +429,6 @@
|
|||||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||||
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
||||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||||
#define CONFIG_FSL_SATA_V2
|
|
||||||
#define CONFIG_SYS_NUM_FMAN 1
|
#define CONFIG_SYS_NUM_FMAN 1
|
||||||
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
||||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||||
|
@ -553,6 +553,7 @@ extern unsigned long get_sdram_size(void);
|
|||||||
|
|
||||||
/* SATA */
|
/* SATA */
|
||||||
#define CONFIG_FSL_SATA
|
#define CONFIG_FSL_SATA
|
||||||
|
#define CONFIG_FSL_SATA_V2
|
||||||
#define CONFIG_LIBATA
|
#define CONFIG_LIBATA
|
||||||
|
|
||||||
#ifdef CONFIG_FSL_SATA
|
#ifdef CONFIG_FSL_SATA
|
||||||
|
@ -360,6 +360,7 @@
|
|||||||
/* SATA */
|
/* SATA */
|
||||||
#define CONFIG_LIBATA
|
#define CONFIG_LIBATA
|
||||||
#define CONFIG_FSL_SATA
|
#define CONFIG_FSL_SATA
|
||||||
|
#define CONFIG_FSL_SATA_V2
|
||||||
|
|
||||||
#define CONFIG_SYS_SATA_MAX_DEVICE 2
|
#define CONFIG_SYS_SATA_MAX_DEVICE 2
|
||||||
#define CONFIG_SATA1
|
#define CONFIG_SATA1
|
||||||
|
@ -566,8 +566,10 @@ unsigned long get_board_sys_clk(unsigned long dummy);
|
|||||||
#endif /* CONFIG_PCI */
|
#endif /* CONFIG_PCI */
|
||||||
|
|
||||||
/* SATA */
|
/* SATA */
|
||||||
|
#define CONFIG_FSL_SATA_V2
|
||||||
|
|
||||||
|
#ifdef CONFIG_FSL_SATA_V2
|
||||||
#define CONFIG_FSL_SATA
|
#define CONFIG_FSL_SATA
|
||||||
#ifdef CONFIG_FSL_SATA
|
|
||||||
#define CONFIG_LIBATA
|
#define CONFIG_LIBATA
|
||||||
|
|
||||||
#define CONFIG_SYS_SATA_MAX_DEVICE 2
|
#define CONFIG_SYS_SATA_MAX_DEVICE 2
|
||||||
|
@ -32,6 +32,7 @@
|
|||||||
|
|
||||||
#define CONFIG_MMC
|
#define CONFIG_MMC
|
||||||
#define CONFIG_NAND_FSL_ELBC
|
#define CONFIG_NAND_FSL_ELBC
|
||||||
|
#define CONFIG_FSL_SATA_V2
|
||||||
#define CONFIG_PCIE3
|
#define CONFIG_PCIE3
|
||||||
#define CONFIG_PCIE4
|
#define CONFIG_PCIE4
|
||||||
#define CONFIG_SYS_DPAA_RMAN
|
#define CONFIG_SYS_DPAA_RMAN
|
||||||
|
@ -32,6 +32,7 @@
|
|||||||
|
|
||||||
#define CONFIG_MMC
|
#define CONFIG_MMC
|
||||||
#define CONFIG_NAND_FSL_ELBC
|
#define CONFIG_NAND_FSL_ELBC
|
||||||
|
#define CONFIG_FSL_SATA_V2
|
||||||
#define CONFIG_PCIE3
|
#define CONFIG_PCIE3
|
||||||
#define CONFIG_PCIE4
|
#define CONFIG_PCIE4
|
||||||
#define CONFIG_SYS_FSL_RAID_ENGINE
|
#define CONFIG_SYS_FSL_RAID_ENGINE
|
||||||
|
Loading…
Reference in New Issue
Block a user