update/fix IXDP425 / IXDPG425 boards

Signed-off-by: Michael Schwingen <michael@schwingen.org>
This commit is contained in:
Michael Schwingen 2011-05-23 00:00:10 +02:00 committed by Albert ARIBAUD
parent 10c9787e68
commit 973af335e6
6 changed files with 276 additions and 517 deletions

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@ -1,2 +0,0 @@
#
CONFIG_SYS_TEXT_BASE = 0x00f80000

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@ -1,427 +0,0 @@
/*
* (C) Copyright 2001
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/byteorder/swab.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Board support for 1 or 2 flash devices */
#undef FLASH_PORT_WIDTH32
#define FLASH_PORT_WIDTH16
#ifdef FLASH_PORT_WIDTH16
#define FLASH_PORT_WIDTH ushort
#define FLASH_PORT_WIDTHV vu_short
#define SWAP(x) x
#else
#define FLASH_PORT_WIDTH ulong
#define FLASH_PORT_WIDTHV vu_long
#define SWAP(x) __swab32(x)
#endif
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define mb() __asm__ __volatile__ ("" : : : "memory")
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (FPW * addr, flash_info_t * info);
static int write_data (flash_info_t * info, ulong dest, FPW data);
static void flash_get_offsets (ulong base, flash_info_t * info);
void inline spin_wheel (void);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
int i;
ulong size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
switch (i) {
case 0:
flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
break;
default:
panic ("configured too many flash banks!\n");
break;
}
size += flash_info[i].size;
}
/* Protect monitor and environment sectors
*/
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start,
&flash_info[0]);
flash_protect (FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
return size;
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
return;
}
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
info->protect[i] = 0;
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_INTEL:
printf ("INTEL ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F128J3A:
printf ("28F128J3A\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
}
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (FPW * addr, flash_info_t * info)
{
volatile FPW value;
/* Write auto select command: read Manufacturer ID */
addr[0x5555] = (FPW) 0x00AA00AA;
addr[0x2AAA] = (FPW) 0x00550055;
addr[0x5555] = (FPW) 0x00900090;
mb ();
value = addr[0];
switch (value) {
case (FPW) INTEL_MANUFACT:
info->flash_id = FLASH_MAN_INTEL;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
return (0); /* no or unknown flash */
}
mb ();
value = addr[1]; /* device ID */
switch (value) {
case (FPW) INTEL_ID_28F128J3A:
info->flash_id += FLASH_28F128J3A;
info->sector_count = 128;
info->size = 0x02000000;
break; /* => 16 MB */
default:
info->flash_id = FLASH_UNKNOWN;
break;
}
if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
ulong type;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
type = (info->flash_id & FLASH_VENDMASK);
if ((type != FLASH_MAN_INTEL)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf ("\n");
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
FPWV *addr = (FPWV *) (info->start[sect]);
FPW status;
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
reset_timer_masked ();
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
*addr = (FPW) 0x00D000D0; /* erase confirm */
while (((status =
*addr) & (FPW) 0x00800080) !=
(FPW) 0x00800080) {
if (get_timer_masked () >
CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
rcode = 1;
break;
}
}
*addr = (FPW) 0x00500050; /* clear status register cmd. */
*addr = (FPW) 0x00FF00FF; /* resest to read mode */
printf (" done\n");
}
}
return rcode;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
* 4 - Flash not identified
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp;
FPW data;
int count, i, l, rc, port_width;
if (info->flash_id == FLASH_UNKNOWN) {
return 4;
}
/* get lower word aligned address */
#ifdef FLASH_PORT_WIDTH16
wp = (addr & ~1);
port_width = 2;
#else
wp = (addr & ~3);
port_width = 4;
#endif
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i < port_width && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
return (rc);
}
wp += port_width;
}
/*
* handle word aligned part
*/
count = 0;
while (cnt >= port_width) {
data = 0;
for (i = 0; i < port_width; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
return (rc);
}
wp += port_width;
cnt -= port_width;
if (count++ > 0x800) {
spin_wheel ();
count = 0;
}
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return (write_data (info, wp, SWAP (data)));
}
/*-----------------------------------------------------------------------
* Write a word or halfword to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_data (flash_info_t * info, ulong dest, FPW data)
{
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
printf ("not erased at %08lx (%lx)\n", (ulong) addr,
(ulong) * addr);
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
*addr = (FPW) 0x00400040; /* write setup */
*addr = data;
/* arm simple, non interrupt dependent timer */
reset_timer_masked ();
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
}
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (0);
}
void inline spin_wheel (void)
{
static int p = 0;
static char w[] = "\\/-";
printf ("\010%c", w[p]);
(++p == 3) ? (p = 0) : 0;
}

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@ -33,24 +33,82 @@
#include <malloc.h>
#include <netdev.h>
#include <asm/arch/ixp425.h>
#include <asm/io.h>
#ifdef CONFIG_PCI
#include <pci.h>
#include <asm/arch/ixp425pci.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#define IXDP425_LED_PORT 0x52000000 /* 4-digit hex display */
int board_early_init_f(void)
{
/* CS2: LED port */
writel(0xbcff0002, IXP425_EXP_CS2);
writew(0x0001, IXDP425_LED_PORT); /* output postcode to LEDs */
return 0;
}
#ifdef CONFIG_PCI
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_ixpdp425_config_table[] = {
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, PCI_ANY_ID,
pci_cfgfunc_config_device,
{ 0x400,
0x40000000,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x01, PCI_ANY_ID,
pci_cfgfunc_config_device,
{ 0x800,
0x40010000,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x02, PCI_ANY_ID,
pci_cfgfunc_config_device,
{ 0xc00,
0x40020000,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x03, PCI_ANY_ID,
pci_cfgfunc_config_device,
{ 0x1000,
0x40030000,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
{ }
};
#endif
struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
config_table: pci_ixpdp425_config_table,
#endif
};
#endif /* CONFIG_PCI */
/*
* Miscelaneous platform dependent initialisations
*/
int board_init (void)
int board_init(void)
{
writew(0x0002, IXDP425_LED_PORT); /* output postcode to LEDs */
#ifdef CONFIG_IXDPG425
/* arch number of IXDP */
gd->bd->bi_arch_number = MACH_TYPE_IXDPG425;
#else
/* arch number of IXDP */
gd->bd->bi_arch_number = MACH_TYPE_IXDP425;
#endif
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
#ifdef CONFIG_IXDPG425
/* arch number of IXDP */
gd->bd->bi_arch_number = MACH_TYPE_IXDPG425;
/*
* Get realtek RTL8305 switch and SLIC out of reset
*/
@ -60,19 +118,56 @@ int board_init (void)
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SLIC_RESET_N);
/*
* Setup GPIO's for PCI INTA & INTB
* Setup GPIOs for PCI INTA & INTB
*/
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA_N);
GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA_N);
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB_N);
GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB_N);
/*
* Setup GPIO's for 33MHz clock output
*/
*IXP425_GPIO_GPCLKR = 0x01FF01FF;
/* Setup GPIOs for 33MHz clock output */
writel(0x01FF01FF, IXP425_GPIO_GPCLKR);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
/* set GPIO8..11 interrupt type to active low */
writel((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1, IXP425_GPIO_GPIT2R);
/* clear pending interrupts */
writel(-1, IXP425_GPIO_GPISR);
/* assert PCI reset */
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_SLIC_RESET_N);
udelay(533);
/* deassert PCI reset */
GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SLIC_RESET_N);
udelay(533);
#else /* IXDP425 */
/* Setup GPIOs for 33MHz ExpBus and PCI clock output */
writel(0x01FF01FF, IXP425_GPIO_GPCLKR);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_RESET_N);
/* set GPIO8..11 interrupt type to active low */
writel((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1, IXP425_GPIO_GPIT2R);
/* clear pending interrupts */
writel(-1, IXP425_GPIO_GPISR);
/* assert PCI reset */
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PCI_RESET_N);
udelay(533);
/* deassert PCI reset */
GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_PCI_RESET_N);
udelay(533);
#endif
return 0;
@ -98,30 +193,46 @@ int checkboard(void)
}
putc('\n');
return (0);
return 0;
}
int dram_init (void)
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return (0);
/* we can only map 64MB via PCI, so we limit memory
until a better solution is implemented. */
#ifdef CONFIG_PCI
gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 64<<20);
#else
gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 256<<20);
#endif
return 0;
}
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
extern struct pci_controller hose;
extern void pci_ixp_init(struct pci_controller * hose);
#ifdef CONFIG_PCI
void pci_init_board(void)
{
extern void pci_ixp_init (struct pci_controller *hose);
pci_ixp_init(&hose);
}
/*
* dev 0 on the PCI bus is not the host bridge, so we have to override
* these functions in order to not skip PCI slot 0 during configuration.
*/
int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
{
return 0;
}
int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
{
return 1;
}
#endif
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
#ifdef CONFIG_PCI
pci_eth_init(bis);
#endif
return cpu_eth_init(bis);
}

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@ -173,7 +173,7 @@ actux3 arm ixp
actux4 arm ixp
dvlhost arm ixp
ixdp425 arm ixp
ixdpg425 arm ixp
ixdpg425 arm ixp ixdp425
lpd7a400 arm lh7a40x lpd7a40x
lpd7a404 arm lh7a40x lpd7a40x
balloon3 arm pxa

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@ -36,12 +36,19 @@
#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
/*
* select serial console configuration
*/
#define CONFIG_IXP_SERIAL
#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOARD_EARLY_INIT_F 1
/***************************************************************
* U-boot generic defines start here.
***************************************************************/
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/*
* Size of malloc() pool
*/
@ -50,9 +57,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
/*
* BOOTP options
*/
@ -61,38 +65,33 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
/* Command line configuration. */
#include <config_cmd_default.h>
#define CONFIG_CMD_ELF
#define CONFIG_CMD_PCI
#define CONFIG_PCI
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#define CONFIG_PCI_PNP
#define CONFIG_IXP_PCI
#define CONFIG_NET_MULTI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI_ENUM
#define CONFIG_EEPRO100
#endif
#define CONFIG_BOOTDELAY 3
/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b*/
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.0.21
#define CONFIG_SERVERIP 192.168.0.148
#define CONFIG_BOOTCOMMAND "bootm 50040000"
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
#define CONFIG_CMDLINE_TAG
#define CONFIG_BOOTCOMMAND "run boot_flash"
/* enable passing of ATAGs */
#define CONFIG_CMDLINE_TAG 1
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
@ -103,10 +102,13 @@
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */
/* timer clock - 2* OSC_IN system clock */
#define CONFIG_IXP425_TIMER_CLK 66666666
#define CONFIG_SYS_HZ 1000
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x00010000
#define CONFIG_SYS_HZ 3333333 /* spec says 66.666 MHz, but it appears to be 33 */
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
@ -115,10 +117,6 @@
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/***************************************************************
* Platform/Board specific defines start here.
@ -129,71 +127,145 @@
*/
/*
* select serial console configuration
*/
#define CONFIG_IXP_SERIAL
#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
/*
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
#define CONFIG_SYS_TEXT_BASE 0x50000000
#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */
#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
#define PHYS_FLASH_BANK_SIZE 0x00800000 /* 8 MB Banks */
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
#define CONFIG_SYS_DRAM_BASE 0x00000000
#define CONFIG_SYS_DRAM_SIZE 0x01000000
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_BOARD_SIZE_LIMIT 262144
/*
* Expansion bus settings
*/
#define CONFIG_SYS_EXP_CS0 0xbcd23c42
/* Expansion bus settings */
#define CONFIG_SYS_EXP_CS0 0xbcd23c42
/* SDRAM settings */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/*
* SDRAM settings
*/
#define CONFIG_SYS_SDR_CONFIG 0xd
#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
/*
* GPIO settings
*/
/*
* FLASH and environment organization
*/
/*
* FLASH and environment organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000)
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Use common CFI driver */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
/* no byte writes on IXP4xx */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Ethernet */
/* include IXP4xx NPE support */
#define CONFIG_IXP4XX_NPE 1
#define CONFIG_NET_MULTI 1
/* NPE0 PHY address */
#define CONFIG_PHY_ADDR 0
/* NPE1 PHY address (HW Release E only) */
#define CONFIG_PHY1_ADDR 1
/* MII PHY management */
#define CONFIG_MII 1
/* Number of ethernet rx buffers & descriptors */
#define CONFIG_SYS_RX_ETH_BUFFER 16
#define CONFIG_HAS_ETH1 1
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#undef CONFIG_CMD_NFS
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_EXTRA_ENV_SETTINGS \
"npe_ucode=50060000\0" \
"mtd=IXP4XX-Flash.0:256k(uboot),128k(env),128k(ucode),2048k(linux),-(root)\0" \
"kerneladdr=50080000\0" \
"kernelfile=ixdp425/uImage\0" \
"rootfile=ixdp425/rootfs\0" \
"rootaddr=50280000\0" \
"loadaddr=10000\0" \
"updateboot_ser=mw.b 10000 ff 40000;" \
" loady ${loadaddr};" \
" run eraseboot writeboot\0" \
"updateboot_net=mw.b 10000 ff 40000;" \
" tftp ${loadaddr} ixdp425/u-boot.bin;" \
" run eraseboot writeboot\0" \
"eraseboot=protect off 50000000 5003ffff;" \
" erase 50000000 5003ffff\0" \
"writeboot=cp.b 10000 50000000 ${filesize}\0" \
"updateucode=loady;" \
" era ${npe_ucode} +${filesize};" \
" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
"updateroot=tftp ${loadaddr} ${rootfile};" \
" era ${rootaddr} +${filesize};" \
" cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
"updatekern=tftp ${loadaddr} ${kernelfile};" \
" era ${kerneladdr} +${filesize};" \
" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
"boot_flash=run flashargs addtty addeth;" \
" bootm ${kerneladdr}\0" \
"boot_net=run netargs addtty addeth;" \
" tftpboot ${loadaddr} ${kernelfile};" \
" bootm\0"
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
/*
* GPIO settings
*/
#define CONFIG_SYS_GPIO_UTOPIA_GPIO1 0
#define CONFIG_SYS_GPIO_UTOPIA_IRQ_N 1
#define CONFIG_SYS_GPIO_HSS1_IRQ_N 2
#define CONFIG_SYS_GPIO_HSS0_IRQ_N 3
#define CONFIG_SYS_GPIO_ETH0_IRQ_N 4
#define CONFIG_SYS_GPIO_ETH1_IRQ_N 5
#define CONFIG_SYS_GPIO_I2C_SCL 6
#define CONFIG_SYS_GPIO_I2C_SDA 7
#define CONFIG_SYS_GPIO_PCI_INTD_N 8
#define CONFIG_SYS_GPIO_PCI_INTC_N 9
#define CONFIG_SYS_GPIO_PCI_INTB_N 10
#define CONFIG_SYS_GPIO_PCI_INTA_N 11
#define CONFIG_SYS_GPIO_UTOPIA_GPIO0 12
#define CONFIG_SYS_GPIO_PCI_RESET_N 13
#define CONFIG_SYS_GPIO_PCI_CLK 14
#define CONFIG_SYS_GPIO_EXTBUS_CLK 15
#endif /* __CONFIG_H */

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@ -53,9 +53,6 @@
/*
* Misc configuration options
*/
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */
#define CONFIG_TIMER_IRQ
#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
#define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */
@ -115,6 +112,7 @@
#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */
#define CONFIG_IXP425_TIMER_CLK 66666666
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
/* valid baudrates */
@ -179,6 +177,8 @@
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
#define CONFIG_SYS_TEXT_BASE 0x50000000
#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */
#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
@ -248,4 +248,9 @@
*/
#define CONFIG_SYS_CACHELINE_SIZE 32
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */