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zynqmp: gem: Flush the rx buffers while transmitting
Flush and invalidate the rx buffers while sending the tx packet it self as armv8 does flush also while doing invalidation. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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8a584c8a7f
commit
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@ -20,6 +20,7 @@
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#include <phy.h>
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#include <phy.h>
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#include <miiphy.h>
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#include <miiphy.h>
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#include <watchdog.h>
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#include <watchdog.h>
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#include <asm/system.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/sys_proto.h>
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@ -408,6 +409,11 @@ static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
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addr &= ~(ARCH_DMA_MINALIGN - 1);
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addr &= ~(ARCH_DMA_MINALIGN - 1);
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size = roundup(len, ARCH_DMA_MINALIGN);
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size = roundup(len, ARCH_DMA_MINALIGN);
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flush_dcache_range(addr, addr + size);
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flush_dcache_range(addr, addr + size);
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addr = (u32)priv->rxbuffers;
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addr &= ~(ARCH_DMA_MINALIGN - 1);
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size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
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flush_dcache_range(addr, addr + size);
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barrier();
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barrier();
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/* Start transmit */
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/* Start transmit */
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@ -443,8 +449,6 @@ static int zynq_gem_recv(struct eth_device *dev)
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if (frame_len) {
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if (frame_len) {
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u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
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u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
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addr &= ~(ARCH_DMA_MINALIGN - 1);
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addr &= ~(ARCH_DMA_MINALIGN - 1);
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u32 size = roundup(frame_len, ARCH_DMA_MINALIGN);
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invalidate_dcache_range(addr, addr + size);
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net_process_received_packet((u8 *)addr, frame_len);
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net_process_received_packet((u8 *)addr, frame_len);
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@ -518,7 +522,7 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
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priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
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priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
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memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
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memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
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/* Align bd_space to 1MB */
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/* Align bd_space to MMU_SECTION_SHIFT */
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bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
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bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
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mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
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mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
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BD_SPACE, DCACHE_OFF);
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BD_SPACE, DCACHE_OFF);
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