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https://github.com/brain-hackers/u-boot-brain
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soc: keystone_serdes: enhance to use cmu/comlane/lane specific configurations
Enhance the driver to use cmu/comlane/lane specific configurations instead of 1 big array of configuration. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This commit is contained in:
Hao Zhang
Tom Rini
parent
a43febde44
commit
95f74dad91
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@ -79,6 +79,9 @@
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#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000
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#define KS2_DDR3B_DDRPHYC 0x02328000
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/* SGMII SerDes */
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#define KS2_LANES_PER_SGMII_SERDES 4
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/* Number of DSP cores */
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#define KS2_NUM_DSPS 8
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@ -177,6 +177,9 @@ typedef volatile unsigned int *dv_reg_p;
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#define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
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/* SGMII SerDes */
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#define KS2_SGMII_SERDES_BASE 0x0232a000
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#ifdef CONFIG_SOC_K2HK
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#include <asm/arch/hardware-k2hk.h>
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#endif
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@ -9,92 +9,94 @@
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#include <common.h>
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#define SERDES_LANE_REGS(x) (0x0200 + (0x200 * (x)))
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struct serdes_cfg {
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u32 ofs;
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u32 val;
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u32 mask;
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};
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static struct serdes_cfg cfg_cmu_156p25m_5g[] = {
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{0x0000, 0x00800000, 0xffff0000},
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{0x0014, 0x00008282, 0x0000ffff},
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{0x0060, 0x00142438, 0x00ffffff},
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{0x0064, 0x00c3c700, 0x00ffff00},
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{0x0078, 0x0000c000, 0x0000ff00}
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};
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static struct serdes_cfg cfg_comlane_156p25m_5g[] = {
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{0x0a00, 0x00000800, 0x0000ff00},
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{0x0a08, 0x38a20000, 0xffff0000},
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{0x0a30, 0x008a8a00, 0x00ffff00},
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{0x0a84, 0x00000600, 0x0000ff00},
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{0x0a94, 0x10000000, 0xff000000},
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{0x0aa0, 0x81000000, 0xff000000},
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{0x0abc, 0xff000000, 0xff000000},
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{0x0ac0, 0x0000008b, 0x000000ff},
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{0x0b08, 0x583f0000, 0xffff0000},
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{0x0b0c, 0x0000004e, 0x000000ff}
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};
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static struct serdes_cfg cfg_lane_156p25mhz_5g[] = {
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{0x0004, 0x38000080, 0xff0000ff},
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{0x0008, 0x00000000, 0x000000ff},
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{0x000c, 0x02000000, 0xff000000},
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{0x0010, 0x1b000000, 0xff000000},
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{0x0014, 0x00006fb8, 0x0000ffff},
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{0x0018, 0x758000e4, 0xffff00ff},
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{0x00ac, 0x00004400, 0x0000ff00},
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{0x002c, 0x00100800, 0x00ffff00},
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{0x0080, 0x00820082, 0x00ff00ff},
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{0x0084, 0x1d0f0385, 0xffffffff}
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};
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static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask)
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{
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writel(((readl(addr) & (~mask)) | (value & mask)), addr);
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}
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static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size)
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{
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u32 i;
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for (i = 0; i < size; i++)
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ks2_serdes_rmw(base + cfg[i].ofs, cfg[i].val, cfg[i].mask);
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}
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static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane,
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u32 size, u32 lane)
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{
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u32 i;
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for (i = 0; i < size; i++)
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ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane),
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cfg_lane[i].val, cfg_lane[i].mask);
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}
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static int ks2_serdes_init_156p25m_5g(u32 base, u32 num_lanes)
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{
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u32 i;
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ks2_serdes_cfg_setup(base, cfg_cmu_156p25m_5g,
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ARRAY_SIZE(cfg_cmu_156p25m_5g));
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ks2_serdes_cfg_setup(base, cfg_comlane_156p25m_5g,
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ARRAY_SIZE(cfg_comlane_156p25m_5g));
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for (i = 0; i < num_lanes; i++)
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ks2_serdes_lane_config(base, cfg_lane_156p25mhz_5g,
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ARRAY_SIZE(cfg_lane_156p25mhz_5g), i);
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return 0;
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}
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void ks2_serdes_sgmii_156p25mhz_setup(void)
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{
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unsigned int cnt;
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/*
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* configure Serializer/Deserializer (SerDes) hardware. SerDes IP
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* hardware vendor published only register addresses and their values
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* to be used for configuring SerDes. So had to use hardcoded values
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* below.
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*/
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clrsetbits_le32(0x0232a000, 0xffff0000, 0x00800000);
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clrsetbits_le32(0x0232a014, 0x0000ffff, 0x00008282);
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clrsetbits_le32(0x0232a060, 0x00ffffff, 0x00142438);
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clrsetbits_le32(0x0232a064, 0x00ffff00, 0x00c3c700);
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clrsetbits_le32(0x0232a078, 0x0000ff00, 0x0000c000);
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clrsetbits_le32(0x0232a204, 0xff0000ff, 0x38000080);
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clrsetbits_le32(0x0232a208, 0x000000ff, 0x00000000);
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clrsetbits_le32(0x0232a20c, 0xff000000, 0x02000000);
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clrsetbits_le32(0x0232a210, 0xff000000, 0x1b000000);
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clrsetbits_le32(0x0232a214, 0x0000ffff, 0x00006fb8);
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clrsetbits_le32(0x0232a218, 0xffff00ff, 0x758000e4);
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clrsetbits_le32(0x0232a2ac, 0x0000ff00, 0x00004400);
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clrsetbits_le32(0x0232a22c, 0x00ffff00, 0x00200800);
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clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082);
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clrsetbits_le32(0x0232a284, 0xffffffff, 0x1d0f0385);
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clrsetbits_le32(0x0232a404, 0xff0000ff, 0x38000080);
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clrsetbits_le32(0x0232a408, 0x000000ff, 0x00000000);
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clrsetbits_le32(0x0232a40c, 0xff000000, 0x02000000);
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clrsetbits_le32(0x0232a410, 0xff000000, 0x1b000000);
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clrsetbits_le32(0x0232a414, 0x0000ffff, 0x00006fb8);
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clrsetbits_le32(0x0232a418, 0xffff00ff, 0x758000e4);
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clrsetbits_le32(0x0232a4ac, 0x0000ff00, 0x00004400);
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clrsetbits_le32(0x0232a42c, 0x00ffff00, 0x00200800);
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clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082);
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clrsetbits_le32(0x0232a484, 0xffffffff, 0x1d0f0385);
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clrsetbits_le32(0x0232a604, 0xff0000ff, 0x38000080);
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clrsetbits_le32(0x0232a608, 0x000000ff, 0x00000000);
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clrsetbits_le32(0x0232a60c, 0xff000000, 0x02000000);
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clrsetbits_le32(0x0232a610, 0xff000000, 0x1b000000);
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clrsetbits_le32(0x0232a614, 0x0000ffff, 0x00006fb8);
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clrsetbits_le32(0x0232a618, 0xffff00ff, 0x758000e4);
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clrsetbits_le32(0x0232a6ac, 0x0000ff00, 0x00004400);
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clrsetbits_le32(0x0232a62c, 0x00ffff00, 0x00200800);
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clrsetbits_le32(0x0232a680, 0x00ff00ff, 0x00820082);
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clrsetbits_le32(0x0232a684, 0xffffffff, 0x1d0f0385);
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clrsetbits_le32(0x0232a804, 0xff0000ff, 0x38000080);
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clrsetbits_le32(0x0232a808, 0x000000ff, 0x00000000);
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clrsetbits_le32(0x0232a80c, 0xff000000, 0x02000000);
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clrsetbits_le32(0x0232a810, 0xff000000, 0x1b000000);
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clrsetbits_le32(0x0232a814, 0x0000ffff, 0x00006fb8);
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clrsetbits_le32(0x0232a818, 0xffff00ff, 0x758000e4);
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clrsetbits_le32(0x0232a8ac, 0x0000ff00, 0x00004400);
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clrsetbits_le32(0x0232a82c, 0x00ffff00, 0x00200800);
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clrsetbits_le32(0x0232a880, 0x00ff00ff, 0x00820082);
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clrsetbits_le32(0x0232a884, 0xffffffff, 0x1d0f0385);
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clrsetbits_le32(0x0232aa00, 0x0000ff00, 0x00000800);
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clrsetbits_le32(0x0232aa08, 0xffff0000, 0x38a20000);
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clrsetbits_le32(0x0232aa30, 0x00ffff00, 0x008a8a00);
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clrsetbits_le32(0x0232aa84, 0x0000ff00, 0x00000600);
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clrsetbits_le32(0x0232aa94, 0xff000000, 0x10000000);
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clrsetbits_le32(0x0232aaa0, 0xff000000, 0x81000000);
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clrsetbits_le32(0x0232aabc, 0xff000000, 0xff000000);
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clrsetbits_le32(0x0232aac0, 0x000000ff, 0x0000008b);
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clrsetbits_le32(0x0232ab08, 0xffff0000, 0x583f0000);
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clrsetbits_le32(0x0232ab0c, 0x000000ff, 0x0000004e);
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clrsetbits_le32(0x0232a000, 0x000000ff, 0x00000003);
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clrsetbits_le32(0x0232aa00, 0x000000ff, 0x0000005f);
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clrsetbits_le32(0x0232aa48, 0x00ffff00, 0x00fd8c00);
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clrsetbits_le32(0x0232aa54, 0x00ffffff, 0x002fec72);
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clrsetbits_le32(0x0232aa58, 0xffffff00, 0x00f92100);
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clrsetbits_le32(0x0232aa5c, 0xffffffff, 0x00040060);
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clrsetbits_le32(0x0232aa60, 0xffffffff, 0x00008000);
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clrsetbits_le32(0x0232aa64, 0xffffffff, 0x0c581220);
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clrsetbits_le32(0x0232aa68, 0xffffffff, 0xe13b0602);
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clrsetbits_le32(0x0232aa6c, 0xffffffff, 0xb8074cc1);
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clrsetbits_le32(0x0232aa70, 0xffffffff, 0x3f02e989);
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clrsetbits_le32(0x0232aa74, 0x000000ff, 0x00000001);
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clrsetbits_le32(0x0232ab20, 0x00ff0000, 0x00370000);
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clrsetbits_le32(0x0232ab1c, 0xff000000, 0x37000000);
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clrsetbits_le32(0x0232ab20, 0x000000ff, 0x0000005d);
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ks2_serdes_init_156p25m_5g(CONFIG_KS2_SERDES_SGMII_BASE,
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CONFIG_KS2_SERDES_LANES_PER_SGMII);
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/*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/
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clrbits_le32(0x0232a010, 1 << 28);
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@ -319,4 +319,8 @@
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which is NOT applicable for DDR ECC test */
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#define CONFIG_MAX_UBOOT_MEM_SIZE (4 << 20) /* 4 MiB */
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/* SGMII SerDes */
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#define CONFIG_KS2_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE
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#define CONFIG_KS2_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES
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#endif /* __CONFIG_KS2_EVM_H */
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